AD5301

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2.5 V to 5.5 V, 120 μA, 2-Wire Interface, Voltage-Output 8-/10-/12-Bit DACs Data Sheet AD5301/AD5311/AD5321 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©1999–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

AD5301: buffered voltage output 8-bit DAC AD5311: buffered voltage output 10-bit DAC AD5321: buffered voltage output 12-bit DAC 6-lead SOT-23 and 8-lead MSOP packages Micropower operation: 120 μA at 3 V 2-wire (I2C-compatible) serial interface Data readback capability 2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes Power-down to 50 nA at 3 V Reference derived from power supply Power-on reset to 0 V On-chip rail-to-rail output buffer amplifier 3 power-down functions

APPLICATIONS

Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION The AD5301/AD5311/AD53211 are single 8-/10-/12-bit, buff- ered, voltage-output DACs that operate from a single 2.5 V to 5.5 V supply, consuming 120 μA at 3 V . The on-chip output amplifier allows rail-to-rail output swing with a slew rate of 0.7 V/μs. It uses a 2-wire (I2C-compatible) serial interface that operates at clock rates up to 400 kHz. Multiple devices can share the same bus. The reference for the DAC is derived from the power supply inputs and thus gives the widest dynamic output range. These devices incorporate a power-on reset circuit, which ensures that the DAC output powers up to 0 V and remains there until a valid write takes place. The devices contain a power-down feature that reduces the current consumption of the device to 50 nA at 3 V and provides software-selectable output loads while in power-down mode. The low power consumption in normal operation makes these DACs ideally suited to portable battery-operated equipment. The power consumption is 0.75 mW at 5 V and 0.36 mW at 3 V , reducing to 1 μW in all power-down modes. FUNCTIONAL BLOCK DIAGRAM RESISTOR NETWORK BUFFERDAC REGISTER POWER-DOWN LOGIC AD5301/AD5311/AD5321 VDD SCL GND A1* REF POWER-ON RESET PD* SDA *AVAILABLE ON 8-LEAD VERSION ONLY INTERFACE LOGIC 8-/10-/12-BIT DAC VOUT 00927-001 Figure 1. 1 Protected by U.S. Patent No. 5684481.

AD5301/AD5311/AD5321 Data Sheet Rev. C | Page 2 of 24 TABLE OF CONTENTS Bipolar Operation Using the AD5301/ AD5311/AD5321 .... 18

REVISION HISTORY

6/2016—Rev. B to Rev. C 3/2007—Rev. A to Rev. B 11/2003—Rev. 0 to Re v. A 7/1999—Revision 0: Initial Version

Data Sheet AD5301/AD5311/AD5321 Rev. C | Page 3 of 24 SPECIFICATIONS VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. B Version1 Parameter2 Min Typ Max Unit Test Conditions/Comments DC PERFORMANCE3, 4 AD5301 Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes. AD5311 Resolution 10 Bits Relative Accuracy ±0.5 ±4 LSB Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes. AD5321 Resolution 12 Bits Relative Accuracy ±2 ±16 LSB Differential Nonlinearity ±0.3 ±0.8 LSB Guaranteed monotonic by design over all codes. Zero-Code Error 5 20 mV All zeros loaded to DAC, see Figure 12. Full-Scale Error ±0.15 ±1.25 % of FSR All ones loaded to DAC, see Figure 12. Gain Error ±0.15 ±1 % of FSR Zero-Code Error Drift5 –20 μV/°C Gain Error Drift5 −5 ppm of FSR/°C OUTPUT CHARACTERISTICS5 Minimum Output Voltage 0.001 V This is a measure of the minimum drive capability of the output amplifier. Maximum Output Voltage VDD − 0.001 V This is a measure of the maximum drive capability of the output amplifier. DC Output Impedance 1 Ω Short-Circuit Current 50 mA VDD = 5 V. 20 mA VDD = 3 V. Power-Up Time 2.5 μs Coming out of power-down mode. VDD = 5 V. 6 μs Coming out of power-down mode. VDD = 3 V. LOGIC INPUTS (A0, A1, PD)5 Input Current ±1 μA Input Low Voltage, VIL 0.8 V VDD = 5 V ± 10%. 0.6 V VDD = 3 V ± 10%. 0.5 V VDD = 2.5 V. Input High Voltage, VIH 2.4 V VDD = 5 V ± 10%. 2.1 V VDD = 3 V ± 10%. 2.0 V VDD = 2.5 V. Pin Capacitance 3 pF LOGIC INPUTS (SCL, SDA)5 Input High Voltage, VIH 0.7 × VDD VDD + 0.3 V Input Low Voltage, VIL −0.3 +0.3 × VDD V Input Leakage Current, IIN ±1 μA VIN = 0 V to VDD. Input Hysteresis, VHYST 0.05 × VDD V Input Capacitance, CIN 6 pF Glitch Rejection6 50 ns Pulse width of spike suppressed.

AD5301/AD5311/AD5321 Data Sheet Rev. C | Page 4 of 24 B Version1 Parameter2 Min Typ Max Unit Test Conditions/Comments LOGIC OUTPUT (SDA)5 Output Low Voltage, VOL 0.4 V ISINK = 3 mA. 0.6 V ISINK = 6 mA. Three-State Leakage Current ±1 μA Three-State Output Capacitance 6 pF POWER REQUIREMENTS VDD 2.5 5.5 V IDD specification is valid for all DAC codes. IDD (Normal Mode) DAC active and excluding load current. VDD = 4.5 V to 5.5 V 150 250 μA VIH = VDD and VIL = GND. VDD = 2.5 V to 3.6 V 120 220 μA VIH = VDD and VIL = GND. IDD (Power-Down Mode) VDD = 4.5 V to 5.5 V 0.2 1 μA VIH = VDD and VIL = GND. VDD = 2.5 V to 3.6 V 0.05 1 μA VIH = VDD and VIL = GND. 1 Temperature range is as follows: B Version: −40°C to +105°C. 2 See the Terminology section. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); and AD5321 (Code 112 to 4000). 5 Guaranteed by design and characterization, not production tested. 6 Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.

VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. 1 See the Terminology section. 2 Temperature range for the B Version is as follows: –40°C to +105°C. 3 Guaranteed by design and characterization, not production tested. VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 2 Guaranteed by design and characterization, not production tested. 4 tR and tF measured between 0.3 VDD and 0.7 VDD. 5 Cb is the total capacitance of one bus line in picofarads. Figure 2. 2-Wire Serial Interface Timing Diagram

AD5301/AD5311/AD5321 Data Sheet Rev. C | Page 6 of 24 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.1 Table 4. Parameter Rating VDD to GND −0.3 V to +7 V SCL, SDA to GND −0.3 V to VDD + 0.3 V PD, A1, A0 to GND −0.3 V to VDD + 0.3 V VOUT to GND −0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C Power Dissipation (TJ max − TA)/θJA θJA Thermal Impedance 229.6°C/W Power Dissipation (TJ max – TA)/θJA θJA Thermal Impedance 206°C/W Lead Temperature JEDEC Industry Standard Soldering J-STD-020 1 Transient currents of up to 100 mA do not cause SCR latch-up. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

Figure 3. 8-Lead MSOP (RM-8) Pin Configuration Figure 4. 6-Lead SOT-23 (RJ-6) Pin Configuration Table 5. Pin Function Descriptions decoupled with a 10 μF in parallel with a 0.1 μF capacitor to GND. 2 5 A0 Address Input. Sets the least si gnificant bit of the 7-bit slave address. 3 Not applicable A1 Address Input. Sets the second least significant bit of the 7-bit slave address. 4 4 VOUT Buffered Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. shift register. Clock rates of up to 400 kbps can be accommodated in the I2C-compatible interface. readback mode, SDA may be CMOS/TTL driven. 8 1 GND Ground Reference Point for All Circuitry on the Device.

Figure 21. Exiting Power-Down to Midscale

2.47 VOUT (V)

Figure 22. Major-Code Transition Figure 23. Digital Feedthrough

the bits corresponds to the mode of operation of the DAC. Table 6. PD1 and PD0 Operating Modes PD0 may be overridden by the PD pin on the 8-lead version. resistor, or it is left three-stated. Resistor tolerance = ±20%. The output stage is illustrated in Figure 35. Figure 35. Output Stage During Power-Down

ground plane layer, but separating the lines helps. Figure 38. Multiple AD5301 Devices on One Bus

2.90 BSC

0.95 BSC

0.15 MAX

1.45 MAX

Figure 39. 6-Lead Small Outline Transistor Package [SOT-23]

0.65 BSC

1.10 MAX

Figure 40. 8-Lead Mini Small Outline Package [MSOP]

Data Sheet AD5301/AD5311/AD5321 Rev. C | Page 21 of 24 ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding AD5301BRMZ –40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] RM-8 D8B AD5301BRMZ-REEL7 –40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] RM-8 D8B AD5301BRTZ-500RL7 –40°C to +105°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 D8B AD5301BRTZ-REEL7 –40°C to +105°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 D8B AD5311BRMZ –40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] RM-8 D9B AD5311BRMZ-REEL –40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] RM-8 D9B AD5311BRMZ-REEL7 –40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] RM-8 D9B AD5311BRTZ-500RL7 –40°C to +105°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 D9B AD5311BRTZ-REEL7 –40°C to +105°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 D9B AD5321BRM –40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] RM-8 DAB AD5321BRM-REEL7 –40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] RM-8 DAB AD5321BRMZ –40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] RM-8 DAB AD5321BRMZ-REEL –40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] RM-8 DAB AD5321BRMZ-REEL7 –40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] RM-8 DAB AD5321BRTZ-500RL7 –40°C to +105°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 DAB AD5321BRTZ-REEL7 –40°C to +105°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 DAB 1 Z = RoHS Compliant Part.

AD5301/AD5311/AD5321 Data Sheet Rev. C | Page 22 of 24 NOTES

Data Sheet AD5301/AD5311/AD5321 Rev. C | Page 23 of 24 NOTES

AD5301/AD5311/AD5321 Data Sheet Rev. C | Page 24 of 24 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©1999–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00927-0-6/16(C)