AD5300BRT-REEL

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2.7 V to 5.5 V, 140 μA, Rail-to-Rail Output 8-Bit DAC in a SOT-23 AD5300 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved.

FEATURES

6-Lead SOT-23 and 8-Lead MSOP Packages Micropower Operation: 140 μA @ 5 V Power-Down to 200 nA @ 5 V, 50 nA @ 3 V 2.7 V to 5.5 V Power Supply Guaranteed Monotonic by Design Reference Derived from Power Supply Power-On Reset to 0 V

3 Power-Down Functions

Low Power Serial Interface with Schmitt-Triggered Inputs On-Chip Output Buffer Amplifier, Rail-to-Rail Operation SYNC Interrupt Facility Qualified for automotive applications

APPLICATIONS

Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators FUNCTIONAL BLOCK DIAGRAM AD5300 GND SYNC SCLK DIN VDD VOUT OUTPUT BUFFER8-BIT DAC REF (+) REF (–) POWER-ON RESET DAC REGISTER INPUT CONTROL LOGIC POWER-DOWN CONTROL LOGIC RESISTOR NETWORK 00471-001 GENERAL DESCRIPTION The AD5300 is a single, 8-bit buffered voltage output DAC that operates from a single 2.7 V to 5.5 V supply, consuming 115 μA at 3 V . Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The AD5300 uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The reference for the AD5300 1 is derived from the power supply inputs and thus gives the widest dynamic output range. The part incorporates a power-on reset circuit that ensures that the DAC output powers up to 0 V and remains there until a valid write takes place to the device. The part contains a power-down feature that reduces the current consumption of the device to 200 nA at 5 V and provides software selectable output loads while in power- down mode. The part is put into power-down mode over the serial interface. The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is 0.7 mW at 5 V , reducing to 1 μW in power-down mode. The AD5300 is one of a family of pin-compatible DACs. The AD5310 is the 10-bit version, and the AD5320 is the 12-bit version. The AD5300/AD5310/AD5320 are available in 6-lead SOT-23 packages and 8-lead MSOP packages. PRODUCT HIGHLIGHTS 1. Available in 6-lead SOT-23 and 8-lead MSOP packages. 2. Low power, single-supply operation. This part operates from a single 2.7 V to 5.5 V supply and typically consumes 0.35 mW at 3 V and 0.7 mW at 5 V , making it ideal for battery-powered applications. 3. The on-chip output buffer amplifier allows the output of the DAC to swing rail-to-rail with a slew rate of 1 V/μs. 4. Reference derived from the power supply. 5. High speed serial interface with clock speeds up to 30 MHz. Designed for very low power consumption. The interface powers up only during a write cycle. 6. Power-down capability. When powered down, the DAC typically consumes 50 nA at 3 V and 200 nA at 5 V . 1 Patent pending; protected by U.S. Patent No. 5684481.

–2– REV. AD5300–SPECIFICATIONS (VDD = 2.7 V to 5.5 V; RL = 2 k/H9024 to GND; CL = 500 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.) B Version1 Parameter Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE 2 Resolution 8 Bits Relative Accuracy ± 1 LSB See Figure 2. Differential Nonlinearity ± 0.25 LSB Guaranteed Monotonic by Design. See Figure 3. Zero-Code Error +0.5 +3.5 LSB All Zeros Loaded to DAC Register. See Figure 6. Full-Scale Error –0.5 –3.5 LSB All Ones Loaded to DAC Register. See Figure 6. Gain Error ± 1.25 % of FSR Zero-Code Error Drift –20 µV/°C Gain Temperature Coefficient –5 ppm of FSR/°C OUTPUT CHARACTERISTICS 3 Output Voltage Range 0 VDD V Output Voltage Settling Time 4 6 µs 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex). RL = 2 kΩ; 0 pF < CL < 500 pF. See Figure 16. Slew Rate 1 V/ µs Capacitive Load Stability 470 pF R L = ∞. 1000 pF RL = 2 kΩ. Digital-to-Analog Glitch Impulse 20 nV-s 1 LSB Change Around Major Carry. See Figure 19. Digital Feedthrough 0.5 nV-s DC Output Impedance 1 Ω Short-Circuit Current 50 mA VDD = 5 V. 20 mA VDD = 3 V. Power-Up Time 2.5 µs Coming Out of Power-Down Mode. V DD = 5 V. 5 µs Coming Out of Power-Down Mode. V DD = 3 V. LOGIC INPUTS3 Input Current ± 1 µA VINL, Input Low Voltage 0.8 V VDD = 5 V. VINL, Input Low Voltage 0.6 V VDD = 3 V. VINH, Input High Voltage 2.4 V VDD = 5 V. VINH, Input High Voltage 2.1 V VDD = 3 V. Pin Capacitance 3 pF POWER REQUIREMENTS VDD 2.7 5.5 V IDD (Normal Mode) DAC Active and Excluding Load Current. VDD = 4.5 V to 5.5 V 140 250 µAV IH = VDD and VIL = GND. VDD = 2.7 V to 3.6 V 115 200 µAV IH = VDD and VIL = GND. IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V 0.2 1 µAV IH = VDD and VIL = GND. VDD = 2.7 V to 3.6 V 0.05 1 µAV IH = VDD and VIL = GND. POWER EFFICIENCY IOUT/IDD 93 % ILOAD = 2 mA. VDD = 5 V. NOTES 1Temperature range as follows: B Version: –40 °C to +105 °C. 2Linearity calculated using a reduced code range of 4 to 251. Output unloaded. 3Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. D

1All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. Specifications subject to change without notice. Figure 1. Serial Write Operation tions for extended periods may affect device reliability. accumulate on the human body and test equipment and can discharge without detection. precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. PIN CONFIGURATIONS TOP VIEW (Not to Scale) VOUT GND VDD SYNC SCLK DIN AD5300 TOP VIEW (Not to Scale) NC AD5300 SYNCVOUT GNDVDD SCLK DIN NC NC = NO CONNECT SOT-23 MSOP PIN FUNCTION DESCRIPTIONS SOT-23 MSOP Pin No. Pin No. Mnemonic Function 14 V OUT Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. 28 GND Ground Reference Point for All Circuitry on the Part. 31 V DD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and VDD should be decoupled to GND. 47 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 56 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 65 SYNC Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 16th clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. NC 2, 3 NC No Connect. D

–5–REV. TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 2. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 3. Zero-Code Error Zero-code error is a measure of the output error when zero code (00 Hex) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5300 because the output of the DAC cannot go below 0 V. This is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in LSBs. A plot of zero-code error vs. temperature can be seen in Figure 6. Full-Scale Error Full-scale error is a measure of the output error when full- scale code (FF Hex) is loaded to the DAC register. Ideally, the output should be V DD – 1 LSB. Full-scale error is expressed in LSBs. A plot of full-scale error vs. temperature can be seen in Figure 6. Gain Error This is a measure of the span error of the DAC. It is the devia- tion in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Total Unadjusted Error Total unadjusted error (TUE) is a measure of the output error taking into account all the various errors. A typical TUE vs. code plot can be seen in Figure 4. Zero-Code Error Drift This is a measure of the change in zero-code error with a change in temperature. It is expressed in µV/°C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/ °C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-secs and is measured when the digital input code is chan ged by 1 LSB at the major carry transition (7F Hex to 80 Hex). See Figure 19. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-secs and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s, and vice versa. D

Figure 2. Typical INL Plot Figure 5. INL Error and DNL Error Figure 8. Source and Sink Current Figure 3. Typical DNL Plot Figure 6. Zero-Scale Error and Figure 9. Source and Sink Current Figure 4. Typical Total Unadjusted Figure 7. I DD Histogram with

100 VDD = 3V

Figure 10. Supply Current vs. Code

Figure 11. Supply Current vs. Figure 14. Supply Current vs. Logic Figure 17. Power-On Reset to 0 V Figure 12. Supply Current vs.

00 HEX – FF HEX

Figure 15. Full-Scale Settling Time Figure 18. Exiting Power-Down Figure 13. Power-Down Current vs.

40 HEX – C0 HEX

Figure 16. Half-Scale Settling Time

80 HEX TO 7F HEX

Figure 19. Digital-to-Analog Glitch

diagram of the DAC architecture. Figure 20. DAC Architecture to the DAC register; D can range from 0 to 255. Figure 21. Resistor String with a half-scale settling time of 4 µs with the output loaded. timing diagram of a typical write sequence. DAC register contents and/or a change in the mode of operation).

0.8 V, SYNC should be idled low between write sequences for

last four bits are Don’t Cares.

00 NORMAL OPERATION

11 THREE-STATE

Figure 22. Input Register Contents

Figure 24. Output Stage During Power-Down Tx register after the SPORT has been enabled. Figure 25. AD5300 to ADSP-2101/ADSP-2103 Interface Figure 23. SYNC Interrupt Facility 16th falling edge, this acts as an interrupt to the write sequence. change in the operating mode occurs—see Figure 23. put of the DAC while it is in the process of powering up. of the bits corresponds to the mode of operation of the device. part is in power-down mode. There are three different options. tor or a 100 kΩ resistor, or it is left open-circuited (three-stated). The output stage is illus trated in Figure 24.

0.95 BSC

0.15 MAX

0.05 MIN

1.45 MAX

0.95 MIN

0.20 MAX

0.08 MIN

0.50 MAX

0.30 MIN

Figure 33. 6-Lead Small Outline Transistor Package (SOT-23)

0.65 BSC

1.10 MAX

Figure 34. 8-Lead Mini Small Outline Package (MSOP)

Rev. D | Page 13 of 13 ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option Branding AD5300BRM −40°C to +105°C 8-Lead MSOP RM-8 D2B AD5300BRMZ −40°C to +105°C 8-Lead MSOP RM-8 D2B AD5300BRMZ-REEL −40°C to +105°C 8-Lead MSOP RM-8 D2B AD5300BRMZ-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2B AD5300BRT-500RL7 −40°C to +105°C 6-Lead SOT-23 RJ-6 D2B AD5300BRT-REEL −40°C to +105°C 6-Lead SOT-23 RJ-6 D2B AD5300BRT-REEL7 −40°C to +105°C 6-Lead SOT-23 RJ-6 D2B AD5300BRTZ-500RL7 −40°C to +105°C 6-Lead SOT-23 RJ-6 D2B AD5300BRTZ-REEL −40°C to +105°C 6-Lead SOT-23 RJ-6 D2B AD5300BRTZ-REEL7 −40°C to +105°C 6-Lead SOT-23 RJ-6 D2B AD5300WBRTZ-RL7 −40°C to +105°C 6-Lead SOT-23 RJ-6 DG5 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5300WBRTZ-RL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model.

REVISION HISTORY

12/10—Rev. C to Rev. D 11/03—Rev. B to Rev. C ©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D00471-0-12/10(D)