AD52080 ESMT | Alldatasheet
Document overview
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Technical content
Features
Supply voltage range: 3.0 V to 5.8 V Max. 2.5W AGC non-clip function <12mA static operation current <1uA shutdown current 64 steps DC volume control from -60dB to +20dB High Efficiency >87% into 4, and >92% into 8 loudspeaker Over current, under voltage, and over temperature, fully protection Loudspeaker output power @ 10% THD+N 1.7W/CH into 8 loudspeaker 3W/CH into 4 loudspeaker Headphone output power @ 1% THD+N 80mW/CH into 32 headphone
Applications
Monitor audio Portable multimedia devices Mobile phone
Description
The AD52080 is a stereo, filter-less Class-D audio amplifier with a C lass-AB headphone driver also. Operating with 3.0V~5.8V wide power supply range, it delivers 3W/CH power into 4 loudspeaker within 10% THD+N or 80mW/CH power into 32 headphone within 1% THD+N The AD52080 has not only a 64 -step DC volume controller, also with a 2.5W power limiter, which implement with an automatic gain controller (AGC) internally. The AD 52080 is a stereo audio amplifier with high efficiency, which leads to longer battery li fe, less heat sink, smaller board size, lower system cost, and suitable for the notebook and portable multimedia devices application. Typical Application Circuit AD52080 SDB BYPASS INR AGND AGND INL VOLUME MUTE SE/BTLB AGC UVP AVDD OUTNR PVDD OUTPR PGND PGND OUTPL PVDD OUTNL HPOUTR HPOUTL Bead Bead Bead Bead VDD HP Jack VDD VDD Shutdown Control R-ch Input L-ch Input VDD Mute Control HPSPK 0.1uF 1uF 100kΩ 1nF 100 kΩ 100 kΩ 100 kΩ 1uF 1uF 1uF 2.2uF 220uF 220uF 10uF 0.1uF 0.1uF 1nF 1nF 1nF 1nF HPSPK 1kΩ 1kΩ
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 2/18 Pin Assignments OUTNR HPOUTR INR MUTE SE/BTLB AGC AVDD PVDD PVDD 1 2 3 4 5 15 14 13 12 11 SDB BYPASS AGND INL OUTNL HPOUTL UVP OUTPL OUTPR VOLUMEPGND AD52080 TQFN-20L (TOP VIEW) Pin Description PIN NAME QFN-20L DESCRIPTION OUTNR 1 Right channel negative output. HPOUTR 2 Right channel headphone output. SDB 3 Shut-down control, 0=shutdown, internal pull low, 1.5M ohm. BYPASS 4 Bias voltage for power amplifiers. INR 5 Input of right channel power amplifier. AGND 6 Analog circuit’s ground. INL 7 Input of left channel power amplifier. VOLUME 8 Internal gain setting input. MUTE 9 Mute control, high active, internal pull low, 1.3M ohm. SE/BTLB 10 Output mode control, 1=SE mode, 0=BTL mode, internal pull low, 2M ohm. AGC 11 Maximum power output setting. UVP 12 Under voltage protection unit. AVDD 13 Power supply. HPOUTL 14 Left channel headphone output. OUTNL 15 Left channel negative output. PVDD 16 Power supply. OUTPL 17 Left channel positive output. PGND 18 Power amplifier's ground. OUTPR 19 Right channel positive output. PVDD 20 Power supply.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 3/18 Functional Block Diagram AGC Control Volume Control Bias & Reference Under Voltage Detection Mute Control SE/BTL Selection Shutdown Control Oscillator Output Stage Output Stage PVDD OUTPL OUTNL OUTNR HPOUTL OUTPR HPOUTR PVDD SE/BTLB UVP SDB PGNDAGND AVDD VOLUME INR BYPASS AGC MUTE INL
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 4/18
Ordering Information
Product ID Package Packing / MPQ Comments AD52080-HI20NRY TQFN-20L
490 Units / Tray
4900 Units / Small Box
5000 Units / Reel
10000 Units / Small Box
Package Type Device No. θ JA(℃/W) θ JT (℃/W) Ψ JT (℃/W) Exposed Thermal Pad TQFN-20L (4mm x 4mm) AD52080 46 52.8 1.3 Yes (Note 1) Note 1.1: The thermal pad is located at the bottom of the package. To optimize thermal performance, soldering the thermal pad to the PCB’s ground plane is necessary. Note 1.2: θ JA is simulated on a room temperature ( TA=25℃), natural convection environment test board , which is constructed with a thermally efficient, 4 -layers PCB (2S2P). The measurement is simulated using the JEDEC51-5 thermal measurement standard. Note 1.3: θ JT represents the thermal resistance for the heat flow between the chip junction and the package’s top surface. It’s extracted from t he simulation data with obtaining a cold plate on the package top. Note 1.4: ΨJT represents the thermal parameter for the heat flow between the chip junction and the package’s top surface center. It’s extracted from the simulation data for obtainingθ JA, using a procedure described in JESD51-5. Marking Information AD52080 Line 1 : LOGO Line 2 : Product no. Line 3 : Tracking Code PIN1 DOT ESMT AD52080 Tracking Code
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 5/18 Absolute Maximum Ratings SYMBOL PARAMETER MIN MAX UNIT AVDD Power supply for analog circuits 3.0 6 V PVDD Power supply for loudspeaker driver 3.0 6 V Input voltage -0.3 AVDD V Tstg Storage temperature -65 150 oC TJ Operating junction temperature range -40 150 oC TA Ambient operating temperature -40 85 oC RL Minimum Load Resistance for speaker 3.2 Minimum Load Resistance for headphone 16 ESD Human Body Model ±2k V Charged Device Model ±500 General Electrical Characteristics TA=25°C (unless otherwise noted) SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT VDD Supply voltage AVDD and PVDD 3 5.8 V VIH Input high threshold SDB, MUTE and SE/BTLB 1.4 V VIL Input low threshold SDB, MUTE and SE/BTLB 0.6 V IQ Quiescent current BTL, no load 6 12 mA SE, no load 2 4 mA Imute Mute current BTL, no load 2 6 mA SE, no load 2 4 mA Isd Shutdown current BTL mode, unmute 1 uA Iin Input current, Vin=2V SDB, MUTE, VOLUME and SE/BTLB 1.5 uA Fosc Switching frequency VDD=3.0V to 5.5V 400 500 600 kHz Ri Input resistance BTL, Gain=20dB kΩ SE, Gain=3.5dB kΩ Ron Static drain-source on-state resistance PMOS, VDD=5.5V, IL=0.8A 200 mΩ NMOS, VDD=5.5V, IL=0.8A 200 mΩ Tstart Start-up time from shutdown CBYASS=2.2uF 1.4 Sec OTP Over temperature protection 170 oC OTP_Hys OTP hysteresis oC
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 6/18 Electrical Characteristics and Specifications of Loudspeaker Driver VDD=5V, RL=4Gain=20dB , TA=25°C (unless otherwise noted) SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT Po Output power THD+N=1%, RL=4Ω 2.2 2.5 W THD+N=1%, RL=8Ω 1.42 W THD+N=10%, RL=4Ω 3.0 W THD+N=10%, RL=8Ω 1.74 W ƞ Efficiency RL=4Ω, Po=3W RL=8Ω, Po=1.7W THD+N Total harmonic distortion plus noise Fin=1kHz, RL=4Ω, Po=1.7W 0.08 Fin=1kHz, RL=8Ω, Po=1W 0.09 XTLK Crosstalk, channel separation Po=0.2W, RL=4Ω, Fin=1kHz -100 dB PSRR Power supply rejection ratio RL=4Ω, Fin=100Hz -70 dB RL=4Ω, Fin=1kHz -70 dB SNR Signal to noise ratio Vi=1Vrms, RL=8Ω, with A-weighting filter dB Att(mute) Mute attenuation Fin=1kHz, RL=8Ω, Vin=1Vrms_AES17 -105 dB Att(shutdown) Shutdown attenuation Fin=1kHz, RL=8Ω, Vin=1Vrms_AES17 -120 dB Vn Output noise voltage with A-weighting filter, Gain=20dB uVrms Vos_spk Offset voltage RL=4Ω, Gain=20dB 5 30 mV VDD=3.6V, RL=4Gain=20dB , TA=25°C (unless otherwise noted) SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT Po Output power THD+N=1%, RL=4Ω 1.25 W THD+N=1%, RL=8Ω 0.73 W THD+N=10%, RL=4Ω 1.55 W THD+N=10%, RL=8Ω 0.89 W ƞ Efficiency RL=4Ω, Po=1.4W 84.5 THD+N Total harmonic distortion plus noise Fin=1kHz, RL=4Ω, Po=0.8W 0.11 Fin=1kHz, RL=8Ω, Po=0.5W 0.1 XTLK Crosstalk, channel separation Po=0.2W, RL=4Ω, Fin=1kHz -100 dB PSRR Power supply rejection ratio RL=4Ω, Fin=100Hz -70 dB RL=4Ω, Fin=1kHz -70 dB SNR Signal to noise ratio Vi=1Vrms, RL=8Ω, with A-weighting filter dB Att(mute) Mute attenuation Fin=1kHz, RL=8Ω, Vin=1Vrms -100 dB Att(shutdown) Shutdown attenuation Fin=1kHz, RL=8Ω, Vin=1Vrms -120 dB Vn Output noise voltage with A-weighting filter, Gain=20dB uVrms Vos Offset voltage RL=4Ω, Gain=20dB 5 30 mV
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 7/18 Electrical Characteristics and Specifications of Headphone Driver VDD=5V, RL=32Gain=3.5dB, TA=25°C (unless otherwise noted) SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT Po Output power THD+N=1%, RL=32Ω mW THD+N=10%, RL=32Ω 110 mW THD+N Total harmonic distortion plus noise Fin=1kHz, RL=32Ω, Po=42.5mW 0.013 XTLK Crosstalk, channel separation Po=6mW, RL=32Ω, Fin=1kHz -102 dB PSRR Power supply rejection ratio RL=32Ω, Fin=100Hz -70 dB RL=32Ω, Fin=1kHz -70 dB SNR Signal to noise ratio Vo=1Vrms, RL=32Ω, with A-weighting filter dB Att(mute) Mute attenuation Fin=1kHz, RL=32Ω, Vin=1Vrms -85 dB Att(shutdown) Shutdown attenuation Fin=1kHz, RL=32Ω, Vin=1Vrms -75 dB Vn Output noise voltage with A-weighting filter, Gain=3.5dB uVrms
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 8/18 Typical Characteristics Efficiency (Stereo 4 load) / 2ch Efficiency (Stereo 8 load) / 2ch 100 0 0.5 1 1.5 2 2.5 3 Efficiency(%) Output power(W) 5.0V 3.3V 100 0 0.5 1 1.5 2 2.5 3 Efficiency(%) Output power(W) 5.0V 3.3V THD+N vs. Output Power, 4 load ( BTL Mode ) THD+N vs. Output Power, 8 load ( BTL Mode ) 0.01 0.02 0.05 0.1 0.2 0.5 10m 520m 50m 100m 200m 500m 1 2 Output Power(W) Gain=20dB Load=4ohm+33uH FIN=1kHz AES-17(20kHz) THD+N(%) 5.5V 5.0V 3.6V 3.3V T 0.01 0.02 0.05 0.1 0.2 0.5 10m 5 20m 50m 100m 200m 500m 1 2 Output Power(W) Gain=20dB Load=8ohm+66uH FIN=1kHz AES-17(20kHz) THD+N(%) 5.5V 5.0V 3.6V 3.3V THD+N vs. Output Power, 16 load ( SE Mode ) THD+N vs. Output Power, 32 load ( SE Mode ) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 100u 400m 200u 500u 1m 2m 5m 10m 20m 50m 100m 200m Output Power(W) Gain=3.5dB Load=16ohm FIN=1kHz AES-17(20kHz) THD+N(%) 5.5V 5.0V 3.6V 3.3V 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 100u 200m 200u 500u 1m 2m 5m 10m 20m 50m 100m Output Power(W) Gain=3.5dB Load=32ohm FIN=1kHz AES-17(20kHz) THD+N(%) 5.5V 5.0V 3.6V 3.3V
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 9/18 THD + N (%) vs. Frequency, 4 load ( BTL Mode ) THD + N (%) vs. Frequency, 8 load ( BTL Mode ) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 20 20k 50 100 200 500 1k 2k 5k 10k THD+N(%) Frequency(Hz) AV=20dB AV=10dB VDD=5V PO=1.6W Load=4ohm+33uH AES-17(20kHz) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 20 20k 50 100 200 500 1k 2k 5k 10k THD+N(%) Frequency(Hz) AV=20dB AV=10dB VDD=5V PO=0.8W Load=8ohm+66uH AES-17(20kHz) THD + N (%) vs. Frequency, 32 load ( SE Mode ) Cross-Talk ,4 load ( BTL Mode ) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 20 20k 50 100 200 500 1k 2k 5k 10k THD+N(%) Frequency(Hz) VDD=5V PO=42.5mW Load=32ohm AES-17(20kHz) -110 -50 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 20 20k 50 100 200 500 1k 2k 5k 10k Crosstalk(dB) Frequency(Hz) VDD=5V PO=1.6W Load=4ohm+33uH AES-17(20kHz) Right to Left Left to Right Cross-Talk ,8 load ( BTL Mode ) Cross-Talk ,32 load ( SE Mode ) -110 -50 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 20 20k 50 100 200 500 1k 2k 5k 10k Crosstalk(dB) Frequency(Hz) VDD=5V PO=0.5W Load=8ohm+66uH AES-17(20kHz) Right to Left Left to Right -110 -60 -105 -100 -95 -90 -85 -80 -75 -70 -65 20 20k 50 100 200 500 1k 2k 5k 10k Crosstalk(dB) Frequency(Hz) Right to Left Left to Right Noise, 4 load ( BTL Mode ) Noise, 8 load ( SE Mode )
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 10/18 100u 10u 20u 30u 40u 50u 60u 80u 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k VDD=5V Load=4ohm Input AC GND Noise(uV) Frequency(Hz) 100u 10u 20u 30u 40u 50u 60u 80u 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k VDD=5V Load=32ohm Input AC GND Noise(uV) Frequency(Hz) AGC Function Output Power vs. Input AC, 4 load AGC Function Output Power vs. Input AC, 8 load 100m 200m 300m 400m 500m 600m 700m 800m 100m 2 200m 300m 400m 500m 700m 1 Gain=20dB Load=4ohm+33uH VAGC to GND AES-17(20kHz Output Power (W) Input Voltage (Vrms) 100m 200m 300m 400m 500m 600m 700m 800m 100m 2 200m 300m 400m 500m 700m 1 Gain=20dB Load=8ohm+66uH VAGC to GND AES-17(20kHz Output Power (W) Input Voltage (Vrms) Mute Enable ( Gain=20dB ) Mute Release ( Gain=20dB ) Audio Output Mute Audio Outp ut Audio Output Mute Audio Outp ut
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 11/18 Operation Descriptions Volume Control Table AD52080 has built-in a 64-steps DC volume controller, and the volume level is set by VOLUME pin which is ratio of AVDD. AVDD=5V, TA=25 C, no load Step BTL Gain(dB) SE Gain(dB) Recommended Voltage(V) % of AVDD 1 20 3.5 0 0 2 19.6 3.2 0.14 2.8 3 19.2 2.9 0.21 4.2 4 18.8 2.6 0.29 5.8 5 18.4 2.3 0.37 7.4 6 18 2 0.45 9 7 17.6 1.7 0.52 10.4 8 17.2 1.4 0.6 12 9 16.8 1.1 0.68 13.6 10 16.4 0.8 0.76 15.2 11 16 0.5 0.83 16.6 12 15.6 0.1 0.91 18.2 13 15.2 -0.2 0.99 19.8 14 14.8 -0.5 1.07 21.4 15 14.4 -0.8 1.14 22.8 16 14 -1.2 1.22 24.4 17 13.6 -1.5 1.3 26 18 13.2 -1.8 1.38 27.6 19 12.8 -2.2 1.45 29 20 12.4 -2.5 1.53 30.6 21 12 -2.9 1.61 32.2 22 11.6 -3.2 1.69 33.8 23 11.2 -3.6 1.76 35.2 24 10.8 -3.9 1.84 36.8 25 10.4 -4.3 1.92 38.4 26 10 -4.6 2 40 27 9.6 -5 2.07 41.4 28 9.2 -5.4 2.15 43 29 8.8 -5.7 2.23 44.6 30 8.4 -6.1 2.31 46.2 31 8 -6.4 2.38 47.6 32 7.6 -6.8 2.46 49.2 33 7.2 -7.2 2.54 50.8
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 12/18 34 6.8 -7.5 2.62 52.4 35 6.4 -7.9 2.69 53.8 36 6 -8.3 2.77 55.4 37 5.6 -8.6 2.85 57 38 5.2 -9 2.93 58.6 39 4.8 -9.4 3 60 40 4.4 -9.8 3.08 61.6 41 4 -10.1 3.16 63.2 42 3.6 -10.5 3.24 64.8 43 3.2 -10.9 3.31 66.2 44 2.8 -11.3 3.39 67.8 45 2.4 -11.6 3.47 69.4 46 2 -12 3.55 71 47 1.6 -12.4 3.62 72.4 48 1.2 -12.8 3.7 74 49 0.8 -13.1 3.78 75.6 50 0.4 -13.5 3.86 77.2 51 0 -13.9 3.93 78.6 52 -1 -14.9 4.01 80.2 53 -2 -15.8 4.09 81.8 54 -3 -16.8 4.17 83.4 55 -5 -18.8 4.24 84.8 56 -7 -20.7 4.32 86.4 57 -9 -22.7 4.4 88 58 -11 -24.7 4.48 89.6 59 -17 -30.7 4.55 91 60 -23 -36.9 4.63 92.6 61 -29 -43 4.71 94.2 62 -35 -49.3 4.79 95.8 63 -41 -55.3 4.86 97.2 64 -60 -60 5 100
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 13/18 AGC Non-clip Function AD52080 support AGC non-clip function to keep power amplifier performs high quality audio into speakers and to prevent the speakers from damage when higher volume level is selected. Using AGC pin to set the power limited threshold. AGC Setting Limited Output Power 0.45x AVDD ~ AVDD or floating Disable AGC function 0.27x AVDD ~ 0.45xAVDD X0.95RL AGC)2 AVDD(8 Po 2 0V ~ 0.27xAVDD Po(max)= 2.5W into 4Ω Po(max)= 1.35W into 8Ω Short-circuit Protection To protect loudspeaker drivers from over -current damage, AD52080 has built -in short -circuit protection circuit. When the wires connected to loudspeakers are shorted to each other, GND or power supply, overload detectors may activate. Once short circuit is detected, AD52080 would auto recovery while short-circuit is removed. Over Temperature Protection If the internal junction temperature is higher than 170oC, the outputs of loudspeaker drivers will be disabled and at low state. The temperature hysteresis for AD52080 to return to normal operation is about 30oC. Under Voltage Protection (UVP) Under voltage protection can be used to shutdown AD52080 by external circuit to set the AVDD threshold. Below equations shows how to design the UVP threshold. With the condition: R3 >> R1//R2 2135 2136251 R RRRμAHysteresis R RR)RμA-(.oldUVP thresh
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 14/18 Mute control (MUTE) Like shutdown mode, AD52080 ceases output driver, but keeps parts of internal circuits still working. That could provide lower standby current, quick disable and enable power amplifier. AD52080 with volume fade-in/fade-out design during mute process, the relative mute timing diagrams are shown below. Symbol Min. (ms) Typ. (ms) Max. (ms) t1 0 - - t2 0 - - t3 Depend on Gain setting 528 (gain=20dB) 972 t4 1 - - t5 0 - - Bypass Voltage Bypass voltage of AD52080 is equal to AVDD/2 . The external capacitor for this referenced voltage is a critical component and serves several performances.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 15/18
Application information
Input capacitors (Cin) The performance at low frequency (bass) is affected by the corner frequency (f c) of the high -pass filter composed of input resistors (Rin) and input capacitors (Cin), determined in equation (a). And, the resistance of input resistors is different at different volume gain. But there is 20% variation in input resistance from 20% process variation in actual resistance of the inpu t resistors. Typically, a 0.47 F or 1 F ceramic capacitor is suggested. aHzCRf inin c 2 Capacitor on BYPASS (CByp) In order t o reduce low-frequency noise produced by power supply, the capacitor (CVref) on Vref, which is the mid-rail voltage of AVDD, is necessary. It is also good for PSRR. And, to have less annoying pop, the recommended CVref is the same with Cin. Decoupling capacitor Because of the power loss on the trace, which is between the device and decoupling capacitor, the decoupling capacitor should be placed as close to the device PVDD L (PVDDR) and PGNDL (PGNDR) to reduce any parasitic resistor or inductor between them. And, a low ESR ceramic capacitor, typically 1F, is suggested for high frequency transients and as close to AD52080 as possible . For filtering audio band noise signal, a 10F or greater capacitor (tantalum or electrolytic type) is suggested. Headphone DC decoupling capacitors (Chp) The DC decoupling capacitors (C hp) between headphone and HPL/HPR pins are used to remove the DC voltage on the headphone from HPL/HPR. The high pass filter, which is composed of the headphone resistance and the DC decoupling capacitor, attenuates the low frequency audio performance. For 16 headphone, the electrolytic or tantalum capacitor with 100 F or greater is suggested. The relationship between fhc, Rhp and Chp is shown in the below equation (b). bHzCRf hphp hc 2
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 16/18 Package Dimensions TQFN-20L (4mm x 4mm) TOP VIEW D E BOTTOM VIEW L e SIDE VIEW AA3A1 b 16 20 10 6 1111 Min Max Dimention in mm A 0.70 0.85 Min Max A1 0.00 0.05 D2 1.90 2.05 A3 0.18 0.30 E2 1.90 2.05 b 0.18 0.30 D 3.90 4.10 E 3.90 4.10 e L 0.30 0.50 Symbol Dimension in mm
0.50 BSC
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 17/18
Revision History
0.1 2019.04.26 Initial version. 0.2 2020.02.18 Update typical characteristics. Update operation descriptions. Update pin description. 1.0 2020.05.18 Remove” Preliminary” and revision to 1.0 1.1 2020.09.24 Update features. Update typical characteristics. Update operation descriptions. 1.2 2021.05.20 Update Pin Description 1.3 2021.09.09 Update package dimensions 1.4 2022.09.28 Update mute control sequence
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2022 Revision: 1.4 18/18 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves th e right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.