AD5207BRU10-REEL7

AD5207 AD | Alldatasheet

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REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD5207 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 2-Channel, 256-Position Digital Potentiometer FUNCTIONAL BLOCK DIAGRAM RDAC1 REGISTER R RDAC2 REGISTER R POWER- ON RESET LOGIC SERIAL INPUT REGISTER AD5207 8 SDO DGND SDI CS VSS SHDN VDD A1 W1 B1 A2 W2 B2 CLK

FEATURES

256-Position, 2-Channel Potentiometer Replacement 10 k/H9024, 50 k/H9024, 100 k/H9024 Power Shut-Down, Less than 5 /H9262A 2.7 V to 5.5 V Single Supply /H115502.7 V Dual Supply 3-Wire SPI-Compatible Serial Data Input Midscale Preset During Power-On

APPLICATIONS

Mechanical Potentiometer Replacement Stereo Channel Audio Level Control Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Automotive Electronics Adjustment GENERAL DESCRIPTION The AD5207 provides dual channel, 256-position, digitally controlled variable resistor (VR) devices that perform the same electronic adjustment function as a potentiometer or variable resistor. Each channel of the AD5207 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance, between the A Terminal and the wiper or the B Terminal and the wiper. The fixed A-to-B terminal resistance of 10 k Ω, 50 kΩ or 100 kΩ has a ±1% channel-to-channel matching tolerance with a nomi- nal temperature coefficient of 500 ppm/ °C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs and avoids any make-before-b reak or break- before-make operation. Each VR has its own VR latch, which holds its programmed resistance value. These VR latches are updated from an internal serial-to-parallel shift register, which is loaded from a standard 3-wire serial-input digital interface. Ten bits, to make up the data word, are required and clocked into the serial input register. The first two bits are address bits. The following eight bits are the data bits that represent the 256 steps of the resistance value. The reason for two address bits instead of one is to be compatible with similar products such as AD8402 so that drop-in replacement is possible. The address bit determines the corresponding VR latch to be loaded with the data bits during the returned positive edge of CS strobe. A serial data output pin at the opposite end of the serial register allows simple daisy chaining in multiple VR applications without additional external decoding logic. An internal reset block will force the wiper to the midscale posi- tion during every power-up condition. The SHDN pin forces an open circuit on the A Terminal and at the same time shorts the wiper to the B Terminal, achieving a microwatt power shutdown state. When SHDN is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown. The digital interface remains active during shutdown; code changes can be made to produce new wiper positions when the device is resumed from shutdown. The AD5207 is available in 1.1 mm thin TSSOP-14 package, which is suitable for PCMCIA applications. All parts are guaran- teed to operate over the extended industrial temperature range of –40°C to +125°C.

REV. 0–2– AD5207–SPECIFICATIONS ELECTRICAL CHARACTERISTICS 10 k/H9024, 50 k/H9024, 100 k/H9024 VERSION (VDD = 5 V, VSS = 0, VA = 5 V, VB = 0, –40 /H11543C < TA < +125/H11543C unless otherwise noted.) Parameter Symbol Conditions Min Typ 1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential Nonlinearity

2 R-DNL R WB, VA = NC –1 +1 LSB

Resistor Nonlinearity 2 R-INL R WB, VA = NC –1.5 +1.5 LSB Nominal Resistor Tolerance 3 ∆R –30 +30 % Resistance Temperature Coefficient R AB/∆TV AB = VDD, Wiper = No Connect 500 ppm/ °C Wiper Resistance R W IW = 1 V/R, VDD = 5 V 50 100 Ω Nominal Resistance Match ∆R/RO Ch 1 to 2, VAB = VDD, TA = 25°C 0.2 1 % DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Resolution N 8 Bits Integral Nonlinearity 4 INL –1.5 +1.5 LSB Differential Nonlinearity 4 DNL V DD = 5 V, VSS = 0 V –1 +1 LSB Voltage Divider Temperature ∆VW/∆T Code = 80 H 15 ppm/ °C Coefficient Full-Scale Error V WFSE Code = FFH –1.5 LSB Zero-Scale Error V WZSE Code = 00H +1.5 LSB RESISTOR TERMINALS Voltage Range5 VA, B, W |VDD| + |VSS| ≤5.5 V V SS VDD V Capacitance6 AX, BX CA,B f = 1 MHz, Measured to GND, Code = 80H 45 pF Capacitance6 WX CW f = 1 MHz, Measured to GND, Code = 80H 70 pF Shutdown Current 7 IA_SD VA = VDD, VB = 0 V, SHDN = 0 5 µA Shutdown Wiper Resistance R W_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V 200 Ω Common-Mode Leakage I CM VA = VB = VDD/2 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High V IH VDD = 5 V, VSS = 0 V 2.4 V Input Logic Low V IL VDD = 5 V, VSS = 0 V 0.8 V Input Logic High V IH VDD = 3 V, VSS = 0 V 2.1 V Input Logic Low V IL VDD = 3 V, VSS = 0 V 0.6 V Output Logic High V OH RL = 1 kΩ to VDD VDD – 0.1 V Output Logic Low V OL IOL = 1.6 mA, VDD = 5 V 0.4 V Input Current I IL VIN = 0 V or 5 V ±10 µA Input Capacitance 6 CIL 10 pF POWER SUPPLIES Power Single-Supply Range V DD RANGE VSS = 0 V 2.7 5.5 V Power Dual-Supply Range V DD/SS RANGE ±2.2 ±2.7 V Positive Supply Current I DD VIH = VDD or VIL = GND, VSS = 0 V 40 µA Negative Supply Current I SS VIH = VDD or VIL = GND VSS = –2.5 V 40 µA Power Dissipation 8 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 0.2 mW Power Supply Sensitivity, V DD PSS ∆VDD = 5 V ± 10%, VSS = 0 V, Code = 80H 0.01 %/% Power Supply Sensitivity, V SS PSS ∆VSS = –2.5 V ± 10%, VDD = 2.5 V, Code = 80H 0.03 %/% DYNAMIC CHARACTERISTICS 6, 9 Bandwidth –3 dB BW_10 k Ω RAB = 10 kΩ 600 kHz Bandwidth –3 dB BW_50 k Ω RAB = 50 kΩ 125 kHz Bandwidth –3 dB BW_100 k Ω RAB = 100 kΩ 71 kHz Total Harmonic Distortion THD W VA = 1 V rms, VB = 0 V, f = 1 kHz, R AB = 10 kΩ 0.003 % VW Settling Time t S RAB = 10 kΩ/50 kΩ/100 kΩ, ±1 LSB Error Band 2/9/18 µs Resistor Noise Voltage e N_WB RWB = 5 kΩ, f = 1 kHz, RS = 0 9 nV √Hz Crosstalk10 CT VA = 5 V, VB = 0 V –65 dB

REV. 0 AD5207 –4– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5207 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C, unless otherwise noted) IMAX Digital Inputs and Output Voltage to GND . . 0 V, VDD + 0.3 V NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2 Max current is bounded by the maximum current handling of the switches,

maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W Terminals at a given resistance. Please refer to TPC 22 for detail. 3 Package Power Dissipation = (T J Max–TA)/θJA. PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description 1V SS Negative Power Supply, specified for opera- tion from 0 V to –2.7 V. 2 B2 Terminal B of RDAC#2. 3 A2 Terminal A of RDAC#2.

4 W2 Wiper, RDAC#2, addr = 1

5 DGND Digital Ground. 6 SHDN Active Low Input. Terminal A open-circuit and Terminal B shorted to Wiper. Shut- down controls both RDACs #1 and #2. 7 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the address bit, and loaded into the corresponding RDAC register. 8 SDI Serial Data Input. MSB is loaded first. 9 SDO Serial Data Output. Open Drain transistor requires pull-up resistor. 10 CLK Serial Clock Input. Positive Edge Triggered. 11 V DD Positive Power Supply. Specified for opera- tion at 2.7 V to 5.5 V. 12 W1 Wiper, RDAC #1, addr = 0 2. 13 A1 Terminal A of RDAC #1. 14 B1 Terminal B of RDAC #1. Table I. Serial-Data Word Format ADDR DATA B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB 29 28 27 20 NOTES ADDR(RDAC1) = 00; ADDR(RDAC2 = 01). Data loads B9 first into SDI pin. PIN CONFIGURATION TOP VIEW (Not to Scale) B1VSS AD5207 A1B2 W1A2 VDDW2 CLKDGND SDOSHDN SDICS ORDERING GUIDE Temperature Package Package Qty Per Branding Model k /H9024Range Description Option Container Information * AD5207BRU10-REEL7 10 –40 °C to +125°C TSSOP-14 RU-14 1,000 B10 AD5207BRU50-REEL7 50 –40 °C to +125°C TSSOP-14 RU-14 1,000 B50 AD5207BRU100-REEL7 100 –40 °C to +125°C TSSOP-14 RU-14 1,000 B100 *Three lines of information appear on the device. Line 1 lists the part number; Line 2 includes branding information and the ADI logo, and Line 3 contains the date code YYWW.

REV. 0 –5– Typical Performance Characteristics– AD5207 CODE – Decimal /H115460.20 RDNL – LSB 224 /H115460.15 /H115460.10 /H115460.05 0.00 0.05 0.10 0.15 0.20 1921601289664320 256 VDD = 5.5V , VSS = 0V TPC 1. 10 kΩ RDNL vs. Code CODE – Decimal RINL – LSB 224 –0.15 –0.10 –0.05 0.00 0.10 0.20 1921601289664320 256 –0.20 0.15 0.05 VDD = 5.5V , VSS = 0V TPC 2. 10 kΩ RINL vs. Code CODE – Decimal DNL – LSB 224 –0.2 –0.1 0.0 0.3 1921601289664320 256 –0.3 0.1 0.2 VDD = 5.5V , VSS = 0V TPC 3. 10 kΩ DNL vs. Code CODE – Decimal INL – LSB 224 –0.2 –0.1 0.0 0.1 0.3 1921601289664320 256 –0.3 0.2 –0.4 0.4 VDD = 5.5V , VSS = 0V TPC 4. 10 kΩ INL vs. Code VIH – V IDD/ISS – mA 0.01 1.0 0.001 0.1 IDD @ VDD/VSS = 5V/0V IDD @ VDD/VSS = 3V/0V IDD @ VDD/VSS = /H115502.5V ISS @ VDD/VSS = /H115502.5V TPC 5. Supply Current vs. Logic Input Voltage TEMPERA TURE – /H11543C IDD SUPPL Y CURRENT – /H9262A –40 VIL = VSS VIH = VDD18 –20 0 20 40 60 80 100 VDD = 5.5V VDD = 2.7V TPC 6. Supply Current vs. Temperature

REV. 0 AD5207 –6– TEMPERA TURE – /H11543C IA_SD SHUTDOWN CURRENT – nA –40 –2 00 2 04 06 08 0 1 0 0 120 VDD = 5.5V TPC 7. Shutdown Current vs. Temperature VSUPPL Y – V RON – /H9024 160 140 120 100 54321 VDD = 3V VDD = 5V TPC 8. Wiper ON Resistance vs. VSUPPLY FREQUENCY – Hz IDD/ISS – /H9262A 1000 10k 900 800 700 600 500 400 300 200 100 100k 1M 10M CODE FFH ISS @ VDD/VSS = /H115502.5V IDD @ VDD/VSS = /H115502.5V IDD @ VDD/VSS = 5V/0V IDD @ VDD/VSS = 3V/0V TPC 9. 10 kΩ Supply Current vs. Clock Frequency FREQUENCY – Hz IDD/ISS – /H9262A 1000 10k 900 800 700 600 500 400 300 200 100 100k 1M 10M CODE 55H ISS @ VDD/VSS = /H115502.5V IDD @ VDD/VSS = /H115502.5V IDD @ VDD/VSS = 5V/0V IDD @ VDD/VSS = 3V/0V TPC 10. 10 kΩ Supply Current vs. Clock Frequency FREQUENCY – Hz PSRR – dB 100 1k 10k 1M 100k –PSRR @ VDD = 3V DC /H1155010% p-p AC +PSRR @ VDD = 5V DC /H1155010% p-p AC +PSRR @ VDD = 3V DC /H1155010% p-p AC CODE = 80H, VA = VDD, VB = 0V TPC 11. Power Supply Rejection Ratio vs. Frequency FREQUENCY – Hz –54 GAIN – dB 1k 10k 100k 1M –48 –42 –36 –30 –24 –18 –12 –60 DA T A = 01H DA T A = 02H DA T A = 04H DA T A = 08H DA T A = 10H DA T A = 20H DA T A = 40H DA T A = 80H VDD = +2.7V VSS = –2.7V VA = 100mV rms TA = 25/H11543C VA OP42 TPC 12. 10 kΩ Gain vs. Frequency vs. Code

REV. 0 AD5207 –7– FREQUENCY – Hz –54 GAIN – dB 1k 10k 100k 1M –48 –42 –36 –30 –24 –18 –12 –60 DA T A = 80H DA T A = 40H DA T A = 20H DA T A = 10H DA T A = 08H DA T A = 04H DA T A = 02H DA T A = 01H VDD = +2.7V VSS = –2.7V VA = 100mV rms TA = 25/H11543C VA OP42 TPC 13. 50 kΩ Gain vs. Frequency vs. Code FREQUENCY – Hz –54 GAIN – dB 1k 10k 100k 1M –48 –42 –36 –30 –24 –18 –12 –60 DA T A = 01H DA T A = 02H DA T A = 04H DA T A = 08H DA T A = 10H DA T A = 20H DA T A = 40H DA T A = 80H VDD = +2.7V VSS = –2.7V VA = 100mV rms TA = 25/H11543C VA OP42 TPC 14. 100 kΩ Gain vs. Frequency vs. Code FREQUENCY – Hz –12 GAIN – dB 1k 10k 100k 1M –10 10k/H9024 50k/H9024 VDD = 2.7V VSS = 0V VA = 100mV rms DA T A = 80H TA = 25/H11543C 2.7V 1.5V OP42 –14 100k/H9024 TPC 15. –3 dB Bandwidth FREQUENCY – Hz –5.99 GAIN – dB 10k 100k100 1k –6.00 –6.01 –6.02 –6.03 –6.04 –6.05 –6.06 –6.07 –6.08 –6.09 100k/H9024 VDD = +2.7V VSS = –2.7V VA = 100mV rms DA T A = 80H TA = 25/H11543C VA OP42 VB = 0V 10k/H9024 50k/H9024 TPC 16. Normalized Gain Flatness vs. Frequency VW (10mV/DIV) TPC 17. One Position Step Change at Half Scale VOUT (50mV/DIV) VIN (5mV/DIV) TPC 18. Large Signal Settling Time

REV. 0 AD5207 –8– VW (10mV/DIV) TPC 19. Digital Feedthrough vs. Time CODE – Decimal 120 /H1154640 POTENTIOMETER MODE TEMPCO – ppm//H11543C 100 –20 32 64 96 128 160 192 224 256 TPC 20. ∆VWB/∆T Potentiometer Mode Temperature Coefficient CODE – Decimal /H11546500 RHEOST A T MODE TEMPCO – ppm//H11543C 2500 2000 1500 1000 500 32 64 96 128 160 192 224 256 TPC 21. ∆RWB/∆T Rheostat Mode Temperature Coefficient CODE – Decimal 100.0 10.0 0.1 03 2 THEORETICAL IMAX – mA 1.0 64 96 128 160 192 224 256 RAB = 10k/H9024 RAB = 50k/H9024 IWB_MAX TPC 22. IMAX vs. Code

the internal switch contacts can occur. the B Terminal should be let open or tied to the wiper terminal. the following RDAC latch codes. with temperature has a 500 ppm/ °C temperature coefficient. tics of the three available resistor versions 10 k Ω and 50 k Ω. Figure 9. RDAC Circuit Simulation Model for RDAC = 10 kΩ

1 LSB = V+/2N

Figure 10. Potentiometer Divider Nonlinearity Error Test Figure 11. Resistor Position Nonlinearity Error (Rheostat Figure 12. Wiper Resistance Test Circuit Figure 13. Power Supply Sensitivity Test Circuit Figure 14. Inverting Gain Test Circuit Figure 15. Noninverting Gain Test Circuit Figure 16. Gain vs. Frequency Test Circuit Figure 17. Incremental ON Resistance Test Circuit Figure 18. Common-Mode Leakage Current Test Circuit

REV. 0 AD5207 –13– DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE Number Resolution Power of VRs Terminal Interface Nominal (Number Supply Part per Voltage Data Resistance of Wiper Current Number Package Range Control (k /H9024) Positions) (I DD) Packages Comments AD5201 1 ± 3 V, +5.5 V 3-Wire 10, 50 33 40 µA µSOIC-10 Full AC Specs, Dual Supply, Pwr-On-Reset, Low Cost AD5220 1 5.5 V Up/Down 10, 50, 100 128 40 µA PDIP, SO-8, µSOIC-8 No Rollover, Pwr-On-Reset AD7376 1 ± 15 V, +28 V 3-Wire 10, 50, 100, 1000 128 100 µA PDIP-14, SOL-16, Single +28 V or Dual ± 15 V TSSOP-14 Supply Operation AD5200 1 ± 3 V, +5.5 V 3-Wire 10, 50 256 40 µA µSOIC-10 Full AC Specs, Dual Supply, Pwr-On-Reset AD8400 1 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA SO-8 Full AC Specs AD5260 1 ± 5 V, +15 V 3-Wire 20, 50, 200 256 60 µA TSSOP-14 15 V or ± 5 V, TC < 50 ppm/°C AD5241 1 ± 3 V, +5.5 V 2-Wire 10, 100, 1000 256 50 µA SO-14, TSSOP-14 I 2C-Compatible, TC < 50 ppm/°C AD5231* 1 ± 3 V, +5.5 V 3-Wire 10, 50, 100 1024 20 µA TSSOP-16 Nonvolatile Memory, Direct Program, I/D, ± 6 dB Settability AD5222 2 ± 3 V, +5.5 V Up/Down 10, 50, 100, 1000 128 80 µA SO-14, TSSOP-14 No Rollover, Stereo, Pwr-On- Reset, TC < 50 ppm/ °C AD8402 2 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA PDIP, SO-14, Full AC Specs, nA TSSOP-14 Shutdown Current AD5207 2 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 40 µA TSSOP-14 Full AC specs, Dual Supply, Pwr-On-Reset, SDO AD5232* 2 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 20 µA TSSOP-16 Nonvolatile Memory, Direct Program, I/D, ±6 dB Settability AD5235* 2 ± 3 V, +5.5 V 3-Wire 25, 250 1024 20 µA TSSOP-16 Nonvolatile Memory, Direct Program, TC < 50 ppm/ °C AD5242 2 ± 3 V, +5.5 V 2-Wire 10, 100, 1000 256 50 µA SO-16, TSSOP-16 I 2C-Compatible, TC < 50 ppm/°C AD5262* 2 ± 5 V, +15 V 3-Wire 20, 50, 200 256 60 µA TSSOP-16 ± 15 V or ± 5 V, Pwr-On- Reset, TC < 50 ppm/ °C AD5203 4 5.5 V 3-Wire 10, 100 64 5 µA PDIP, SOL-24, Full AC Specs, nA TSSOP-24 Shutdown Current AD5233* 4 ± 3 V, +5.5 V 3-Wire 10, 50, 100 64 20 µA TSSOP-16 Nonvolatile Memory, Direct Program, I/D, ± 6 dB Settability AD5204 4 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 60 µA PDIP, SOL-24, Full AC Specs, Dual Supply, TSSOP-24 Pwr-On-Reset AD8403 4 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA PDIP, SOL-24, Full AC Specs, nA TSSOP-24 Shutdown Current AD5206 6 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 60 µA PDIP, SOL-24, Full AC Specs, Dual Supply, TSSOP-24 Pwr-On-Reset *Future product, consult factory for latest status. Latest Digital Potentiometer Information available at www.analog.com/support/standard_linear/selection_guides/dig_pot.html

REV. 0 AD5207 –14– OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 14-Lead TSSOP (RU-14) 14 8 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30)PIN 1 0.201 (5.10) 0.193 (4.90) SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8/H11543 0/H11543

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–16– C01885–1.5–4/01(0) PRINTED IN U.S.A.