AD52070 ESMT | Alldatasheet
Document overview
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Technical content
Features
Single supply voltage 4.5V ~ 26V for loudspeaker driver Built-in LDO output 5V for others Supports Multiple Output Configurations BTL Mode: 30W/CH into 8at 24 V BTL Mode: 30W/CH into 4at 18 V PBTL Mode: 60W/CH into 4at 24 V PBTL Mode: 45W/CH into 4at 18 V PBTL Mode: 60W/CH into 2at 18 V Loudspeaker performance BTL Mode: 30W/CH into 8 <1% THD+N@24V BTL Mode: 30W/CH into 4 <1% THD+N@18V >90% efficient Cl ass-D operation eliminates need for heat sink Energy Saving Class-D Operation Low Idle Current <23mA Multiple Switching Frequencies AM Avoidance Master/Slave Synchronization 300KHz to 1.2MHz Switching Frequency Differential inputs Four selectable, fixed gain settings Internal oscillator Short-Circuit protection with auto recovery Under-Voltage detection Over-Voltage protection Pop noise and click noise reduction Adjustable Automatic Gain Control or adjustable power limit function for speaker protection Output DC detection for speaker protection Thermal fold-back control Over temperature protection with auto recovery
Applications
TV audio Boom-Box Powered speaker Monitors Consumer Audio Equipment
Description
The AD52070 is a high efficie ncy stereo class -D audio amplifier with adjustable power limit function . It can deliver 30W/CH output power into 4 or 8loudspeaker within 1% THD+N at 24V supply voltage. AD52070 also provides parallel BTL (Mono) application, and it can deliver 60W into 4 loudspeaker at 24V supply voltage. The AD52070 has low idle current mode for battery-powered audio system and h elps to extend the batter y life. The advanced oscillator/PLL circuit employs a multiple switching frequency option to avoid AM interferences . In order to achieve multi-channels application, which the clock slave mode design with, making it possible to synchronize multiple devices. The Automatic Gain Control (AGC) is enabled to prevent output signal from distortion when the input signal exceeds a threshold level. The AGC allows adjustment of maximum output voltage without signal clipping for enhanced speaker protection and audio quality. The power -limit control can provide further limit output power level of amplifier. The adjustable power limit function allows user to set a voltage to limit the amount of current through the speaker. All these functions are p erformed automatically. Output DC detection prevents speaker damage from long-time current stress. AD52070 output short circuit and over temperature protection include auto-recovery feature.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 2/33 Simplified Application Circuit L IN N R IN N S D Z AD 52070 O U T P L O U T N L P V C C G A IN /S L V L IM R A T E 4 .5 V to 26 V P L IM IT L IN P 1 uF R IN P L C F ilte r O U T P R O U T N R G N D 1 uF 1 uF 1 uF A V C C BSPL B S N L BSPR B S N R 0 .22 uF L C F ilte r 0 .22 uF 0 .22 uF 0 .22 uF S Y N C G N D G V D D 1 uF AM 0 AM 1
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 3/33 Pin Assignments G V D D P L IM IT L IM R A T E G A IN /S L V R IN N P V C C G N D O U T P R B S N R O U T N R BSPR 15A V C C L IN N G N D L IN P AM 0 P V C C G N D BSPL O U T P L B S N L AM 1 O U T N L E -T S S O P- 28 L S D Z R IN P ( T O P V IE W ) S Y N C P V C C P V C C Pin Description NAME E-TSSOP -28L TYP DESCRIPTION SDZ 1 DI Shutdown signal for IC (low = disabled, high = operational). Voltage compliance to AVCC. Chip is with internal pull low, 250kohm@normal state, <250ohm@ fault state. RINP 2 AI Positive audio input for right channel. Connect to GND for MONO mode. RINN 3 AI Negative audio input for right channel. Connect to GND for MONO mode. PLIMIT 4 AI Voltage level for AGC or power limiter. Connect a resistor divider from GVDD to GND to set AGC or power limit level. Give VPLIMIT ≦ 2.1V to set AGC or power limit level. Connect to GND to disable AGC or power limit function , and chip will into mute function when connect to GVDD ( ≧ 2.4V). GVDD 5 P 5V regulated output, with a 1uF X7R (or X5R) ceramic decoupling capacito r is necessary. Not to be used as a supply or connected to any components other than the PLIMIT and GAIN/SLV resistor dividers. GAIN/SLV 6 AI Selects gain depending on pin voltage divider. LIMRATE 7 AI Decay speed for clip free for AGC or power limiter. Connect a resistor divider from GVDD to GND to set decay speed. Connect directly to GND to enable power limit function. GND 8 P Power ground. Connect to the thermal pad. LINP 9 AI Positive audio input for left channel. Connect to GND for PBTL mode. LINN 10 AI Negative audio input for left channel. Connect to GND for PBTL mode. AM1 11 DI AM avoidance frequency selection 1. Chip is with internal pull low, 250kohm.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 4/33 AM0 12 DI AM avoidance frequency selection 0. Chip is with internal pull low, 250kohm. SYNC 13 DIO Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV terminal. Chip is at output mode @Master mode; Input mode (HiZ) @Slave mode. AVCC 14 P Analog supply. PVCC 15,16 P High-voltage power supply. BSNL 17 BST Bootstrap I/O for left channel, negative high side FET. OUTNL 18 O Class-D H-bridge negative output for left channel. GND 19 P Power ground. Connect to the thermal pad. OUTPL 20 O Class-D H-bridge positive output for left channel. BSPL 21 BST Bootstrap I/O for left channel, positive high side FET. BSNR 22 BST Bootstrap I/O for right channel, negative high side FET. OUTNR 23 O Class-D H-bridge negative output for right channel. GND 24 P Power ground. Connect to the thermal pad. OUTPR 25 O Class-D H-bridge positive output for right channel. BSPR 26 BST Bootstrap I/O for right channel, positive high side FET. PVCC 27,28 P High-voltage power supply. Thermal Pad P Must be soldered to PCB’s ground plane. AI = Analog input; AO = Analog output; AI/O = Analog Bi-directional (input and output); DI = Digital Input; DO = Digital Output; DI/O = Digital Bi-directional (input and output); P = Power or Ground; BST = Boot Strap
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 5/33
Ordering Information
Product ID Package Packing Comments AD52070-QG28NRR E-TSSOP 28L
2500 Units / Reel
1 Reels / Small Box
Package Type Device No. θJA(℃/W) θ JT(℃/W) Ψ JT(℃/W) Exposed Thermal Pad E-TSSOP 28L AD52070 28 27.1 1.33 Yes (Note 1) Note 1.1: The thermal pad is located at the bottom of the packag e. To optimize thermal performance, soldering the thermal pad to the PCB’s ground plane is necessary. Note 1.2: θ JA is simulated on a room temperature ( TA=25℃), natural convection environment test board, which is constructed with a thermally efficient, 4 -layers PCB (2S2P). The measurement is simulated using the JEDEC51-5 thermal measurement standard. Note 1.3: θ JT represents the thermal resistance for the heat flow between the chip junction and the package’s top surface. It’s extracted from the simulation d ata with obtaining a cold plate on the package top. Note 1.4: ΨJT represents the thermal parameter for the heat flow between the chip junction and the package’s top surface center. It’s extracted from the simulation data for obtainingθ JA, using a procedure described in JESD51-5.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 6/33 PIN 1 DO T ESM T AD 52070 Tracking Code Marking Information AD52070
- Marking Information Line 1：LOGO Line 2：Product No Line 3：Tracking Code Absolute Maximum Ratings Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT PVCC Supply voltage PVCC and AVCC -0.3 30 V VI Interface pin voltage SDZ, AM0 and AM1 -0.3 30 V PLIMIT, GAIN/SLV, SYNC and LIMRATE -0.3 5.5 TA Operating free-air temperature range -40 85 oC TJ Operating junction temperature range -40 150 oC Tstg Storage temperature range -65 150 oC RL Minimum Load Resistance BTL (Stereo, Mono) 3.2 PBTL ＞ 18V 3.2 PBTL ≦ 18V 1.6 ESD Human Body Model ±2k Charged Device Model ±500 Recommended Operating Conditions SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT PVCC Supply voltage PVCC and AVCC 4.5 26 V VIH High-level input voltage SDZ, AM0, AM1 and SYNC 2 V VIL Low-level input voltage SDZ, AM0, AM1 and SYNC 0.8 V IIH High-level input current SDZ, AM0, AM1, SYNC, VI=2V, PVCC=18V 50 uA IIL Low-level input current SDZ, AM0, AM1, SYNC, VI=0.8V, PVCC=18V 5 uA TA Operating free-air temperature -40 85 oC
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 7/33 General Electrical Characteristics PVCC=24V, RL=8TA=25°C (unless otherwise noted) SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT ICC(q) Quiescent supply current SDZ=2V, PWM=400KHz, With load and filter, PVCC=12V 17 mA SDZ=2V, PWM=400KHz, With load and filter, PVCC=24V ICC(SD) Quiescent supply current in shutdown mode SDZ=0.8V, no load, PVCC=12V 20 uA SDZ=0.8V, no load, PVCC=24V 30 RDS(on) Drain-source on-state resistance-High side NMOS PVCC=12V, Id=500mA, TJ=25°C m Drain-source on-state resistance-Low side NMOS |VOS| Class-D output offset voltage (measured differential) PVCC=12V VI=0V, Gain=36dB 1.5 15 mV tON Turn-on time SDZ=2V 10 ms tOFF Turn-off time SDZ=0.8V 10 GVDD Regulator output IGVDD=0.1mA 4.75 5 5.25 V G Gain (Master) R1=5.6k, R2=Open 19 20 21 dB R1=20k, R2=100k 25 26 27 R1=39k, R2=100k 31 32 33 R1=47k, R2=75k 35 36 37 Gain (Slave) R1=51k, R2=51k 19 20 21 dB R1=75k, R2=47k 25 26 27 R1=100k, R2=39k 31 32 33 R1=100k, R2=16k 35 36 37
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 8/33 Application Circuit Example for Stereo 10 uH Speaker 0 .68 uF 0 .68 uF SDZ AD 52070 G N D P V C C P V C C P V C C 220 uF0 .1 uF O U T P R BSPR G V D D 1 uF P L IM IT R P L1R P L21 uF GAIN/SLV LIMRATE 1 uF 1 uF1 K R IN P R IN N 1 uF1 K L IN P L IN N 1 uF SYNC AM0 AM1 220 nF O U T N R B S N R 220 nF 10 uH 0 .68 uF 0 .68 uF O U T P L BSPL 220 nF O U T N L B S N L 220 nF AVCC 10 uH 10 uH R -ch In p u t L -ch In p u t PVCC PVCC PVCC 220 uF 0 .1 uF Speaker 1 uF P V C C 0 .1 uF 10
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 9/33 Application Circuit Example for Mono Mode SDZ AD 52070 G N D P V C C P V C C P V C C 220 uF0 .1 uF G V D D 1 uF P L IM IT R P L1R P L21 uF GAIN/SLV LIMRATE R IN P R IN N 1 uF1 K L IN P L IN N 1 uF SYNC AM0 AM1 10 uH 2 .2 uF 2 .2 uF O U T P L BSPL 220 nF O U T N L B S N L 220 nF AVCC 10 uH L -ch In p u t PVCC PVCC PVCC 220 uF 0 .1 uF Speaker 1 uF P V C C 0 .1 uF 10
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 10/33 Application Circuit Example for PBTL Mode 10 uH Speaker 2 .2 uF SDZ AD 52070 G N D P V C C P V C C P V C C 220 uF0 .1 uF O U T P R BSPR G V D D 1 uF P L IM IT R P L1R P L21 uF GAIN/SLV LIMRATE 1 uF 1 uF1 K R IN P R IN N L IN P L IN N SYNC AM0 AM1 220 nF O U T N R B S N R 220 nF 2 .2 uF O U T P L BSPL 220 nF O U T N L B S N L 220 nF AVCC 10 uH PVCC PVCC PVCC 220 uF 0 .1 uF 1 uF P V C C 0 .1 uF 10
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 11/33 Application Circuit Example for Clock Synchronization (multiple devices) 10uH Speaker 0.68uF 0.68uF SDZ AD52070 (Master) FAULTZ GND MODSEL PVCC PVCC PVCC 220uF0.1uF OUTPR BSPR GVDD 1uF PLIMIT RPL1RPL21uF GAIN/SLV (Setting in Master) LIMRATE 1uF 1uF1K RINP RINN 1uF1K LINP LINN 1uF SYNC AM0 AM1 220nF OUTNR BSNR 220nF 10uH 0.68uF 0.68uF OUTPL BSPL 220nF OUTNL BSNL 220nF AVCC 10uH 10uH R-ch Input L-ch Input PVCC PVCC PVCC 220uF 0.1uF Speaker 10uH Speaker 0.68uF 0.68uF SDZ AD52070 (Slave) GND PVCC PVCC PVCC 220uF0.1uF OUTPR BSPR GVDD 1uF PLIMIT RPL1RPL21uF GAIN/SLV (Setting in Slave) LIMRATE 1uF 1uF1K RINP RINN 1uF1K LINP LINN 1uF SYNC AM0 AM1 220nF OUTNR BSNR 220nF 10uH 0.68uF 0.68uF OUTPL BSPL 220nF OUTNL BSNL 220nF AVCC 10uH 10uH R-ch Input L-ch Input PVCC PVCC PVCC 220uF 0.1uF Speaker 4.7K 47pF 1uF PVCC 0.1uF 10 1uF PVCC 0.1uF 10
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 12/33 Electrical Characteristics and Specifications of Loudspeaker Driver PVCC=24V, RL=8with passive LC low-pass filter in ESMT EVB, fosc=400kHz (unless otherwise noted). SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT PO Output power (BTL) THD+N=0.3%, f=1kHz, PVCC=24V 30 W THD+N=10%, f=1kHz, PVCC=12V 10 THD+N=0.35%, f=1kHz, VCC=21V, 4ohm 30 THD+N=0.95%, f=1kHz, VCC=18V, 4ohm 30 THD+N=10%, f=1kHz, PVCC=12V, 4ohm 19 THD+N=10%, f=1kHz, PVCC=8V, 4ohm 8.5 Output power (PBTL) THD+N=0.27%, f=1kHz, PVCC=24V, 4ohm 60 THD+N=10%, f=1kHz, PVCC=18V, 4ohm 45 THD+N=0.5%, f=1kHz, PVCC=18V, 2ohm 60 THD+N Total harmonic distortion plus noise PVCC=24V, RL=8f=1kHz, PO=15W (half-power) 0.02 PVCC=12V, RL=8f=1kHz, PO=5W (half-power) 0.02 SNR Signal to noise ratio Maximum output at THD+N<1%, f=1kHz, Gain=20dB, a-weighted 103 dB Vn Output integrated noise F=20Hz ~ 20kHz, Gain=20dB, a-weighted filter, RL=8 65 uV KSVR Power Supply Rejection Ratio Vripple=200mVpp at 1kHz, Gain=20dB, inputs ac-grounded -70 dB X-talk Crosstalk F=1kHz, PO=1W, Gain=20dB -80 dB TAGC,AT AGC Attack Time LIMRATE=GVDD (FAST) 0.32 ms/dB LIMRATE=2/3*GVDD (MEDIUM) 2.56 LIMRATE=1/3*GVDD (SLOW) 5.12 TTFB,AT TFB Attack Time LIMRATE=GVDD (FAST) 164 LIMRATE=2/3*GVDD (MEDIUM) 326 LIMRATE=1/3*GVDD (SLOW) 655 TRLS AGC/TFB Release Time LIMRATE=GVDD (FAST) 328 LIMRATE=2/3*GVDD (MEDIUM) 655 LIMRATE=1/3*GVDD (SLOW) 1311 fOSC Oscillator frequency AM1=0, AM0=0 (Low idle current mode) 376 400 424 kHz AM1=0, AM0=1 (Low idle current mode) 470 500 530
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 13/33 AM1=1, AM0=0 (Pure quaternary mode) 1128 1200 1272 AM1=1, AM0=1 (Pure ternary mode) 282 300 318 TFB Thermal Fold-back trip point 150 oC TSENSOR Thermal trip point for over temperature 170 oC Thermal hysteresis 35 oC
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 14/33 Typical Characteristics THD+N vs. Output Power, 8 load (BTL) THD+N vs. Output Power, 4 load (BTL) 0.001 0.01 0.1 10m 100 20m 50m 100m 200m 500m 1 2 5 10 20 50 Gain=26dB Load=8ohm fOSC=400kHz Output Power(W) THD+N(%) 24V 21V 18V 12V 0.001 0.01 0.1 10m 100 20m 50m 100m 200m 500m 1 2 5 10 20 50 Gain=26dB Load=4ohm fOSC=400kHz Output Power(W) THD+N(%) 24V 21V 18V 12V THD+N vs. Output Power, 4 load (PBTL) THD+N vs. Output Power, 2 load (PBTL) 0.001 0.01 0.1 10m 100 20m 50m 100m 200m 500m 1 2 5 10 20 50 Gain=26dB Load=4ohm fOSC=400kHz Output Power(W) THD+N(%) 24V 21V 18V 12V 0.001 0.01 0.1 10m 200 20m 50m 100m 200m 500m 1 2 5 10 20 50 100 Gain=26dB Load=2ohm fOSC=400kHz Output Power(W) THD+N(%) 24V 21V 18V 12V Noise, 24V, 8 load (BTL) Noise, 24V, 4 load (PBTL) Gain=20dB Load=8ohm fOSC=400kHz V Frequency(Hz) 10u 200u 20u 30u 40u 50u 60u 80u 100u 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k Gain=20dB Load=4ohm fOSC=400kHz V Frequency(Hz)
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 15/33 Crosstalk, 24V, 4 load (BTL) Crosstalk, 24V, 8 load (BTL) -140 -50 -130 -120 -110 -100 -90 -80 -70 -60 20 20k 50 100 200 500 1k 2k 5k 10k Gain=26dB Load=4ohm fOSC=400kHz dB Frequency(Hz) Lch to Rch Rch toLch -140 -50 -130 -120 -110 -100 -90 -80 -70 -60 20 20k 50 100 200 500 1k 2k 5k 10k Gain=26dB Load=8ohm fOSC=400kHz dB Frequency(Hz) Lch to Rch Rch toLch Maximum Output Power vs Supply Voltage (BTL) Maximum Output Power vs Supply Voltage (BTL) 0 5 10 15 20 25 30 Output Power (W) PVCC(V) THD+N=10% THD+N=1% Gain=26dB Load=8ohm fOSC=400kHz 2OZ copper PCB 100 0 5 10 15 20 25 30 Output Power (W) PVCC(V) THD+N=10% THD+N=1% Gain=26dB Load=4ohm fOSC=400kHz 2OZ copper PCB Maximum Output Power vs Supply Voltage (PBTL) Maximum Output Power vs Supply Voltage (PBTL) 100 0 5 10 15 20 25 30 Output Power (W) PVCC(V) THD+N=10% THD+N=1% Gain=26dB Load=4ohm fOSC=400kHz 2OZ copper PCB 100 125 150 0 5 10 15 20 25 30 Output Power (W) PVCC(V) Gain=26dB Load=2ohm fOSC=400kHz 2OZ copper PCB THD+N=10% THD+N=1% Note: Dashed Line represent thermally limited regions.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 16/33 THD + N (%) vs. Frequency, 24V, 8 load (BTL) THD + N (%) vs. Frequency, 24V, 4 load (BTL) 0.0001 0.001 0.01 0.1 20 20k 50 100 200 500 1k 2k 5k 10k Gain=26dB Load=8ohm fOSC=400kHz THD+N(%) Frequency(Hz) 20W 10W 0.0001 0.001 0.01 0.1 20 20k 50 100 200 500 1k 2k 5k 10k Gain=26dB Load=4ohm fOSC=400kHz Frequency(Hz) THD+N(%) 30W 20W 10W THD + N (%) vs. Frequency, 24V, 4 load (PBTL) THD + N (%) vs. Frequency, 24V, 2 load (PBTL) 0.0001 0.001 0.01 0.1 20 20k 50 100 200 500 1k 2k 5k 10k Gain=26dB Load=4ohm fOSC=400kHz THD+N(%) Frequency(Hz) 60W 40W 20W 0.0001 0.001 0.01 0.1 20 20k 50 100 200 500 1k 2k 5k 10k Gain=26dB Load=2ohm fOSC=400kHz THD+N(%) Frequency(Hz) 60W 40W 20W Power Supply Rejection Ratio, 24V, 8 load (BTL) Power Supply Rejection Ratio, 12V, 8 load (BTL) ColorSweep Trace Line Style Thick Data Axis Comment 1 1 Red Solid 3 Anlr.Crosstalk Left 24v LCH 2 1 Blue Solid 3 Anlr.Crosstalk Left 24V RCH -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 d B 20 20k 50 100 200 500 1k 2k 5k 10k Hz Frequency (Hz) PSRR (dB) Gain=20dB Load=8ohm LCH RCH ColorSweep Trace Line Style Thick Data Axis Comment 1 1 Red Solid 3 Anlr.Crosstalk Left 12V LCH 2 1 Blue Solid 3 Anlr.Crosstalk Left RCH -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 d B 20 20k 50 100 200 500 1k 2k 5k 10k Hz T Frequency (Hz) PSRR (dB) Gain=20dB Load=8ohm LCH RCH Gain=20dB Load=8ohm fOSC=400kHz Gain=20dB Load=8ohm fOSC=400kHz
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 17/33 Efficiency, 8 load / 2ch (BTL) Efficiency, 4 load / 2ch (BTL) 100 0 20 40 60 80 100 Efficiency(%) Po(W) 24V 18V 12V Gain=26dB fOSC=400kHz 100 0 20 40 60 80 100 Efficiency(%) Po(W) 24V 18V 12V Gain=26dB fOSC=400kHz Efficiency, 4 load (PBTL) Efficiency, 2 load (PBTL) 100 0 20 40 60 80 100 Efficiency(%) Po(W) 24V 18V 12V Gain=26dB fOSC=400kHz 100 0 20 40 60 80 100 Efficiency(%) Po(W) 18V 12V Gain=26dB fOSC=400kHz
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 18/33 Functional Block Diagram L IN P R IN P O U T P L P L IM IT P o w e r S ta g e G a in S e le c t/ M o d e c o n tro l C o n tro l L o g ic L IN N R IN N M o d u la to r O U T N L O U T P R O U T N R P L IM IT B ia s A n d R e fe re n c e U n d e r-V o lta g e P ro te c tio n P L IM IT R e fe re n c e DC D e te c t G N D P V C C P o w e r S ta g e G N D P V C C G N D S h o rt-C irc u it P ro te c tio n BSPL B S N L N /N N /N BSPR B S N R P W M L o g ic P W M L o g icM o d u la to r AD 52070 G A IN /S L V L IM R A T E T h e rm a l D e te c t T ri-W a v e G e n e ra to r + A M A v o id a n c eAM [1 :0 ] R e g u la to r G V D DA V C C A G C P L IM IT P B T L /M O N O D e te c t S D Z w a v e w a v e S Y N C
input resistance from production variation. for a clock input. TTL logic levels with compliance to GVDD. Table 1. Volume gain, master/slave and input impedance
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 20/33 Shutdown (SDZ) control Pulling SDZ pin low will let AD52070 operate in low-current state for power conservation. The AD52070 outputs will enter shutdown once SDZ pin is pulled low, and regulator will also disable to save power. SDZ pin with pull low resistor internally, AD52070 will enter shutdown mode still if SDZ pin keep floating. For the best power-off performance, place the chip in the shutdown mode in advance of removing the power supply. Fade-in / Fade-out To reduce pop during high -speed on-off switching of audio amp, AD52070 uses slow rate on/off envelopes transition to avoid crack sound and uncomfortable feeling during in every fast turn-on/off. 10 ms 10 ms P W M _ O U T U V N& P O R S D N SPK 10 ms10 ms A V CC 4 .2 V 4 .0 V Automatic Gain Control Function Large input signal or lower supply voltage will easily distort output signal. The distorted and crack signal may damage speaker permanently. To provide a better listening experience for use r and protect the speaker from overload, AD52070 features a n Automatic Gain Control (AGC) function to prevent output signal from distortion. AGC function can automatically adjust system gain to let the output signal remain smooth by detecting the distortio n level of output signal and keep the distortion level smaller than adjustable AGC level. Figure 1 shows the ideal output waveform without clipping by rail. Figure 2 shows the realistic output signal with clipping by rail. Figure 3 shows the output waveform with AGC function enabled. When output signal is distorted, gain immediately decreases by 0.32ms/dB (2.56ms/dB or 5.12ms/dB) in AGC mode Fast (AGC mode Medium or mode Slow). Once the output signal does not reached predetermined power level, the gain level will remain unchanged until the input signal is lowered. As output is lowered, the attenuated gain step is released incrementally every 328ms/dB in AGC mode -Fast or
selectable by the LIMRATE pin setting. Table 2. AGC and Power limit Setting function. The limiter threshold set by the PLIMT pin voltage.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 22/33 AGC & Power limit level The AGC and PLIMIT volta ge threshold is set by a voltage at PLIMIT pin. The PLIMIT voltage is set by a voltage divider from GVDD and GND , the limiting is set a limit on the output peak-to-peak voltage. The PLIMIT voltage can be used to calculate the maximum output power for uncli pped in AGC mode and clipped in PLIMIT mode. PLIMIT pin is adjustable from 1.33V~2.1V. For unclipped power, Where: PLIMIT: Adjustable AGC voltage at PLIMIT pin PVCC: Chip operating voltage RL: Load resistance 90m: RDS-on value in AD52070 Pout: Maximum unclipped output power in AGC Power limit level (Po @1% THD+N): 1.1x Pout (unclipped) Connect PLIMIT pin to ground to disable AGC/PLIMIT mode. The output variation during AGC/PLIMIT mode may have +-20% variation due to process window. Table 3.1 AGC or PLIMIT Typical OperationⅠ Test Conditions Output PO (W) VPLIMIT (V) @ AGC mode VPLIMIT (V) @ PLIMIT mode (PO @1%) PVCC=24V RL=8ohm 5 1.98 1.96 8 1.85 1.82 10 1.77 1.74 12 1.70 1.66 15 1.61 1.56 20 1.47 1.42 L L LLIMIT R mR RPVCCV PV Pout 90734.2 5.22
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 23/33 Table 3.2 AGC or PLIMIT Typical OperationⅡ Test Conditions Output PO (W) VPLIMIT (V) @ AGC mode VPLIMIT (V) @ PLIMIT mode (PO @1%) PVCC=12V RL=8ohm 3 1.70 1.66 4 1.58 1.53 5 1.47 1.42 6 1.37 - Table 3.3 AGC or PLIMIT Typical Operation Ⅲ Test Conditions Output PO (W) VPLIMIT (V) @ AGC mode VPLIMIT (V) @ PLIMIT mode (PO @1%) PVCC=24V RL=4ohm 10 1.98 1.95 15 1.86 1.83 20 1.76 1.73 30 1.60 1.55 Table 3.4 AGC or PLIMIT Typical Operation Ⅳ Test Conditions Output PO (W) VPLIMIT (V) @ AGC mode VPLIMIT (V) @ PLIMIT mode (PO @1%) PVCC=12V RL=4ohm 5 1.76 1.73 8 1.57 1.52 10 1.46 1.41 12 1.36 -
loudspeaker drivers of right/left channel will disable and enter Hi-Z. the DC detect threshold is listed in table5. Table 4. DC Detect Threshold Table 5. Output DC Detect Duty (for Either Channel) reached, and the gain will be decreased again, or the gain is at its nominal gain level. setting as shown in Table 2.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 25/33 Thermal protection If the internal junction temperature is higher than 1 70oC, the outputs of loudspeaker drivers will be disabled and at low state. The tem perature for AD52070 returning to normal operation is about 135oC. The variation of protected temperature is about 10%. Short-circuit protection To protect loudspeaker drivers from over -current damage, AD52070 has built -in short-circuit protection circuit. When the wires connected to loudspeakers are shorted to each other or shorted to GND or to PVCC, overload detectors may activate. Once one of right and left channel overload detectors are active, the amplifier outputs will enter a Hi-Z state and the pro tection latch is engaged. The latch can be cleared by reset SDZ or power supply cycling. Under-voltage detection When the GVDD voltage is lower than 2. 8V or the AVCC voltage is lower than 4V, loudspeaker drivers of right/left channel will be disabled and kept at low state. Otherwise, AD52070 return to normal operation. Over-voltage protection When the AVCC voltage is higher than 29.5V, loudspeaker will be disabled kept at low state. The protection status will be released as AVCC lower than 29V. PBTL function AD52070 provides the application of parallel BTL operation with two outputs of each channel connected directly. If connect LINP and LINN directly to Ground (without capacitors) this sets the device in PBTL mode during power up. Connect OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL together for the negative pin. Analog input signal is applied to INPR and INNR. Mono function (Single Channel) AD52070 can be connected in MONO mode to cut the idle power -loss nearly by h alf. If connect RINP and RINN directly to Ground (without capacitors) this sets the device in Mono mode during power up. Connect OUTPL and OUTNL to speaker just like normal BTL mode. Analog input signal is applied to LINP and LINN. Mute control The mute function provides also in AD52070 via PLIMIT pin. To connect PLITMIT pin to GVDD (>2.4V), the outputs will switch at idle PWM duty cycle (Low idle mode). A logic low (<2.3V) on this pin enables the outputs. This function may be used as a quick disable/enable of outputs when transitioning between different audio sources . It’s also good with pop suppression via mute control . For power conservation, the SDZ
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 26/33 (shutdown) terminal should be used to reduce the quiescent current to the absolute minimum level. Power On/Off sequence Hereunder is AD52070’s power on/off sequence. P V C C A V C C S D Z A u d io P L IM IT (M U T E) t3 t4 Symbol Min. (ms) Typ. (ms) Max. (ms) t1 0 - - t2 0.1 - - t3 10 - - t4 10 - - t5 10 - - t6 0
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 27/33
Application information
Input capacitors (Cin) The performance at low frequency (b ass) is affected by the corner frequency (f c) of the high-pass filter composed of input resistor (R in) and input capacitor (C in), determined in equation (2). Typically, a 0.1 F or 1 F ceramic capacitor is suggested for C in. The resistance of input resistors is different at different gain setting. The respective gain and input resistance are listed in Table 1 (shown at GAIN SETTING). However, there is 20% variation in input resistance from production variation. 2HzCR 2 inin c π Boot-strap capacitor The output stage of the AD52070 uses a high -side NMOS driver. To generate the gate driver voltage for the high -side NMOS, a boot -strap capacitor for each output terminal acts as a floating power supply for the switching cycle. Use 0.22uF capacitors to connect the appropriate output pin to the boot-strap pin in stereo/mono application. Output LC Filter If the traces from the AD52070 to speaker are not short, it is recommended to add the output LC filter to eliminate the high frequency emissions. Figure 3 shows the typical output filter for 8 and 4 speaker with a cut -off frequency of 61 kHz and Figure 4 shows the typical output filter for 4 speaker with a cut-off frequency of 34 kHz. OUTP OUTN 10uH 10uH 0.68uF 0.68uF Figure 3. Typical LC Output Filter for 8 Speaker
Figure 4. Typical LC Output Filter for 4 Speaker AD52070 switching frequency can be adjusted by 300KHz, 400KHz, 500KHz or 1.2MHz. Higher switching frequency means smaller inductor value needed. enough to avoid the large ripple current to trigger the OC threshold.
Figure 6. Recommended Power Supply Decoupling Capacitors. GVDD supply can also be used to supply the PLIMIT and GAIN/SLV voltage dividers. In addition, it is required that the peak current is smaller than the OCP trigger threshold. current >1.35 times of the peak current of maximum output power is suggested.
frequency being demodulated by the AM radio. Table 6. AM Frequencies
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 31/33 Package Dimensions E-TSSOP 28L (173 mil) SIDE VIEW L PIN#1 MARK E E1 b TOP VIEW c DETAIL A A D e 1 14 1528 1 14 Exposed pad Min Max Dimension in mm A -- 1.20 Min Max A1 0.05 0.15 D2 5.00 6.40 b 0.19 0.30 E2 2.50 2.90 c 0.09 0.20 D 9.60 9.80 E 4.30 4.50 E1 6.30 6.50 e L 0.45 0.75
0.65 BSC
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 32/33
Revision History
0.1 2020.12.16 Initial version. 0.2 2021.02.03 Update pin description. Update absolute maximum ratings. 1.0 2021.06.21 Remove “Preliminary” and Revise to 1.0 1.1 2021.10.06 1) Update features and description. 2) Update pin description. 3) Update absolute maximum ratings. 4) Update application circuit example for PBTL. 5) Update electrical characteristics. 6) Update typical characteristics. 7) Update function description.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2021 Revision: 1.1 33/33 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for a ny error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellect ual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.