AD5206BN10

AD5204 AD | Alldatasheet

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD5204/AD5206 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 REV. 0 4-/6-Channel Digital Potentiometers FUNCTIONAL BLOCK DIAGRAMS VDDAD5204CS CLK EN ADDR DECA2 A0SDI DI SER REG GND RDAC LATCH R RDAC LATCH RPOWER- ON PRESET VSS SDO DO PR SHDN VDDAD5206CS CLK EN ADDR DECA2 A0SDI DI SER REG GND RDAC LATCH R RDAC LATCH RPOWER- ON PRESET VSS

FEATURES

256 Position

Multiple Independently Programmable Channels AD5204—4-Channel AD5206—6-Channel Potentiometer Replacement 10 kV, 50 k V, 100 k V 3-Wire SPI-Compatible Serial Data Input +2.7 V to +5.5 V Single Supply; 62.7 V Dual Supply Operation Power ON Midscale Preset

APPLICATIONS

Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching GENERAL DESCRIPTION The AD5204/AD5206 provides four-/six-channel, 256 position digitally-controlled Variable Resistor (VR) devices. These de- vices perform the same electronic adjustment function as a potentiometer or variable resistor. Each channel of the AD5204/ AD5206 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resis- tance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely program- mable value of resistance between the A terminal and the wiper or the B Terminal and the wiper. The fixed A-to-B terminal resistance of 10 kW , 50 kW , or 100 kW has a nominal tempera- ture coefficient of 700 ppm/ °C. Each VR has its own VR latch which holds its programmed resistance value. These VR latches are updated from an internal serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Eleven data bits make up the data word clocked into the serial input register. The first three bits are decoded to determine which VR latch will be loaded with the last eight bits of the data word when the CS strobe is returned to logic high. A serial data output pin at the opposite end of the serial register (AD5204 only) allows simple daisy-chaining in multiple VR applications without additional external decoding logic. An optional reset (PR) pin forces all the AD5204 wipers to the midscale position by loading 80 H into the VR latch. The AD5204/AD5206 is available in both surface mount (SOL-24), TSSOP-24 and the 24-lead plastic DIP package. All parts are guaranteed to operate over the extended industrial temperature range of –40 °C to +85 °C. For additional single, dual, and quad channel devices, see the AD8400/AD8402/ AD8403 products.

REV. 0 AD5204/AD5206–SPECIFICATIONS –2–

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ 1 Max Units DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL 2 R-DNL R WB, VA = No Connect –1 – 1/4 +1 LSB Resistor Nonlinearity Error 2 R-INL R WB, VA = No Connect –2 – 1/2 +2 LSB Nominal Resistor Tolerance 3 D RAB TA = +25°C –30 +30 % Resistance Temperature Coefficient D RAB/D TV AB = VDD, Wiper = No Connect 700 ppm/ °C Nominal Resistance Match D R/RAB CH1 to 2, 3, 4, or 5, 6; V AB = VDD 0.25 1.5 % Wiper Resistance R W IW = 1 V/R, VDD = +5 V 50 100 W DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Resolution N 8 Bits Differential Nonlinearity

4 DNL –1 – 1/4 +1 LSB

Integral Nonlinearity 4 INL –2 – 1/2 +2 LSB Voltage Divider Temperature Coefficient D VW/D T Code = 40 H 15 ppm/ °C Full-Scale Error V WFSE Code = 7FH –2 –1 0 LSB Zero-Scale Error V WZSE Code = 00H 0+ 1 + 2L S B RESISTOR TERMINALS Voltage Range5 VA, VB, VW VSS VDD V Capacitance6 Ax, Bx C A, CB f = 1 MHz, Measured to GND, Code = 40 H 45 pF Capacitance6 Wx C W f = 1 MHz, Measured to GND, Code = 40 H 60 pF Shutdown Current 7 IA_SD 0.01 5 mA Common-Mode Leakage I CM VA = VB = VW = 0, VDD = +2.7 V, VSS = –2.5 V 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High V IH VDD = +5 V/+3 V 2.4/2.1 V Input Logic Low V IL VDD = +5 V/+3 V 0.8/0.6 V Output Logic High V OH RPULL–UP = 1 kW to +5 V 4.9 V Output Logic Low V OL IOL = 1.6 mA, VLOGIC = +5 V 0.4 V Input Current I IL VIN = 0 V or +5 V – 1 mA Input Capacitance 6 CIL 5p F POWER SUPPLIES Power Single Supply Range V DD Range V SS = 0 V 2.7 5.5 V Power Dual Supply Range V DD/SS Range – 2.3 – 2.7 V Positive Supply Current I DD VIH = +5 V or V IL = 0 V 12 60 mA Negative Supply Current I SS VSS = –2.5 V, VDD = +2.7 V 12 60 mA Power Dissipation 8 PDISS VIH = +5 V or V IL = 0 V 0.3 mW Power Supply Sensitivity PSS D VDD = +5 V – 10% 0.0002 0.005 %/% DYNAMIC CHARACTERISTICS 6, 9 Bandwidth –3 dB BW_10K R AB = 10 kW 721 kHz BW_50K R AB = 50 kW 137 kHz BW_100K R AB = 100 kW 69 kHz Total Harmonic Distortion THD W VA = 1.414 V rms, V B = 0 V dc, f = 1 kHz 0.004 % VW Settling Time (10K/50K/100K) t S VA = 5 V, VB = 0 V, – 1 LSB Error Band 2/9/18 ms Resistor Noise Voltage e N_WB RWB = 5 kW , f = 1 kHz, PR = 0 9 nV/ ÖHz INTERFACE TIMING CHARACTERISTICS Applies to All Parts 6, 10 Input Clock Pulsewidth t CH, tCL Clock Level High or Low 20 ns Data Setup Time t DS 5n s Data Hold Time t DH 5n s CLK to SDO Propagation Delay 11 tPD RL = 2 kW , CL < 20 pF 1 150 ns CS Setup Time t CSS 15 ns CS High Pulsewidth t CSW 40 ns Reset Pulsewidth t RS 90 ns CLK Fall to CS Fall Setup t CSH0 0n s CLK Fall to CS Rise Hold Time t CSH1 0n s CS Rise to Clock Rise Setup t CS1 10 ns NOTES 1Typicals represent average readings at +25 °C and VDD = +5 V. 2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 23 test circuit. I W = VDD/R for both VDD = +3 V or VDD = +5 V. 3VAB = VDD, Wiper (VW) = No connect. 4INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of – 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 22 test circuit. (VDD = +5 V 6 10% or +3 V 6 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40 8C < TA < +858C unless otherwise noted.)

–3– AD5204/AD5206 REV. 0 5Resistor Terminals A, B, W, have no limitations on polarity with respect to each other. 6Guaranteed by design and not subject to production test. 7Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8PDISS is calculated from (I DD · VDD). CMOS logic level inputs result in minimum power dissipation. 9All dynamic characteristics use V DD = +5 V. 10See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V DD = +3 V or +5 V. 11Propagation delay depends on value of V DD, RL and CL. See Operation section. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* (TA = +25°C, unless otherwise noted) Maximum Junction Temperature (T CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5204/AD5206 features proprietary ESD protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Thermal Resistance qJA *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. WARNING! ESD SENSITIVE DEVICE

The AD5204/AD5206 contains 5,925 transistors. Die size; 92 mil · 114 mil, 10,488 sq. mil. Figure 1. Timing Diagram

61 LSB ERROR BAND

61 LSB

Figure 2. Detail Timing Diagram Figure 3. AD5204 Preset Timing Diagram

–5–REV. 0 AD5204 PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1, 2, 12 NC Not Connected. 3 GND Ground. 4 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded based on the address bits and loaded into the target RDAC latch.

5 PR Active low preset to midscale; sets RDAC

registers to 80H. DD Positive power supply, specified for operation at both +3 V or +5 V. (Sum of DD| + |VSS| <5.5 V.) 7 SHDN Active low input. Terminal A open-circuit. Shutdown controls Variable Resistors #1 through #4. 8 SDI Serial Data Input. MSB First. 9 CLK Serial Clock Input, positive edge triggered.

10 SDO Serial Data Output, Open Drain transistor

requires pull-up resistor. 11 V SS Negative Power Supply, specified for operation at both 0 V or –2.7 V. (Sum of DD| + |VSS| <5.5 V.) 13 B3 B Terminal RDAC #3.

14 W3 Wiper RDAC #3, addr = 010

15 A3 A Terminal RDAC #3. 16 B1 B Terminal RDAC #1.

17 W1 Wiper RDAC #1, addr = 000

18 A1 A Terminal RDAC #1. 19 A2 A Terminal RDAC #2.

20 W2 Wiper RDAC #2, addr = 001

21 B2 B Terminal RDAC #2. 22 A4 A Terminal RDAC #4.

23 W4 Wiper RDAC #4, addr = 011

24 B4 B Terminal RDAC #4. AD5206 PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1 A6 A Terminal RDAC #6. 2 W6 Wiper RDAC #6, addr = 101 2. 3 B6 B Terminal RDAC #6. 4 GND Ground. 5 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded based on the address bits and loaded into the target RDAC latch. DD Positive power supply, specified for operation at both +3 V or +5 V. (Sum of DD| + |VSS| <5.5 V.) 7 SDI Serial Data Input. MSB First. 8 CLK Serial Clock Input, positive edge triggered. SS Negative Power Supply, specified for operation at both 0 V or –2.7 V. (Sum of DD| + |VSS| <5.5 V.) 10 B5 B Terminal RDAC #5.

11 W5 Wiper RDAC #5, addr = 100

12 A5 A Terminal RDAC #5. 13 B3 B Terminal RDAC #3. 15 A3 A Terminal RDAC #3. 16 B1 B Terminal RDAC #1. 18 A1 A Terminal RDAC #1. 19 A2 A Terminal RDAC #2. 21 B2 B Terminal RDAC #2. 22 A4 A Terminal RDAC #4. 24 B4 B Terminal RDAC #4. AD5206 PIN CONFIGURATION VSS CLK GND SDI VDD CS AD5206 (NOT TO SCALE) AD5204 PIN CONFIGURATION NC VSS SDO CLK SDI NC NC GND CS SHDN VDD PR AD5204 (NOT TO SCALE) NC = NO CONNECT

Figure 4. Incremental Wiper ON Resistance vs. Voltage Figure 5. Gain Flatness vs. Frequency Figure 6. –3 dB Bandwidth vs. Terminal Resistance,

2.7 V Single Supply Operation

Figure 7. –3 dB Bandwidth vs. Terminal Resistance, Figure 8. Bandwidth vs. Code, 10K Version Figure 9. Bandwidth vs. Code, 50K Version

Figure 16. AD5204/AD5206 Equivalent RDAC Circuit diagram of the equivalent RDAC circuit. RBA is the nominal end-to-end resistance.

temperature has a 700 ppm/ °C temperature coefficient. proportional to the input voltage applied to a given terminal. absolute value, therefore, the drift improves to 15 ppm/ °C. Figure 17. Block Diagram referenced to digital ground (GND). for equivalent SDO output circuit schematic. L L H H No SR effect, enables SDO pin. P L H H Shift one bit in from the SDI pin. is shifted out of the SDO pin. on A2, A1, A0 decode (Table V). NOTE: P = positive edge, X = don’t care, SR = shift register. latches, see Figure 18 detail.

–11–REV. 0 24-Lead Narrow Body PDIP (N-24) 11 2 PIN 1 1.275 (32.30) 1.125 (28.60) 0.280 (7.11) 0.240 (6.10) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) SEATING PLANE 0.060 (1.52) 0.015 (0.38)0.210 (5.33) MAX 0.022 (0.558) 0.014 (0.356) 0.200 (5.05) 0.125 (3.18) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 24-Lead SOIC (R-24/SOL-24) 0.0125 (0.32) 0.0091 (0.23) 0.0291 (0.74) 0.0098 (0.25)3 458 0.0500 (1.27) 0.0157 (0.40) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 24 13 121 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40)PIN 1 0.6141 (15.60) 0.5985 (15.20) 24-Lead Thin Shrink SO Package (TSSOP) (RU-24) 24 13 121 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30)PIN 1 0.311 (7.90) 0.303 (7.70) SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3677–8–9/99PRINTED IN U.S.A.