AD52060 ESMT | Alldatasheet
Document overview
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Technical content
Features
Single supply voltage 8V ~ 26V for loudspeaker driver Built-in LDO output 5V for others Loudspeaker power from 24V supply BTL Mode: 20W/CH into 8 @<1% THD+N PBTL Mode: 40W/CH into 4 @<10% THD+N Loudspeaker power from 12V supply BTL Mode: 10W/CH into 8 @10% THD+N 88% efficient Class -D operation eliminates need for heat sink Differential inputs Four selectable, fixed gain settings Internal oscillator Short-Circuit protection with auto recovery option Under-Voltage detection Over-Voltage protection Pop noise and click noise reduction Adjustable power limit function for speaker protection Output DC detection for speaker protection Filter-Free operation Over temperature protection with auto recovery Superior EMC performance
Applications
TV audio Boom-Box Powered speaker Monitors Consumer Audio Equipment
Description
The AD52060 is a high efficiency stereo class -D audio amplifier with adjustable power limit function . The lou dspeaker driver operates from 8V~26V supply voltage. It can deliver 20W/CH output power into 8 loudspeaker within 1% THD+N at 24 V supply voltage and without external heat sink when playing music. AD52060 provides parallel BTL (Mono) application, and it ca n deliver 40W into 4 loudspeaker at 24V supply voltage . The adjustable power limit function allows user to set a voltage rail lower than half of 5V to limit the amount of current through the speaker. Output DC detection prevents speaker damage from long -time current stress . AD52060 provide s superior EMC performance for filter-free application. The output short circuit and over temperature protection include auto-recovery feature. Simplified Application Circuit
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 2/23 Pin Assignments GAIN0 LINN AVCC GAIN1 LINP PVCCL PGND OUTPL BSNL OUTNL BSPL 15PBTL PLIM AGND GVDD RINP PVCCR PGND BSNR OUTNR BSPR RINN OUTPR E-TSSOP-28L SD FAULT (TOP VIEW) TEST PVCCL PVCCR Pin Description NAME E-TSSOP -28L TYP DESCRIPTION SD 1 I Shutdown signal for IC (low = disabled, high = operational). Voltage compliance to AVCC. FAULT 2 O Open drain output used to display short circuit or dc detect fault. Voltage compliant to AVCC. Short circuit faults can be set to auto -recovery by connecting FAULTB pin to SD pin. Otherwise, both short circuit faults and dc detect faults must be reset by cycling AVCC. LINP 3 I Positive audio input for left channel. Biased at 2.5V. LINN 4 I Negative audio input for left channel. Biased at 2.5V. GAIN0 5 I Gain select least significant bit. Voltage compliance to AVCC. GAIN1 6 I Gain select most significant bit. Voltage compliance to AVCC. AVCC 7 P Analog supply. AGND 8 P Analog signal ground. Connect to the thermal pad. GVDD 9 O 5V regulated output, also used as supply for PLIMIT function. PLIMIT 10 I Power limit level adjustment. Connect a resistor divider from GVDD to GND to set power limit. Give V(PLIMIT) <2.4V to set power limit level. Connect to GVDD (>2.4V) or GND to disable power limit function. RINN 11 I Negative audio input for right channel. Biased at 2.5V. RINP 12 I Positive audio input for right channel. Biased at 2.5V. TEST 13 I Test mode pin. PBTL 14 I Parallel BTL mode switch, high for parallel BTL output. Voltage compliance to AVCC.
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 3/23 PVCCR 15,16 P High-voltage power supply for right -channel. Right channel and left channel power supply inputs are connect internal. BSPR 17 I Bootstrap I/O for right channel, positive high side FET. OUTPR 18 O Class-D H-bridge positive output for right channel. PGND 19 P Power ground for the H-bridges. OUTNR 20 O Class-D H-bridge negative output for right channel. BSNR 21 I Bootstrap I/O for right channel, negative high side FET. BSNL 22 I Bootstrap I/O for left channel, negative high side FET. OUTNL 23 O Class-D H-bridge negative output for left channel. PGND 24 P Power ground for the H-bridges. OUTPL 25 O Class-D H-bridge positive output for left channel. BSPL 26 I Bootstrap I/O for left channel, positive high side FET. PVCCL 27,28 P High-voltage power supply for right -channel. Right channel and left channel power supply inputs are connect internal. Thermal Pad P Must be soldered to PCB’s ground plane.
Ordering Information
Product ID Package Packing / MPQ Comments AD52060-QG28NRT E-TSSOP 28L
50 Units / Tube
100 Tubes / Small Box
AD52060-QG28NRR E-TSSOP 28L
2500 Units / Reel
2500 Units / Small Box
Package Type Device No. θJA(℃/W) θ JT(℃/W) Ψ JT(℃/W) Exposed Thermal Pad E-TSSOP 28L AD52060 28 27.1 1.33 Yes (Note 1) Note 1.1: The thermal pad is located at the bottom of the package. To optimize thermal performance, soldering the thermal pad to the PCB’s ground plane is necessary. Note 1.2: θ JA is simulated on a room temperature ( TA=25℃), natural convection environment test board, which is constructed with a thermally efficient, 4 -layers PCB (2S2P). The measurement is simulated using the JEDEC51-5 thermal measurement standard. Note 1.3: θ JT represents the thermal resistance for the heat flow between the chip junction and the package’s top surface. It’s extracted from the simulation data with obtaining a cold plate on the package top. Note 1.4: ΨJT represents the thermal parameter for the heat flow between the chip junction and the package’s top surface center. It’s extracted from the simulation data for obtainingθ JA, using a procedure described in JESD51-5.
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 4/23 Marking Information AD52060
- Marking Information Line 1：LOGO Line 2：Product No Line 3：Tracking Code Absolute Maximum Ratings Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT PVCC Supply voltage PVCCL, PVCCR -0.3 30 V VI Interface pin voltage SD, GAIN0, GAIN1, PBTL, FAULT, -0.3 30 V PLIMIT -0.3 5.5 TA Operating free-air temperature range -40 85 oC TJ Operating junction temperature range -40 150 oC Tstg Storage temperature range -65 150 oC RL Minimum Load Resistance BTL: PVCC ＞ 13V 4.8 BTL: PVCC ≦ 13V 3.2 PBTL 3.2 ESD Human Body Model ±2k Charged Device Model ±500 Recommended Operating Conditions SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT PVCC Supply voltage AVCC, PVCCL, PVCCR 8 26 V VIH High-level input voltage SD, GAIN0, GAIN1, PBTL 2 V VIL Low-level input voltage SD, GAIN0, GAIN1, PBTL 0.8 V VOL Low-level output voltage FAULT, RPULL-UP=100k, VCC=16V 0.8 V IIH High-level input current SD, GAIN0, GAIN1, PBTL, VI=2V, VCC=18V 50 uA IIL Low-level input current SD, GAIN0, GAIN1, PBTL, VI=0.8V, VCC=18V 5 uA IOH High-level output current VI=2V, VCC=18V 50 IOL Low-level output current VI=0.8V, VCC=18V 50 TA Operating free-air temperature -40 85 oC PIN1 DOT ESMT AD52060 Tracking Code
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 5/23 General Electrical Characteristics PVCC=24V, RL=8TA=25°C (unless otherwise noted) SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT ICC(q) Quiescent supply current SD=2V, no load, PVCC=12V 20 35 mA ICC(SD) Quiescent supply current in shutdown mode SD=0.8V, no load, PVCC=12V < 12 25 uA RDS(on) Drain-source on-state resistance-High side NMOS PVCC=12V, Id=500mA, TJ=25 oC 220 m Drain-source on-state resistance-Low side NMOS 220 m |VOS| Class-D output offset voltage (measured differential) PVCC=12V VI=0V, Gain=36dB 1.5 15 mV tON Turn-on time SD=2V 90 ms tOFF Turn-off time SD=0.8V 2 s GVDD Regulator output IGVDD=0.1mA 4.75 5 5.25 V G Gain GAIN1 =0.8V GAIN0=0.8V 18 20 22 dB GAIN0=2V 24 26 28 GAIN1 =2V GAIN0=0.8V 30 32 34 GAIN0=2V 34 36 38
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 6/23 Electrical Characteristics and Specifications of Loudspeaker Driver PVCC=24V, RL=8TA=25°C (unless otherwise noted) SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT PO Output power THD+N=0.03%, f=1kHz, PVCC=24V 20 W THD+N=10%, f=1kHz, PVCC=12V 10 THD+N Total harmonic distortion plus noise PVCC=24V, RL=8f=1kHz, PO=10W (half-power) 0.02 PVCC=12V, RL=8f=1kHz, PO=5W (half-power) 0.03 SNR Signal to noise ratio Maximum output at THD+N<1%, f=1kHz, Gain=20dB, a-weighted 103 dB Vn Output integrated noise F=20Hz ~ 20kHz, Gain=20dB, a-weighted filter, RL=8 80 V KSVR Power Supply Rejection Ratio Vripple=200mVpp at 1kHz, Gain=20dB, inputs ac-grounded -70 dB Crosstalk Crosstalk F=1kHz, VO=1Vrms, Gain=20dB -103 dB fOSC Oscillator frequency 250 310 370 kHz TSENSOR Thermal trip point 150 oC Thermal hysteresis 25 oC THD + N (%) v.s. Output power (8ohm load) ColorSweep Trace Line Style Thick Data Axis Comment 1 1 Red Solid 3 Anlr.THD+N Ratio Left 24V 2 1 Blue Solid 3 Anlr.THD+N Ratio Left 18V 3 1 Magenta Solid 3 Anlr.THD+N Ratio Left 12V 0.01 0.02 0.05 0.1 0.2 0.5 10m 20m 50m 100m 200m 500m W T THD + N (%) v.s. Output power (6ohm load) Gain=20dB Load=8ohm+66uH 18V 24V 12V
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 7/23 ColorSweep Trace Line Style Thick Data Axis Comment 1 1 Red Solid 3 Anlr.THD+N Ratio Left 24V 2 1 Blue Solid 3 Anlr.THD+N Ratio Left 18V 3 1 Magenta Solid 3 Anlr.THD+N Ratio Left 12V 0.01 0.02 0.05 0.1 0.2 0.5 10m 20m 50m 100m 200m 500m W T THD + N (%) v.s. Output power (4ohm load) ColorSweep Trace Line Style Thick Data Axis Comment 1 1 Blue Solid 3 Anlr.THD+N Ratio Left 18V 2 1 Magenta Solid 3 Anlr.THD+N Ratio Left 12V 0.01 0.02 0.05 0.1 0.2 0.5 10m 20m 50m 100m 200m 500m W T Gain=20dB Load=6ohm+47uH 18V 24V 12V Gain=20dB Load=4ohm+33uH 18V 12V
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 8/23 AD52060_8ohm stereo 4 6 8 10 12 14 16 18 20 22 24 26 Output Power (W PVCC (V) THD+N=10% THD+N=1% Note: Dashed Line represent thermally limited regions. AD52060_6ohm stereo 4 6 8 10 12 14 16 18 20 22 24 26 Output Power (W) PVCC (V) THD+N=10% THD+N=1% Note: Dashed Line represent thermally limited regions.
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 9/23 AD52060_4ohm Mono 4 6 8 10 12 14 16 18 20 22 24 26 Output Power (W) PVCC (V) THD+N=10% THD+N=1% Note: Dashed Line represent thermally limited regions. THD + N (%) v.s. Frequency (24V 8ohm load) ColorSweep Trace Line Style Thick Data Axis Comment 1 1 Red Solid 3 Anlr.THD+N Ratio Left 24V 20W LCH 3 1 Blue Solid 3 Anlr.THD+N Ratio Left 10W LCH 4 1 Magenta Solid 3 Anlr.THD+N Ratio Left 5W LCH 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 20k 100 200 500 10k Hz T T T Noise (8ohm load) 10W 20W Gain=20dB Load=8ohm+66uH
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 10/23 120u 10u 20u 30u 40u 50u 60u 70u 80u 90u 100u 110u V 20 20k50 100 200 500 1k 2k 5k 10k Hz Efficiency (Stereo 8ohm load) / 2ch 100 0 10 20 30 40 50 60 70 80 Output Pow er (W)*2CH Efficiency (%) PVDD=24V PVDD=18V PVDD=12V Efficiency (Mono 4ohm load) / 2ch 24V 18V 12V Gain=20dB Load=8ohm+66uH
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 11/23 100 0 10 20 30 40 50 60 70 80 Output Pow er (W) Efficiency (%) PVDD=24V PVDD=18V PVDD=12V
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 12/23 Functional Block Diagram Modulator GAIN0 GAIN1 LINP RINP OUTPL PLIMIT Power Stage PLIMIT PVCC Regulator Gain Select Control Logic LINN RINN ModulatorGain Control Amplifier SD OUTNL OUTPR OUTNR PLIMIT Bias And Reference Thermal Detect Under-Voltage Protection FAULT GVDD PLIMIT Reference DC Detect FAULT Logic Short Circuit Error DC Detect Error AGND PVCCL Power Stage PGND PVCCR PGND Short-Circuit Protection BSPL BSNL N/N N/N BSPR BSNR ∆-wave PWM Logic PWM Logic Gain Control Amplifier
resistance from production variation. Table 1. Volume gain and input impedance SD pin low will let AD52060 operate in low-current state for power conservation. shutdown mode in advance of removing the power supply. SD , it is necessary to cycle the PVCC supply. the DC detect threshold is listed in table3.
Table 2. DC Detect Threshold Table 3. Output DC Detect Duty (for Either Channel) normal operation is about 125oC. The variation of protected temperature is about 10%. protection latch will re-cycle if output overload is detected again. AD52060 return to normal operation.
state. The protection status will be released as PVCC lower than 29V. PLIMIT pin. The voltage VPLIMIT sets a limit on the output peak -to-peak voltage. PLIMIT is adjustable from 1.33V~2.5V. Table 4. PLIMIT Typical OperationⅠ
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 16/23 AD52060 provides the application of parallel BTL operation with two outputs of each channel connected directly. If the PBTL pin is tied high, the positive and negative outputs of left and right channel are synchronized and in phase. Apply the input signal to the RIGHT channel input in PBTL mode and let the LEFT channel input grounded, and place the speaker between the LEFT and RIGHT outputs. The output swing is doubled of that in normal mode. See the application circuit example for PBTL (Mono) mode operation. For normal BTL (Stereo) operation, connect the PBTL pin to ground.
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 17/23
Application information
Input capacitors (Cin) The performance at low frequency (bass) is affected by the corner frequency (fc) of the high-pass filter composed of input resistor (R in) and input capacitor (Cin), determined in equation (2). Typically, a 0.1 F or 1 F ceramic capacitor is suggested for C in. The resistance of input resistors is different at different gain setting. The respective gain and input resistance are listed in Table 1 (shown at GAIN SETTING). However, there is 20% variation in input resistance from production variation. 2HzCR 2 inin c π Ferrite Bead selection If the traces from the AD52060 to speaker are short, the ferrite bead filters can reduce the high frequency emissions to meet FCC requirements. A ferrite bead that has very low impedance at low frequency and high impedance at high frequency (above 1MHz) is recommended. The impedance of the ferrite bead can be used along with a small capacitor with a value around 1000pF to reduce the frequency spectrum of the signal to an acceptable level. FB 1000pF 1000pFFB OUTP OUTN Figure 2. Typical Ferrite Bead Filter typical output filter for 4 speaker with a cut-off frequency of 27 kHz.
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 19/23 Application Circuit Example Application circuit for BTL (Stereo) mode configuration and Singe-Ended Input PVCC GAIN0 LINN AVCC GAIN1 LINP PVCCL PVCCL PGND OUTPL BSNL OUTNL BSPL AD52060 PBTL TEST PLIM AGND GVDD RINP PVCCR PVCCR PGND BSNR OUTNR BSPR RINN OUTPR SD FAULT 100k Shutdown Control 1uF 1uF 1uF 1uF 1uF 1uF FB 1000pF 1000pFFB PVCC 100uF0.1uF PVCC L-ch Input R-ch Input RPL1 RPL2 100uF0.1uF FB 1000pF 1000pFFB PVCC 1uF 0.22uF 0.22uF 0.22uF 0.22uF Note 2: These resistances must be connected to ground, resistance=1Kohm Note 2 Note 2
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 20/23 Application Circuit Example Application circuit for parallel BTL (Mono) mode configuration and Singe-Ended Input PVCC GAIN0 LINN AVCC GAIN1 LINP PVCCL PVCCL PGND OUTPL BSNL OUTNL BSPL AD52060 PBTL TEST PLIM AGND GVDD RINP PVCCR PVCCR PGND BSNR OUTNR BSPR RINN OUTPR SD FAULT 100k Shutdown Control 1uF 1uF 1uF 1uF FB 1000pF 1000pFFB PVCC 100uF0.1uF PVCC R-ch Input RPL1 RPL2 100uF0.1uF PVCC 1uF 0.47uF 0.47uF PVCC Note 2: These resistances must be connected to ground, resistance=1Kohm. Note 3: Be noted that input should be applied on R-channel only for Mono application. Note 2
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 21/23 Package Dimensions E-TSSOP 28L SIDE VIEW L PIN#1 MARK E E1 b TOP VIEW c DETAIL A A D e 1 14 1528 1 14 Exposed pad Min Max Dimension in mm A -- 1.20 Option 1 Min Max A1 0.05 0.15 D2 4.25 5.75 b 0.19 0.30 E2 2.35 3.18 c 0.09 0.20 D 9.60 9.80 E 4.30 4.50 E1 6.30 6.50 e L 0.45 0.75
0.65 BSC
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 22/23
Revision History
0.1 2016.04.18 Original. 0.2 2016.10.07 Add Tape/Reel information 1.1 2016.12.15 Modified Package Dimensions information 1.2 2017.01.05 Modified Exposed PAD information 1.3 2017.04.19 Added performance data. 1.4 2018.01.22 Modify ESD data 1.5 2018.03.05 1.Modify simplified application circuit 2.Modify MOQ for AD52060-QG28NRR
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018 Revision: 1.5 23/23 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibi lity for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such ki nds of application, purchaser must do its own quality assurance testing appropriate to such applications.