AD5206

AD5204/AD5206 (Rev.G)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 16

Technical content

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REVISION HISTORY

8/2024—Rev. F to Rev. G 5/2022—Rev. E to Rev. F Changed 0x40 to Midscale, 0x7F to Full Scale, 0x00 to Zero Scale, and VDD Range to VDD Throughout, Changes to VW Settling Time Parameter, Input Logic High Parameter, and Input Logic Low Parameter,

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ELECTRICAL CHARACTERISTICS

VDD = 5 V ± 10% or 3 V ± 10%, VSS = 0 V, VA = VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE2 Resistor Differential NL3 R-DNL RWB, VA = no connect −1 ±0.25 +1 LSB Resistor Nonlinearity Error3 R-INL RWB, VA = no connect −2 ±0.5 +2 LSB Nominal Resistor Tolerance4 ΔRAB TA = 25°C −30 +30 % Resistance Temperature Coefficient ΔRAB/ΔT VAB = VDD, wiper = no connect 700 ppm/°C Nominal Resistance Match ΔR/RAB Channel 1 to Channel 2, Channel 3, and Channel 4, or to Channel 5 and Channel 6; VAB = VDD 0.25 1.5 % Wiper Resistance RW IW = 1 V/R, VDD = 5 V 50 100 Ω DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE2 Resolution N 8 Bits Differential Nonlinearity5 DNL −1 ±0.25 +1 LSB Integral Nonlinearity5 INL −2 ±0.5 +2 LSB Voltage Divider Temperature CoefficientΔVW/ΔT Code = midscale 15 ppm/°C Full-Scale Error VWFSE Code = full scale −2 −1 0 LSB Zero-Scale Error VWZSE Code = zero scale 0 1 2 LSB RESISTOR TERMINALS Voltage Range6 VA, VB, VW VSS VDD V Capacitance7 Ax, Bx CA, CB f = 1 MHz, measured to GND, code = midscale 45 pF Capacitance7 Wx CW f = 1 MHz, measured to GND, code = midscale 60 pF Shutdown Current8 IA_SD 0.01 5 μA Common-Mode Leakage ICM VA = VB = VW = 0, VDD = +2.7 V, VSS = −2.5 V 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V 2.4 V VDD = 3 V 2.1 V Input Logic Low VIL VDD = 5 V 0.8 V VDD = 3 V 0.6 V Output Logic High VOH RPULL–UP = 1 kΩ to 5 V 4.9 V Output Logic Low VOL IOL = 1.6 mA, VLOGIC = 5 V 0.4 V Input Current IIL VIN = 0 V or 5 V ±1 μA Input Capacitance7 CIL 5 pF POWER SUPPLIES Power Single-Supply Range VDD VSS = 0 V 2.7 5.5 V Power Dual-Supply Range VDD/VSS ±2.3 ±2.7 V Positive Supply Current IDD VIH = 5 V or VIL = 0 V 12 60 μA Negative Supply Current ISS VSS = −2.5 V, VDD = +2.7 V 12 60 μA Power Dissipation9 PDISS VIH = 5 V or VIL = 0 V 0.3 mW Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% 0.0002 0.005 %/% DYNAMIC CHARACTERISTICS7, 10 Bandwidth −3 dB BW_10K RAB = 10 kΩ 721 kHz BW_50K RAB = 50 kΩ 137 kHz

Table 1. (Continued) 1 Typicals represent average readings at 25°C and VDD = 5 V. 3 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. VDD/R for both VDD = 3 V and VDD = 5 V. 4 VAB = VDD, wiper (VW) = no connect. ±1 LSB maximum are guaranteed monotonic at operating conditions. See the test circuit in Figure 23. 6 Resistor Terminal A, Terminal B, and Wiper W have no limitations on polarity with respect to each other. 7 Guaranteed by design and not subject to production test. 8 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use VDD = 5 V. timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V. 13 The propagation delay depends on the values of VDD, RL, and CL (see the Theory of Operation section).

TA = 25°C, unless otherwise noted.

1 Maximum terminal current is bounded by the maximum current handling of the

voltage across any two of the A, B, and W terminals at a given resistance. ing conditions for extended periods may affect product reliability. JEDEC natural convection environment. centerline, measured in a JEDEC θJB environment. Table 3. Thermal Resistance

1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal

test board. See JEDEC JESD-51. sitive devices in and ESD-protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. model (CDM) per ANSI/ESDA/JEDEC JS-002. Table 4. AD5204/AD5206, 24-Lead TSSOP, 24-Lead SOIC, and 32-Lead LFCSP damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 6. AD5204 SOIC/TSSOP Pin Configuration Table 5. AD5204 SOIC/TSSOP Pin Function Descriptions 5 PR Preset to Midscale (Active Low). This pin sets the RDAC registers to 0x80. 6 VDD Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. It is the sum of |VDD| + |VSS| < 5.5 V. 7 SHDN Terminal A Open-Circuit Shutdown (Active Low Input). This pin controls VR 1 through VR 4. 8 SDI Serial Data Input. Data is input MSB first. 9 CLK Serial Clock Input. This pin is positive edge triggered. 10 SDO Serial Data Output. This pin is an open-drain transistor and requires a pull-up resistor. 14 W3 Wiper RDAC 3. Address = 0102. 17 W1 Wiper RDAC 1. Address = 0002. 20 W2 Wiper RDAC 2. Address = 0012. 23 W4 Wiper RDAC 4. Address = 0112.

Figure 7. AD5204 LFCSP Pin Configuration Table 6. AD5204 LFCSP Pin Function Descriptions 7 W3 Wiper RDAC 3. Address = 0102. 11 W1 Wiper RDAC 1. Address = 0002. 14 W2 Wiper RDAC 2. Address = 0012. 19 W4 Wiper RDAC 4. Address = 0112. 27 PR Preset to Midscale (Active Low). This pin sets the RDAC registers to 0x80. 28 VDD Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. It is the sum of |VDD| + |VSS| < 5.5 V. 29 SHDN Terminal A Open-Circuit Shutdown (Active Low Input). This pin controls VR 1 through VR 4. 30 SDI Serial Data Input. Data is input MSB first. 31 CLK Serial Clock Input. This pin is positive edge triggered. 32 SDO Serial Data Output. This pin is an open-drain transistor and requires a pull-up resistor.

Figure 8. AD5206 SOIC/TSSOP Pin Configuration Table 7. AD5206 Pin Function Descriptions 2 W6 Wiper RDAC 6. Address = 1012. loaded into the target RDAC latch. 6 VDD Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. It is the sum of |VDD| + |VSS| < 5.5 V. 7 SDI Serial Data Input. Data is input MSB first. 8 CLK Serial Clock Input. This pin is positive edge triggered. 11 W5 Wiper RDAC 5. Address = 1002. 14 W3 Wiper RDAC 3. Address = 0102. 17 W1 Wiper RDAC 1. Address = 0002. 20 W2 Wiper RDAC 2. Address = 0012. 23 W4 Wiper RDAC 4. Address = 0112.

Table 8. Serial Data-Word Format ing in only leakage currents being consumed in the VR structure. device is returned to operational mode from power shutdown. Figure 31. AD5204/AD5206 Equivalent RDAC Circuit Terminal B is available with values of 10 kΩ, 50 kΩ, and 100 kΩ. RDAC latch is decoded to select one of the 256 possible settings. the nominal end-to-end resistance. latch codes (applies to the 10 kΩ potentiometer). Table 9. Output Resistance Values for the RDAC Latch Codes—VB = 0 V and or possible destruction of the internal switch contact, can occur. W and Terminal A produces a digitally controlled resistance, RWA. the nominal end-to-end resistance.

©1999-2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. G | 16 of 16 Package Drawing (Option) Package Type Package Description RW-24 SOIC_W 24-Lead Standard Small Outline Package RU-24 TSSOP 24-Lead Thin Shrink Small Outline Package CP-32-13 LFCSP 32-Lead Lead Frame Chip Scale Package For the latest package outline information and land patterns (footprints), go to Package Index. Updated: May 11, 2022 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option AD5204BCPZ10-REEL -40°C to +85°C 32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)Reel, 5000 CP-32-13 AD5204BCPZ10-REEL7 -40°C to +85°C 32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)Reel, 1500 CP-32-13 AD5204BRUZ10 -40°C to +85°C 24-Lead TSSOP Tube, 62 RU-24 AD5204BRUZ100 -40°C to +85°C 24-Lead TSSOP Tube, 62 RU-24 AD5204BRUZ100-R7 -40°C to +85°C 24-Lead TSSOP Reel, 1000 RU-24 AD5204BRUZ10-REEL7 -40°C to +85°C 24-Lead TSSOP Reel, 1000 RU-24 AD5204BRUZ50 -40°C to +85°C 24-Lead TSSOP Tube, 62 RU-24 AD5204BRUZ50-REEL7 -40°C to +85°C 24-Lead TSSOP Reel, 1000 RU-24 AD5204BRZ10 -40°C to +85°C 24-Lead SOIC (Wide) Tube, 31 RW-24 AD5204BRZ100 -40°C to +85°C 24-Lead SOIC (Wide) Tube, 31 RW-24 AD5204BRZ10-REEL -40°C to +85°C 24-Lead SOIC (Wide) Reel, 1000 RW-24 AD5204BRZ50-REEL -40°C to +85°C 24-Lead SOIC (Wide) Reel, 1000 RW-24 AD5206BRUZ10 -40°C to +85°C 24-Lead TSSOP Tube, 62 RU-24 AD5206BRUZ100-RL7 -40°C to +85°C 24-Lead TSSOP Reel, 1000 RU-24 AD5206BRUZ10-RL7 -40°C to +85°C 24-Lead TSSOP Reel, 1000 RU-24 AD5206BRUZ50 -40°C to +85°C 24-Lead TSSOP Tube, 62 RU-24 AD5206BRUZ50-REEL7 -40°C to +85°C 24-Lead TSSOP Reel, 1000 RU-24 AD5206BRZ10 -40°C to +85°C 24-Lead SOIC (Wide) Tube, 31 RW-24 AD5206BRZ100 -40°C to +85°C 24-Lead SOIC (Wide) Tube, 31 RW-24 AD5206BRZ10-REEL -40°C to +85°C 24-Lead SOIC (Wide) Reel, 1000 RW-24 AD5206BRZ50 -40°C to +85°C 24-Lead SOIC (Wide) Tube, 31 RW-24 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model Description EVAL-AD5204SDZ1 Evaluation Board 1 Z = RoHS Compliant Part.