AD52050 ESMT | Alldatasheet
Document overview
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Technical content
Features
Single supply voltage 4.5V ~ 14.4V for loudspeaker driver Built-in LDO output 5.5V for others Loudspeaker power from 12V supply BTL Mode: 8W/CH into 8 @1% THD+N BTL Mode: 10W/CH into 6 @<1% THD+N BTL Mode: 12W/CH into 4 @<1% THD+N PBTL Mode: 16W/CH into 4 @1% THD+N Loudspeaker power from 12V supply BTL Mode: 10W/CH into 8 @10% THD+N BTL Mode: 13W/CH into 6 @10% THD+N BTL Mode: 15W/CH into 4@10% THD+N PBTL Mode: 20W/CH into 4 @10% THD+N 93% efficient Class -D operation eliminates need for heat sink Differential inputs Internal oscillator Short-Circuit protection with auto recovery option Under-Voltage detection Over-Voltage protection Pop noise and click noise reduction Adjustable power limit function for speaker protection Output DC detection for speaker protection Filter-Free operation Over temperature protection with auto recovery Superior EMC performance
Applications
TV audio Boom-Box Powered speaker Monitors Consumer Audio Equipment
Description
The AD52050 is a high efficiency stereo class -D audio amplifier with adjustable power limit function . The loudspeaker driver operates from 4.5V~14.4V supply voltage. It can deliver 15W/CH output power into 4 loudspeaker within 10% THD+N at 12 V supply voltage and without external heat sink when playing music. The adjustable power limit function allows user to set a voltage rail lower than half of 5.5V to limit the amount of current through the speaker. Output DC detection p revents speaker damage from long -time current stress . AD52050 provides superior EMC performance for filter-free application. The output short circuit and over temperature protection include auto-recovery feature. Simplified Application Circuit
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 2/22 Pin Assignments BSPL PVCCL LINP GVDD PLIM RINN PVCCR OUTNR OUTPL 1 2 3 4 5 15 14 13 12 11 SD FAULT LINN AVCC OUTPR BSPR RINP BSNR OUTNL AGNDBSNL PGND TQFN 20L (4mmx4mm) (Top VIEW) NC LINN AVCC NC LINP PVCCL PGND OUTPL BSNL OUTNL BSPL 15NC PLIM AGND GVDD RINP PVCCR PGND BSNR OUTNR BSPR RINN OUTPR E-TSSOP-28L SD FAULT (TOP VIEW) NC PVCCL PVCCR Pin Description NAME E-TSSOP 28L TQFN 20L TYP DESCRIPTION SD 1 3 I Shutdown signal for IC (low = disabled, high = operational). Voltage compliance to AVCC. FAULT 2 4 O Open drain output used to display short circuit or dc detect fault. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both short circuit faults and dc detect faults must be reset by cycling AVCC. LINP 3 5 I Positive audio input for left channel. LINN 4 6 I Negative audio input for left channel. NC 5 N/A N/A NC pin NC 6 N/A N/A NC pin AVCC 7 7 P Analog supply. AGND 8 8 P Analog signal ground. Connect to the thermal pad. GVDD 9 9 O 5.5V regulated output, also used as supply for PLIMIT function. PLIMIT 10 10 I Power limit level adjustment. Connect a resistor divider from GVDD to GND to set power limit. Give V(PLIMIT) <2.4V to set power limit level. Connect to GVDD (>2.4V) or GND to disable power limit function. RINN 11 11 I Negative audio input for right channel. RINP 12 12 I Positive audio input for right channel. NC 13 N/A N/A NC pin
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 3/22 NC 14 N/A N/A NC pin PVCCR 15,16 13 P High-voltage power supply for right -channel. Right ch annel and left channel power supply inputs are connect internal. BSPR 17 14 I Bootstrap I/O for right channel, positive high side FET. OUTPR 18 15 O Class-D H-bridge positive output for right channel. PGND 19 Exposed pad P Power ground for the H-bridges. OUTNR 20 16 O Class-D H-bridge negative output for right channel. BSNR 21 17 I Bootstrap I/O for right channel, negative high side FET. BSNL 22 18 I Bootstrap I/O for left channel, negative high side FET. OUTNL 23 19 O Class-D H-bridge negative output for left channel. PGND 24 Exposed pad P Power ground for the H-bridges. OUTPL 25 20 O Class-D H-bridge positive output for left channel. BSPL 26 1 I Bootstrap I/O for left channel, positive high side FET. PVCCL 27,28 2 P High-voltage power supply fo r right -channel. Right channel and left channel power supply inputs are connect internal. Thermal Pad PGND P Must be soldered to PCB’s ground plane.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 4/22
Ordering Information
Product ID Package Packing / MPQ Comments AD52050-26QG28NRR E-TSSOP 28L
2500 Units / Reel
2500 Units / Small Box
AD52050-26HI20NRR TQFN 20L (4mm x 4mm)
3000 Units / Reel
6000 Units / Small Box
Package Type Device No. θJA(℃/W) θ JT(℃/W) Ψ JT(℃/W) Exposed Thermal Pad E-TSSOP 28L AD52050 28 27.1 1.33 Yes (Note 1) TQFN 20L 46 52.8 1.3 Note 1.1: The thermal pad is located at the bottom of the package. To optimize thermal performance, soldering the thermal pad to the PCB’s ground plane is necessary. Note 1.2: θ JA is simulated on a room temperature ( TA=25℃), natural convection environment test board, which is constructed with a thermally efficient, 4 -layers PCB (2S2P). The measurement is simulated using the JEDEC51-5 thermal measurement standard. Note 1.3: θ JT represents the thermal resistance for the heat flow between the chip junction and the package’s top surface. It’s extracted from the simulation data with obtaining a cold plate on the package top. Note 1.4: ΨJT represents the thermal parameter for the heat flow between the chip junction and the package’s top surface center. It’s extracted from the simulation data for obtainingθ JA, using a procedure described in JESD51-5. Marking Information AD52050
- Marking Information Line 1：LOGO Line 2：Product No Line 3：Tracking Code PIN1 DOT ESMT AD52050 Tracking Code
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 5/22 Absolute Maximum Ratings Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT PVCC Supply voltage PVCCL, PVCCR, AVCC -0.3 16 V VI Interface pin voltage SD, FAULT -0.3 16 V PLIM -0.3 5.5 TA Operating free-air temperature range -40 85 oC TJ Operating junction temperature range -40 150 oC Tstg Storage temperature range -65 150 oC RL Minimum Load Resistance 3.2 Recommended Operating Conditions SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT PVCC Supply voltage PVCCL, PVCCR, AVCC 4.5 14.4 V VI Signal input level voltage LINP , LINN, RINP, RINN 2 Vrms VIH High-level input voltage SD 2 V VIL Low-level input voltage SD 0.8 V VOL Low-level output voltage FAULT , RPULL-UP=100k, VCC=16V 0.8 V IIH High-level input current SD , VI=2V, PVCC=12V 50 uA IIL Low-level input current SD , VI=0.8V, PVCC=12V 5 uA IOH High-level output current VI=2V, PVCC=12V 50 uA IOL Low-level output current VI=0.8V, PVCC=12V 50 uA TA Operating free-air temperature -40 85 oC
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 6/22 General Electrical Characteristics PVCC=12V, RL=8TA=25°C (unless otherwise noted) SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT ICC(q) Quiescent supply current SD=2V, no load, PVCC=12V 8 12 mA ICC(SD) Quiescent supply current in shutdown mode SD=0.8V, no load, PVCC=12V < 12 25 uA RDS(on) Drain-source on-state resistance-High side NMOS PVCC=12V, Id=500mA, TJ=25 oC 220 m Drain-source on-state resistance-Low side NMOS 220 m |VOS| Class-D output offset voltage (measured differential) PVCC=12V VI=0V, Gain=26dB 1.5 10 mV tON Turn-on time SD=2V 90 ms tOFF Turn-off time SD=0.8V 2 s GVDD Regulator output IGVDD=0.1mA 5.225 5.5 5.775 V G Gain PVCC=12V, SD=2V 25 26 27 dB
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 7/22 Electrical Characteristics and Specifications of Loudspeaker Driver (BTL , Stereo) PVCC=12V, RL=8TA=25°C (unless otherwise noted) SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT PO Output power THD+N=10%, f=1kHz, 8 10 W THD+N=10%, f=1kHz, 6 13 THD+N=10%, f=1kHz, 4 15 THD+N Total harmonic distortion plus noise PVCC=12V, RL=8f=1kHz, PO=5W (half-power) 0.03 % PVCC=12V, RL=6f=1kHz, PO=6.5W (half-power) 0.03 PVCC=12V, RL=4f=1kHz, PO=7.5W (half-power) 0.03 SNR Signal to noise ratio Maximum output at THD+N<1%, f=1kHz, Gain=26dB, a-weighted 100 dB Vn Output integrated noise F=20Hz ~ 20kHz, Gain=26dB, a-weighted filter, RL=8 90 V KSVR Power Supply Rejection Ratio Vripple=200mVpp at 1kHz, Gain=26dB, inputs ac-grounded -70 dB Crosstalk Crosstalk F=1kHz, VO=1Vrms, Gain=26dB -95 dB fOSC Oscillator frequency 250 310 370 kHz TSENSOR Thermal trip point 150 oC Thermal hysteresis 25 oC Electrical Characteristics and Specifications of Loudspeaker Driver (PBTL , Mono) PVCC=12V, RL=4TA=25°C (unless otherwise noted) PO Output power THD+N=1%, f=1kHz, 4 16 W THD+N=10%, f=1kHz, 4 20 THD+N Total harmonic distortion plus noise PVCC=12V, RL=4f=1kHz, PO=10W 0.02 % SNR Signal to noise ratio Maximum output at THD+N<1%, f=1kHz, Gain=26dB, a-weighted 96 dB Vn Output integrated noise F=20Hz ~ 20kHz, Gain=26dB, a-weighted filter, RL=8 90 V KSVR Power Supply Rejection Ratio Vripple=200mVpp at 1kHz, Gain=26dB, inputs ac-grounded -70 dB
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 8/22 Typical Characteristics THD+N vs. Output Power, 8 load (Stereo) THD+N vs. Output Power, 4 load (Stereo) 0.01 0.02 0.05 0.1 0.2 0.5 10m 20 20m 50m 100m 200m 500m 1 2 5 10 Gain=26dB Load=8ohm+66uH Output Power(W) THD+N(%) 0.01 0.02 0.05 0.1 0.2 0.5 10m 20 20m 50m 100m 200m 500m 1 2 5 10 Gain=26dB Load=4ohm+33uH Output Power(W) THD+N(%) THD+N vs. Output Power, 6 load (Stereo) THD + N (%) vs. Frequency, 8 load (Stereo) 0.01 0.02 0.05 0.1 0.2 0.5 10m 20 20m 50m 100m 200m 500m 1 2 5 10 Gain=26dB Load=6ohm+47uH Output Power(W) THD+N(%) 0.0001 0.001 0.01 0.1 20 20k 50 100 200 500 1k 2k 5k 10k Gain=26dB Load=8ohm+66uH THD+N(%) Frequency(Hz) Noise, 8 load (Stereo) Efficiency (Stereo 8 load) / 2ch 10u 200u 20u 30u 40u 50u 60u 80u 100u 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k Gain=26dB Load=8ohm+66uH V Frequency(Hz) 100 0 5 10 15 20 25 Efficiency(%) Output power(W) 12V 14.4V
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 9/22 Cross-Talk ,8 load (Stereo) THD + N (%) vs. Frequency, 4 load (Mono) -140 -50 -130 -120 -110 -100 -90 -80 -70 -60 20 20k 50 100 200 500 1k 2k 5k 10k Gain=26dB Load=8ohm+66uH Po=5W dB Frequency(Hz) 0.0001 0.001 0.01 0.1 20 20k 50 100 200 500 1k 2k 5k 10k Gain=26dB Load=4ohm+33uH THD+N(%) Frequency(Hz) 10W THD+N vs. Output Power, 4 load (Mono) Efficiency (Mono 4 load) 0.01 0.02 0.05 0.1 0.2 0.5 10m 30 20m 50m 100m 200m 500m 1 2 5 10 20 Gain=26dB Load=4ohm+33uH Output Power(W) THD+N(%) 100 0 5 10 15 20 25 30 35 40 Efficiency(%) Output power(W) 12V 14.4V Supply voltage vs. Output Power, 8 load (Stereo) Supply voltage vs. Output Power, 6 load (Stereo) 4 6 8 10 12 14 16 Output Power (W) PVCC (V) THD+N=10% THD+N=1% 4 6 8 10 12 14 16 Output Power (W) PVCC (V) THD+N=10% THD+N=1%
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 10/22 Supply voltage vs. Output Power, 4 load (Stereo) 4 6 8 10 12 14 16 Output Power (W) PVCC (V) THD+N=10% THD+N=1% Note: Dashed Line represent thermally limited regions.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 11/22 Functional Block Diagram
SD pin low will let AD52050 operate in low-current state for power conservation. shutdown mode in advance of removing the power supply. SD , it is necessary to cycle the PVCC supply. the DC detect threshold is listed in table2. Table 1. DC Detect Threshold Table 2. Output DC Detect Duty (for Either Channel)
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 13/22 Thermal protection If the internal junction temperature is higher than 1 50oC, the outputs of loudspeaker drivers will be disable d and at low state. The temperature for AD52050 returning to normal operation is about 125oC. The variation of protected temperature is about 10%. Thermal protection faults are NOT reported on the FAULT pin. Short-circuit protection To p rotect loudspeaker drivers from over -current damage, AD52050 has built -in short-circuit protection circuit. When the wires connected to loudspeakers are shorted to each other or shorted to VSS or to PVCC, overload detectors may activate. Once one of right and left channel overload detectors are active, the amplifier outputs will enter a Hi-Z state and the protection latch is engaged. The short protection fault is reported on FAULT pin as a low state. The latch can be cleared by reset SD or power supply cycling. The short circuit protection latch can have auto-recovery function by connect the FAULT pin directly to SD pin. The latch state will be released after 420msec, and the short protection latch will re-cycle if output overload is detected again. Under-voltage detection When the GVDD voltage is lower than 2. 8V or the AVCC voltage is lower than 4V, loudspeaker drivers of right/left channel will be disabled and kept at low state. Otherwise, AD52050 return to normal operation. PBTL (Mono) function AD52050 provides the application of parallel BTL operation with two outputs of each channel connected directly. If connect INPL and INNL directly to Ground (without capacitors) this sets the device in Mono mode during power up. Connect OUTPR and OUTNR together for the positive speaker terminal a nd OUTNL and OUTPL together for the negative pin. Analog input signal is applied to INPR and INNR. Over-voltage protection When the PVCC voltage is higher than 15.5V, loudspeaker will be disabled kept at low state. The protection status will be released as PVCC lower than 15V.
PLIMIT pin. The voltage VPLIMIT sets a limit on the output peak -to-peak voltage. PLIMIT is adjustable from 1.46V~2.75V. Table 3. BTL PLIMIT Typical OperationⅠ
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 15/22
Application information
Input capacitors (Cin) The performance at low frequency (bass) is affected by the corner frequency (fc) of the high-pass filter composed of input resistor (R in) and input capacitor (C in), determined in equation (2). Typically, a 0.1 F or 1 F ceramic ca pacitor is suggested for C in. The resistance of input resistors is 30k at gain +26dB setting in AD52050. However, there is 20% variation in input resistance from production variation. 2HzCR 2 inin c π Ferrite Bead selection If the traces from the AD52050 to speaker are short, the ferrite bead filters can reduce the high frequency emissions to meet FCC requirements. A ferrite bead that has very low impedance at low frequency and high impedance at high frequency (above 1MHz) is recommended. The impedance of the ferrite bead can be used along with a small capacitor with a value around 1000pF to reduce the frequency spectrum of the signal to an acceptable level. FB 1000pF 1000pFFB OUTP OUTN Figure 2. Typical Ferrite Bead Filter typical output filter for 4 speaker with a cut-off frequency of 27 kHz.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 17/22 Application Circuit Example Application circuit for BTL (Stereo) mode configuration and Single-Ended Input P V C C NC L IN N A V C C NC L IN P P V C C L P V C C L P G N D O U T P L B S N L O U T N L BSPL AD 52050 NC NC P L IM A G N D G V D D R IN P P V C C R P V C C R P G N D B S N R O U T N R BSPR R IN N O U T P R SD F A U L T 100 k 1 k S h u td o w n C o n tro l 1 uF 1 uF 1 uF 1 uF 1 uF 1 uF FB 1000 pF 1000 pFFB P V C C 100 uF0 .1 uF P V C C L -c h In p u t R -c h In p u t R P L1 R P L2 100 uF0 .1 uF FB 1000 pF 1000 pFFB 0 .22 uF 0 .22 uF 0 .22 uF 0 .22 uF 1 k 1 k N o te : T h e s e re s is ta n c e s m u s t b e c o n n e c te d to g ro u n d, re s is ta n c e= 1 K o h m 1 uF 0 .1 uF 100 Note 2: These resistances must be connected to ground, resistance=1Kohm. Note 3: These capacitors should be change to 0.47uF, while the PVCC<=5V. Note 4: The under-voltage threshold for AVCC could be adjusted by RAVCC, the formula will be followed K30 4-AVCCRAVCC , RAVCC=100ohm minimum is requirement in AD52050. Note 2 Note 2 Note 3 Note 3 Note 3 Note 3 Note 4
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 18/22 Application Circuit Example Application circuit for parallel BTL (Mono) mode configuration and Single-Ended Input P V C C NC L IN N A V C C NC L IN P P V C C L P V C C L P G N D O U T P L B S N L O U T N L BSPL AD 52050 NC NC P L IM A G N D G V D D R IN P P V C C R P V C C R P G N D B S N R O U T N R BSPR R IN N O U T P R SD F A U L T 100 k 1 k S h u td o w n C o n tro l 1 uF 1 uF 1 uF 1 uF FB 1000 pF 1000 pFFB P V C C 100 uF0 .1 uF P V C C R -c h In p u t R P L1 R P L2 100 uF0 .1 uF 0 .47 uF 0 .47 uF N o te. B e n o te d th a t in p u t s h o u ld b e a ppl ie d o n R-C h a n n e l o n ly fo r M o n o a p p lic a tio n. 1 k 1 uF 0 .1 uF 100 Note 5: These resistances must be connected to ground, resistance=1Kohm. Note 6: The under-voltage threshold for AVCC could be adjusted by RAVCC, the formula will be followed K30 4-AVCCRAVCC , RAVCC=100ohm minimum is requirement in AD52050. Note 7: Be noted that input should be applied on R-channel only for Mono application Note 6 Note 5
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 19/22 Package Dimensions E-TSSOP 28L (173 mil) SIDE VIEW L PIN#1 MARK E E1 b TOP VIEW c DETAIL A A D e 1 14 1528 1 14 Exposed pad Min Max Dimension in mm A -- 1.20 Min Max A1 0.05 0.15 D2 5.00 6.40 b 0.19 0.30 E2 2.50 2.90 c 0.09 0.20 D 9.60 9.80 E 4.30 4.50 E1 6.30 6.50 e L 0.45 0.75
0.65 BSC
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 20/22 Package Dimensions TQFN-20L (4mm x 4mm) TOP VIEW D E BOTTOM VIEW L e SIDE VIEW AA3A1 b 16 20 10 6 1111 Min Max Dimention in mm A 0.70 0.85 Min Max A1 0.00 0.05 D2 1.90 2.05 A3 0.18 0.03 E2 1.90 2.05 b 0.18 0.30 D 3.90 4.10 E 3.90 4.10 e L 0.30 0.50 Symbol Dimension in mm
0.50 BSC
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 21/22
Revision History
0.1 2017.12.29 Initial version. 0.2 2018.07.24 Added TQFN 20L package option into. 0.3 2018.09.13 Update typical characteristics. 1.0 2019.03.21 1.Remove “Preliminary” reversion to 1.0, modify Package Dimensions 2.Modify gain spec & order information 1.1 2020.01.09 Update operation descriptions for under-voltage detection. Update application circuit. 1.2 2020.12.07 Update application information. Update application circuit (added RAVCC node).
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2020 Revision: 1.2 22/22 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this docum ent are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted unde r any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where f ailure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.