DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 20
Technical content
Rev. C | Page 2 of 20 TABLE OF CONTENTS
REVISION HISTORY
7/10—Rev. B to Rev. C Changes to Digital Input and Output Voltage to GND 5/09—Rev. A to Rev. B 11/07—Rev. 0 to Rev. A Changed R 9/99—Revision 0: Initial Version
Rev. C | Page 3 of 20 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 5 V ± 10% or 3 V ± 10%, VSS = 0 V , VA = VDD, VB = 0 V , −40°C < TA < +85°C, unless otherwise noted. Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE2 Resistor Differential NL3 R-DNL RWB, VA = no connect −1 ±0.25 +1 LSB Resistor Nonlinearity Error3 R-INL RWB, VA = no connect −2 ±0.5 +2 LSB Nominal Resistor Tolerance4 ΔR AB TA = 25°C −30 +30 % Resistance Temperature Coefficient ΔRAB/ΔT VAB = VDD, wiper = no connect 700 ppm/°C Nominal Resistance Match ΔR/RAB Channel 1 to Channel 2, Channel 3, and Channel 4, or to Channel 5 and Channel 6; VAB = VDD 0.25 1.5 % Wiper Resistance RW IW = 1 V/R, VDD = 5 V 50 100 Ω DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE2 Resolution N 8 Bits Differential Nonlinearity5 DNL −1 ±0.25 +1 LSB Integral Nonlinearity5 INL −2 ±0.5 +2 LSB Voltage Divider Temperature Coefficient ΔVW/ΔT Code = 0x40 15 ppm/°C Full-Scale Error VWFSE Code = 0x7F −2 −1 0 LSB Zero-Scale Error VWZSE Code = 0x00 0 1 2 LSB RESISTOR TERMINALS Voltage Range6 V A, VB, VW VSS VDD V Capacitance7 Ax, Bx CA, CB f = 1 MHz, measured to GND, code = 0x40 45 pF Capacitance7 Wx CW f = 1 MHz, measured to GND, code = 0x40 60 pF Shutdown Current8 I A_SD 0.01 5 μA Common-Mode Leakage ICM VA = VB = VW = 0, VDD = +2.7 V, VSS = −2.5 V 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V/3 V 2.4/2.1 V Input Logic Low VIL VDD = 5 V/3 V 0.8/0.6 V Output Logic High VOH RPULL–UP = 1 kΩ to 5 V 4.9 V Output Logic Low VOL IOL = 1.6 mA, VLOGIC = 5 V 0.4 V Input Current IIL VIN = 0 V or 5 V ±1 μA Input Capacitance7 C IL 5 pF POWER SUPPLIES Power Single-Supply Range VDD range VSS = 0 V 2.7 5.5 V Power Dual-Supply Range VDD/VSS range ±2.3 ±2.7 V Positive Supply Current IDD VIH = 5 V or VIL = 0 V 12 60 μA Negative Supply Current ISS VSS = −2.5 V, VDD = +2.7 V 12 60 μA Power Dissipation9 P DISS VIH = 5 V or VIL = 0 V 0.3 mW Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% 0.0002 0.005 %/% DYNAMIC CHARACTERISTICS7, 10 Bandwidth −3 dB BW_10K RAB = 10 kΩ 721 kHz BW_50K RAB = 50 kΩ 137 kHz BW_100K RAB = 100 kΩ 69 kHz Total Harmonic Distortion THDW VA = 1.414 V rms, VB = 0 V dc, f = 1 kHz 0.004 % VW Settling Time (10 kΩ/50 kΩ/100 kΩ) tS VA = 5 V, VB = 0 V, ±1 LSB error band 2/9/18 μs Resistor Noise Voltage eN_WB RWB = 5 kΩ, f = 1 kHz, PR = 0 9 nV/√Hz
Rev. C | Page 4 of 20 Parameter Symbol Conditions Min Typ 1 Max Unit INTERFACE TIMING CHARACTERISTICS7, 11, 12 Input Clock Pulse Width tCH, tCL Clock level high or low 20 ns Data Setup Time tDS 5 ns Data Hold Time tDH 5 ns CLK-to-SDO Propagation Delay13 t PD RL = 2 kΩ , CL < 20 pF 1 150 ns CS Setup Time tCSS 15 ns CS High Pulse Width tCSW 40 ns Reset Pulse Width tRS 90 ns CLK Fall to CS Fall Setup tCSH0 0 ns CLK Fall to CS Rise Hold Time tCSH1 0 ns CS Rise to Clock Rise Setup tCS1 10 ns 1 Typicals represent average readings at 25°C and VDD = 5 V. 2 Applies to all VRs. 3 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal position between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 28. IW = VDD/R for both VDD = 3 V and VDD = 5 V. 4 VAB = VDD, wiper (VW) = no connect. 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic at operating conditions. See the test circuit in Figure 27. 6 Resistor Terminal A, Terminal B, and Wiper W have no limitations on polarity with respect to each other. 7 Guaranteed by design and not subject to production test. 8 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use VDD = 5 V. 11 Applies to all parts. 12 See the timing diagrams (Figure 3 to Figure 5) for the location of the measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V. 13 The propagation delay depends on the values of VDD, RL, and CL (see the Operation section).
Rev. C | Page 6 of 20 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Parameter Rating VDD to GND −0.3 V to +7 V VSS to GND 0 V to −7 V VDD to VSS 7 V VA, VB, VW to GND VSS, VDD IA, IB, IW Pulsed1 ±20 mA Continuous 10 kΩ End-to-End Resistance ±11 mA 50 kΩ and 100 kΩ End-to-End Resistance ±2.5 mA Digital Input and Output Voltage to GND −0.3 V to (VDD + 0.3 V) or 7 V (whichever is less) Operating Temperature Range −40°C to +85°C Maximum Junction Temperature (TJ max) 150°C Storage Temperature −65°C to +150°C Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec Package Power Dissipation (TJ max − TA)/θJA Thermal Resistance, θJA2 PDIP (N-24-1) 63°C/W SOIC (RW-24) 52°C/W TSSOP (RU-24) 50°C/W LFCSP (CP-32-3) 32.5°C/W ESD CAUTION
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Thermal resistance (JEDEC 4-layer (2S2P) board). Paddle soldered to board.
Figure 6. AD5204 SOIC/TSSOP/PDIP Pin Configuration Table 3. AD5204 SOIC/TSSOP/PDIP Pin Function Descriptions bits, and then it is loaded into the target RDAC latch. 5 PR Preset to Midscale (Active Low). This pin sets the RDAC registers to 0x80. 6 VDD Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. It is the sum of |VDD| + |VSS| < 5.5 V. 7 SHDN Terminal A Open-Circuit Shutdown (Active Low Input). This pin controls VR 1 through VR 4. 8 SDI Serial Data Input. Data is input MSB first. 9 CLK Serial Clock Input. This pin is positive edge triggered. 10 SDO Serial Data Output. This pin is an open-drain transistor and requires a pull-up resistor. 14 W3 Wiper RDAC 3. Address = 0102. 17 W1 Wiper RDAC 1. Address = 0002. 20 W2 Wiper RDAC 2. Address = 0012. 23 W4 Wiper RDAC 4. Address = 0112.
- THE LFCSP PACKAGE HAS AN EXPOSED
Figure 7. AD5204 LFCSP Pin Configuration Table 4. AD5204 LFCSP Pin Function Descriptions 7 W3 Wiper RDAC 3. Address = 0102. 11 W1 Wiper RDAC 1. Address = 0002. 14 W2 Wiper RDAC 2. Address = 0012. 19 W4 Wiper RDAC 4. Address = 0112. bits, and then it is loaded into the target RDAC latch. 27 PR Preset to Midscale (Active Low). This pin sets the RDAC registers to 0x80. 28 V DD Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. It is the sum of |VDD| + |VSS| < 5.5 V. 29 SHDN Terminal A Open-Circuit Shutdown (Active Low Input). This pin controls VR 1 through VR 4. 30 SDI Serial Data Input. Data is input MSB first. 31 CLK Serial Clock Input. This pin is positive edge triggered. 32 SDO Serial Data Output. This pin is an open-drain transistor and requires a pull-up resistor.
Figure 8. AD5206 SOIC/TSSOP/PDIP Pin Configuration Table 5. AD5206 Pin Function Descriptions 2 W6 Wiper RDAC 6. Address = 1012. address bits, and then it is loaded into the target RDAC latch. 6 VDD Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. It is the sum of |VDD| + |VSS| < 5.5 V. 7 SDI Serial Data Input. Data is input MSB first. 8 CLK Serial Clock Input. This pin is positive edge triggered. 11 W5 Wiper RDAC 5. Address = 1002. 14 W3 Wiper RDAC 3. Address = 0102. 17 W1 Wiper RDAC 1. Address = 0002. 20 W2 Wiper RDAC 2. Address = 0012. 23 W4 Wiper RDAC 4. Address = 0112.
Figure 9. Incremental On Resistance of the Wiper vs. Voltage Figure 12. −3 dB Bandwidth vs. Terminal Resistance, Figure 10. Gain Flatness vs. Frequency Figure 13. Bandwidth vs. Code, 10 kΩ Version Figure 11. −3 dB Bandwidth vs. Terminal Resistance,
2.7 V Single-Supply Operation
Figure 14. Bandwidth vs. Code, 50 kΩ Version
first. Table 6 provides the serial register data-word format. Table 6. Serial Data-Word Format to operational mode from power shutdown. Figure 21. AD5204/AD5206 Equivalent RDAC Circuit
Terminal B is available with values of 10 kΩ, 50 kΩ, and 100 kΩ. resistance value; for example, 10 kΩ = 10 and 100 kΩ = 100. RAB is the nominal end-to-end resistance. RDAC latch codes (applies to the 10 kΩ potentiometer). Table 7. Output Resistance Values for the RDAC Latch Codes— ±1.35 mA(50 kΩ and 100 kΩ) or pulse current of ±20 mA. RAB is the nominal end-to-end resistance. Table 8. Output Resistance Values for the RDAC Latch Codes— terms of temperature has a 700 ppm/°C temperature coefficient.
proportional to the input voltage applied to a given terminal. Figure 22. Block Diagram
6.40 BSC
0.10 COPLANARITY
Figure 37. 24-Lead Thin Shrink Small Outline Package [TSSOP]
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
3.50 REF
0.60 MAX
0.25 MIN
Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Rev. C | Page 19 of 20 Model1, 2 kΩ Temperature Range Package Description Package Option AD5204BRZ50-REEL 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5204BRU50 50 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRU50-REEL 50 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRU50-REEL7 50 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRUZ50 50 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRUZ50-REEL7 50 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BN100 100 −40°C to +85°C 24-Lead Pl astic Dual In-Line Package [PDIP] N-24-1 AD5204BR100 100 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5204BR100-REEL 100 −40°C to +85°C 24-Lead St andard Small Outline Package [SOIC_W] RW-24 AD5204BRZ100 100 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5204BRZ100-REEL 100 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5204BRU100 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRU100-REEL7 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRUZ100 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5204BRUZ100-R7 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BN10 10 −40°C to +85°C 24-Lead Pl astic Dual In-Line Package [PDIP] N-24-1 AD5206BR10 10 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BR10-REEL 10 −40°C to +85°C 24-Lead St andard Small Outline Package [SOIC_W] RW-24 AD5206BRZ10 10 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRZ10-REEL 10 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRU10 10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BRU10-REEL7 10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BRUZ10 10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BRUZ10-RL7 10 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BN50 50 −40°C to +85°C 24-Lead Pl astic Dual In-Line Package [PDIP] N-24-1 AD5206BR50 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BR50-REEL 50 −40°C to +85°C 24-Lead St andard Small Outline Package [SOIC_W] RW-24 AD5206BRZ50 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRU50 50 −40°C to +85°C 24-Lead Stan dard Small Outline Package [SOIC_W] RW-24 AD5206BRU50-REEL 50 −40°C to +85°C 24-Lead St andard Small Outline Package [SOIC_W] RW-24 AD5206BRU50-REEL7 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRUZ50 50 −40°C to +85°C 24-Lead Stan dard Small Outline Package [SOIC_W] RW-24 AD5206BRUZ50-REEL7 50 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BN100 100 −40°C to +85°C 24-Lead Pl astic Dual In-Line Package [PDIP] N-24-1 AD5206BR100 100 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BR100-REEL 100 −40°C to +85°C 24-Lead St andard Small Outline Package [SOIC_W] RW-24 AD5206BRZ100 100 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD5206BRU100 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BRU100-REEL7 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BRUZ100 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5206BRUZ100-RL7 100 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 The AD5204/AD5206 each contains 5,925 transistors. Die size is 92 mil × 114 mil, or 10,488 sq. mil. 2 Z = RoHS Compliant Part.
Rev. C | Page 20 of 20 NOTES ©1999–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06884-0-7/10(C)