AD5203AN10

AD5203 AD | Alldatasheet

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD5203 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 4-Channel, 64-Position Digital Potentiometer FUNCTIONAL BLOCK DIAGRAM SHDN DAC 1 AGND1 VDD DGND SDI CLK CS AD5203 SDO SHDN AGND2 AGND3 AGND4 RS 6-BIT LATCH CK RS 66-BIT LATCH CK RS SHDN DAC 2 SHDN DAC 3 SHDN DAC 4 6-BIT LATCH CK RS 6-BIT LATCH CK RS DAC SELECT A1, A0 8-BIT SERIAL LATCH D CK Q RS

FEATURES

64 Position

Replaces Four Potentiometers 10 kV, 100 k V Power Shutdown—Less than 5 mA 3-Wire SPI-Compatible Serial Data Input

10 MHz Update Data Loading Rate

+2.7 V to +5.5 V Single Supply Operation Midscale Preset

APPLICATIONS

Mechanical Potentiometer Replacement Programmable Filters, Delays, Time Constants Volume Control, Panning Line Impedance Matching Power Supply Adjustment GENERAL DESCRIPTION The AD5203 provides a quad channel, 64-position digitally- controlled variable resistor (VR) device. These parts perform the same electronic adjustment function as a potentiometer or vari- able resistor. The AD5203 contains four independent variable resistors in a 24-lead SOIC and the compact TSSOP-24 pack- ages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digi- tal code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A-to-B terminal resistance of 10 k W , or 100 kW has a – 1% channel-to- channel matching tolerance with a nominal temperature coeffi- cient of 700 ppm/°C. Each VR has its own VR latch which holds its programmed resistance value. These VR latches are updated from an internal serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Eight data bits make up the data word clocked into the serial input register. The data word is decoded where the first two bits determine the address of the VR latch to be loaded, the last 6-bits are data. A serial data output pin at the opposite end of the serial register allows simple daisy- chaining in multiple VR applications without additional external decoding logic. The reset RS pin forces the wiper to the midscale position by loading 20 H into the VR latch. The SHDN pin forces the resis- tor to an end-to-end open circuit condition on terminal A and shorts the wiper to terminal B, achieving a microwatt power shutdown state. When shutdown is returned to logic-high the previous latch settings put the wiper in the same resistance set- ting prior to shutdown. The AD5203 is available in a narrow body P-DIP-24, the 24-lead surface mount package, and the compact 1.1 mm thin TSSOP-24 package. All parts are guaranteed to operate over the extended industrial temperature range of –40 °C to +85°C. For pin compatible higher resolution applications, see the 256- position AD8403 product.

–2– REV. 0 AD5203–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ 1 Max Units DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL 2 R-DNL R WB, VA = No Connect –0.25 – 0.1 +0.25 LSB Resistor Nonlinearity Error 2 R-INL R WB, VA = No Connect –0.5 – 0.1 +0.5 LSB Nominal Resistor Tolerance 3 D RAB –30 +30 % Resistance Temperature Coefficient D RAB/D TV AB = VDD, Wiper = No Connect 700 ppm/ °C Wiper Resistance R W IW = 1 V/RAB 45 100 W Nominal Resistance Match D R/RO CH 1 to CH 2, VAB = VDD , TA = +25°C 0.2 1 % DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Resolution N 6 Bits Differential Nonlinearity Error 4 DNL –0.25 – 0.1 +0.25 LSB Integral Nonlinearity Error 4 INL –0.75 – 0.1 +0.75 LSB Voltage Divider Temperature Coefficient D VW/D T Code = 20 H 20 ppm/ °C Full-Scale Error V WFSE Code = 3FH –0.75 –0.2 0 LSB Zero-Scale Error V WZSE Code = 00H 0 +0.1 +0.75 LSB RESISTOR TERMINALS Voltage Range5 VA, VB, VW 0V DD V Capacitance6 Ax, Bx C A, CB f = 1 MHz, Measured to GND, Code = 20 H 75 pF Capacitance6 Wx C W f = 1 MHz, Measured to GND, Code = 20 H 120 pF Shutdown Supply Current 7 IA_SD VA = VDD, VB = 0 V, SHDN = 0 0.01 5 mA Shutdown Wiper Resistance R W_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V 45 100 W DIGITAL INPUTS AND OUTPUTS Input Logic High V IH VDD = +5 V 2.4 V Input Logic Low V IL VDD = +5 V 0.8 V Input Logic High V IH VDD = +3 V 2.1 V Input Logic Low V IL VDD = +3 V 0.6 V Output Logic High V OH RL = 2.2 kW to VDD VDD–0.1 V Output Logic Low V OL IOL = 1.6 mA, VDD = +5 V 0.4 V Input Current I IL VIN = 0 V or +5 V, V DD = +5 V – 1 mA Input Capacitance 6 CIL 5p F POWER SUPPLIES Power Supply Range V DD Range 2.7 5.5 V Supply Current (CMOS) I DD VIH = VDD or VIL = 0 V 0.01 5 mA Supply Current (TTL) 8 IDD VIH = 2.4 V or V IL = 0.8 V, V DD = +5.5 V 0.9 4 mA Power Dissipation (CMOS) 9 PDISS VIH = VDD or VIL = 0 V, VDD = +5.5 V 27.5 mW Power Supply Sensitivity PSS D VDD = +5 V – 10% 0.0002 0.001 %/% PSS D VDD = +3 V – 10% 0.006 0.03 %/% DYNAMIC CHARACTERISTICS 6, 10 Bandwidth –3 dB BW_10K R AB = 10 kW 600 kHz BW_100K R AB = 100 kW 71 kHz Total Harmonic Distortion THD W VA =1 V rms + 2 V dc, V B = 2 V dc, f = 1 kHz 0.003 % VW Settling Time t S_10K V A = VDD, VB = 0 V, – 1 LSB Error Band 2 ms tS_100K V A = VDD, VB = 0 V, – 1 LSB Error Band 18 ms Resistor Noise Voltage e NWB RWB = 5 kW , f = 1 kHz, RS = 0 9 nV/ ÖHz RWB = 50 kW , f = 1 kHz, RS = 0 29 nV/ ÖHz Crosstalk11 CT VA = VDD, VB = 0 V –65 dB INTERFACE TIMING CHARACTERISTICS Applies to All Parts 6, 12 Input Clock Pulsewidth t CH, tCL Clock Level High or Low 10 ns Data Setup Time t DS 5n s Data Hold Time t DH 5n s CLK to SDO Propagation Delay 13 tPD RL = 2.2 kW , CL < 20 pF 1 25 ns CS Setup Time t CSS 10 ns CS High Pulsewidth t CSW 10 ns Reset Pulsewidth t RS 50 ns CLK Fall to CS Rise Hold Time t CSH 0n s CS Rise to Clock Rise Setup t CS1 10 ns (VDD = +3 V 6 10% or +5 V 6 10%, VA = +VDD, VB = 0 V, –40 8C < TA < +858C unless otherwise noted)

–3–REV. 0 AD5203 NOTES 1Typicals represent average readings at +25 °C and VDD = +5 V. 2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. I W = VDD/R for both VDD = +3 V or VDD = +5 V. 3VAB = VDD, Wiper (VW) = No connect. 4INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of – 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit. 5Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6Guaranteed by design and not subject to production test. 7Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode. 8Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of I DD vs. logic voltage inputs result in minimum power dissipation. 9PDISS is calculated from (I DD · VDD). CMOS logic level inputs result in minimum power dissipation. 10All dynamic characteristics use V DD = +5 V. 11Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change. 12See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using both V DD = +3 V or +5 V. Input logic should have a 1 V/ ms minimum slew rate. 13Propagation delay depends on value of V DD, RL and CL. See Operation section. ABSOLUTE MAXIMUM RATINGS* (TA = +25°C, unless otherwise noted) Maximum Junction Temperature (T Thermal Resistance qJA *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table I. Serial-Data Word Format ADDR DATA B7 B6 B5 B4 B3 B2 B1 B0 A1 A0 D5 D4 D3 D2 D1 D0 MSB LSB MSB LSB 27 26 25 20 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5203 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE SDI CLK CS VOUT VDD D0D1D2D3D4D5A0A1 DAC REGISTER LOAD Figure 1a. Timing Diagram CLK VOUT VDD SDI (DATA IN) SDO (DATA OUT) CS Ax OR Dx Ax OR Dx A'x OR D'x tDS tDH tPD MAXtPD MIN tCH tCS1 tCLtCSS tCSH

61 LSB

A'x OR D'x Figure 1b. Detail Timing Diagram VOUT VDD RS

61 LSB ERROR BAND

Figure 1c. Reset Timing Diagram

–4– REV. 0 PIN FUNCTION DESCRIPTIONS Pin No. Name Description

1 AGND2 Analog Ground #2*

2 B2 B Terminal RDAC #2

3 A2 A Terminal RDAC #2

4 W2 Wiper RDAC #2, addr = 01

5 AGND4 Analog Ground #4*

6 B4 B Terminal RDAC #4

7 A4 A Terminal RDAC #4

8 W4 Wiper RDAC #4, addr = 11

9 DGND Digital Ground*

10 SHDN Active Low Input. Terminal A open circuit. Shutdown controls Variable Resistors #1 through #4. 11 CS Chip Select Input, Active Low. When CS returns high data in the serial input register is decoded based on the address bits and loaded into the target DAC register.

12 SDI Serial Data Input

13 SDO Serial Data Output. Open drain transistor requires pull-up resistor. 14 CLK Serial Clock Input, positive edge triggered.

15 RS Active low reset to midscale; sets RDAC

16 V DD Positive power supply, specified for opera-

tion at both +3 V and +5 V.

17 AGND3 Analog Ground #3*

18 W3 Wiper RDAC #3, addr =10

19 A3 A Terminal RDAC #3

20 B3 B Terminal RDAC #3

21 AGND1 Analog Ground #1*

22 W1 Wiper RDAC #1, addr = 00

23 A1 A Terminal RDAC #1

24 B1 B Terminal RDAC #1

*All AGNDs must be connected to DGND voltage potential. ORDERING GUIDE Model k V Temperature Range Package Descriptions Package Options AD5203AN10 10 –40 °C to +85°C 24-Lead Narrow Body Plastic DIP N-24 AD5203AR10 10 –40 °C to +85°C 24-Lead Wide Body (SOIC) SOL-24 AD5203ARU10 10 –40 °C to +85°C 24-Lead Thin Surface Mount Package (TSSOP) RU-24 AD5203AN100 100 –40 °C to +85°C 24-Lead Narrow Body Plastic DIP N-24 AD5203AR100 100 –40 °C to +85°C 24-Lead Wide Body (SOIC) SOL-24 AD5203ARU100 100 –40 °C to +85°C 24-Lead Thin Surface Mount Package (TSSOP) RU-24 PIN CONFIGURATION AD5203 SDI CS SHDN DGND AGND2 AGND4 SDO CLK RS VDD AGND3 AGND1 (Not to Scale)

Figure 26. Potentiometer Divider Nonlinearity Error Test Figure 27. Resistor Position Nonlinearity Error (Rheostat Figure 29. Power Supply Sensitivity Test Circuit (PSS, Figure 30. Inverting Programmable Gain Test Circuit

0 TO VDD

Figure 33. Incremental ON Resistance Test Circuit

VR outputs can be changed one at a time in random sequence. exact timing requirements are shown in Figure 1. their previous resistance values. Figure 34. Equivalent RDAC Circuit fied diagram of the equivalent RDAC circuit. RBA is the nominal end-to-end resistance. temperature has a 700 ppm/ °C temperature coefficient.

proportional to the input voltage applied to a given terminal. any value starting at zero volts up to 1 LSB less than +5 V. not the absolute value, therefore the drift improves to 20 ppm/°C. the serial register on each positive clock edge, see Table III. Figure 35. Block Diagram for equivalent SDO output circuit schematic. L L H H No SR effect, enables SDO pin. P L H H Shift one bit in from the SDI pin. is shifted out of the SDO pin. based on A1, A0 decode (Table III). NOTE: P = positive edge, X = don’t care, SR = shift register.

–12– REV. 0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3364–8–7/98PRINTED IN U.S.A. 24-Lead Narrow Body Plastic DIP (N-24) 11 2 13 0.280 (7.11) 0.240 (6.10) PIN 1 1.275 (32.30) 1.125 (28.60) 0.150 (3.81) MIN0.200 (5.05) 0.125 (3.18) SEATING PLANE 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 24-Lead SOIC (SOL-24) 24 13 121 0.6141 (15.60) 0.5985 (15.20) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) PIN 1 SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) 0.0098 (0.25)x 45° 24-Lead Thin Surface Mount TSSOP (RU-24) 24 13 121 0.311 (7.90) 0.303 (7.70) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) PIN 1 SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50)