AD5201 AD | Alldatasheet
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REV.B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD5200/AD5201 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 FUNCTIONAL BLOCK DIAGRAM SER REG PWR-ON PRESET A W B RDAC REGDx CS CLK SDI AD5200/AD5201 VSSVDD GND SHDN 256-Position and 33-Position Digital Potentiometers
FEATURES
AD5200—256-Position AD5201—33-Position 10k /H9024, 50k /H9024 3-Wire SPI-Compatible Serial Data Input Single Supply 2.7V to 5.5V or Dual Supply /H115502.7V for AC or Bipolar Operations Internal Power-On Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching GENERAL DESCRIPTION The AD5200 and AD5201 are programmable resistor devices, with 256 positions and 33 positions respectively, that can be digi- tally controlled through a 3-wire SPI serial interface. The terms programmable resistor, variable resistor (VR), and RDAC are commonly used interchangeably to refer to digital potentiometers. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. Both AD5200/AD5201 contain a single variable resistor in the compact µSOIC-10 package. Each device contains a fixed wiper resistance at the wiper contact that taps the programmable resistance at a point determined by a digital code. The code is loaded in the serial input register. The resistance between the wiper and either end point of the programmable resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper, or the B terminal and the wiper. The fixed A-to-B terminal resistance of 10 k Ω or 50 kΩ has a nominal temperature coefficient of 500 ppm/ °C. The VR has a VR latch that holds its programmed resistance value. The VR latch is updated from an SPI-compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Eight data bits for the AD5200 and six data bits for the AD5201 make up the data word that is clocked into the serial input register. The internal preset forces the wiper to the midscale position by loading 80 H and 10H into AD5200 and AD5201 VR latches respectively. The SHDN pin forces the resistor to an end-to-end open-circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When SHDN is returned to logic high, the previous latch setting puts the wiper in the same resistance setting prior to shutdown. The digital interface is still active dur- ing shutdown so that code changes can be made that will produce a new wiper position when the device is returned from shutdown. All parts are guaranteed to operate over the extended industrial temperature range of –40 °C to +85°C.
REV. B–2– AD5200/AD5201–SPECIFICATIONS AD5200 ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ 1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity 2 R-DNL R WB, VA = No Connect –1 ± 0.25 +1 LSB Resistor Integral Nonlinearity 2 R-INL R WB, VA = No Connect –2 ± 0.5 +2 LSB Nominal Resistor Tolerance 3 ∆RAB TA = 25°C –30 +30 % Resistance Temperature Coefficient R AB/∆TV AB = VDD, Wiper = No Connect 500 ppm/°C Wiper Resistance R W VDD = 5 V 50 100 Ω DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.) Resolution N 8 Bits Differential Nonlinearity
4 DNL –1 ± 1/4 +1 LSB
Integral Nonlinearity 4 INL –2 ± 1/2 +2 LSB Voltage Divider Temperature Coefficient ∆VW/∆T Code = 80 H 5 ppm/ °C Full-Scale Error V WFSE Code = FFH –1.5 –0.5 0 LSB Zero-Scale Error V WZSE Code = 00H 0 +0.5 +1.5 LSB RESISTOR TERMINALS Voltage Range5 VA, B, W VSS VDD V Capacitance 6 A, B C A, B f = 1 MHz, Measured to GND, Code = 80 H 45 pF Capacitance 6 WC W f = 1 MHz, Measured to GND, Code = 80 H 60 pF Shutdown Supply Current 7 IDD_SD VDD = 5.5 V 0.01 5 µA Common-Mode Leakage I CM VA = VB = VDD/2 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High V IH 2.4 V Input Logic Low V IL 0.8 V Input Logic High V IH VDD = 3 V, VSS = 0 V 2.1 V Input Logic Low V IL VDD = 3 V, VSS = 0 V 0.6 V Input Current I IL VIN = 0 V or 5 V ± 1 µA Input Capacitance 6 CIL 5p F POWER SUPPLIES Logic Supply V LOGIC 2.7 5.5 V Power Single-Supply Range V DD RANGE VSS = 0 V –0.3 5.5 V Power Dual-Supply Range V DD/SS RANGE ± 2.3 ± 2.7 V Positive Supply Current I DD VIH = +5 V or VIL = 0 V 15 40 µA Negative Supply Current I SS VSS = –5 V 15 40 µA Power Dissipation 8 PDISS VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = 0 V 0.2 mW Power Supply Sensitivity PSS ∆VDD = +5 V ± 10%, Code = Midscale –0.01 0.001 +0.01 %/% DYNAMIC CHARACTERISTICS 6, 9 Bandwidth –3 dB BW_10 kΩ RAB = 10 kΩ, Code = 80H 600 kHz BW_50 kΩ RAB = 50 kΩ, Code = 80H 100 kHz Total Harmonic Distortion THD W VA = 1 V rms, VB = 0 V, f = 1 kHz, R AB = 10 kΩ 0.003 % VW Settling Time (10 kΩ/50 kΩ)t S VA = 5 V, VB = 0 V, ± 1 LSB Error Band 2/9 µs Resistor Noise Voltage Density e N_WB RWB = 5 kΩ, RS = 0 9 nV √Hz NOTES 1Typicals represent average readings at 25 °C and VDD = 5 V, VSS = 0 V. 2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both V DD = +2.7 V, VSS = –2.7 V. 3VAB = VDD, Wiper (VW) = No connect. 4INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. 5Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 6Guaranteed by design and not subject to production test. 7Measured at the A terminal. A terminal is open-circuited in shutdown mode. 8PDISS is calculated from (I DD × VDD). CMOS logic level inputs result in minimum power dissipation. 9All dynamic characteristics use V DD = 5 V, VSS = 0 V. Specifications subject to change without notice. (VDD = 5 V /H11550 10%, or 3 V /H11550 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40 /H11543C < TA < +85/H11543C unless otherwise noted.)
REV. B –3– AD5200/AD5201 (VDD = 5 V /H11550 10%, or 3 V /H11550 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40 /H11543C < TA < +85/H11543C unless otherwise noted.)AD5201 ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ 1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity 2 R-DNL R WB, VA = No Connect –0.5 ± 0.05 +0.5 LSB Resistor Integral Nonlinearity 2 R-INL R WB, VA = No Connect –1 ± 0.1 +1 LSB Nominal Resistor Tolerance 3 ∆RAB TA = 25°C –30 +30 % Resistance Temperature Coefficient R AB/∆TV AB = VDD, Wiper = No Connect 500 ppm/°C Wiper Resistance R W VDD = 5 V 50 100 Ω DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.) Resolution4 N 6 Bits Differential Nonlinearity 5 DNL –0.5 ± 0.01 +0.5 LSB Integral Nonlinearity 5 INL –1 ± 0.02 +1 LSB Voltage Divider Temperature Coefficient ∆VW/∆T Code = 10 H 5 ppm/ °C Full-Scale Error V WFSE Code = 20H –1/2 –1/4 0 LSB Zero-Scale Error V WZSE Code = 00H 0 +1/4 +1/2 LSB RESISTOR TERMINALS Voltage Range6 VA, B, W VSS VDD V Capacitance 7 A, B C A, B f = 1 MHz, Measured to GND, Code = 10 H 45 pF Capacitance 7 WC W f = 1 MHz, Measured to GND, Code = 10 H 60 pF Shutdown Supply Current 8 IDD_SD VDD = 5.5 V 0.01 5 µA Common-Mode Leakage I CM VA = VB = VDD/2 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High V IH 2.4 V Input Logic Low V IL 0.8 V Input Logic High V IH VDD = 3 V, VSS = 0 V 2.1 V Input Logic Low V IL VDD = 3 V, VSS = 0 V 0.6 V Input Current I IL VIN = 0 V or 5 V ±1 µA Input Capacitance 7 CIL 5p F POWER SUPPLIES Logic Supply V LOGIC 2.7 5.5 V Power Single-Supply Range V DD RANGE VSS = 0 V –0.3 5.5 V Power Dual-Supply Range V DD/SS RANGE ± 2.3 ± 2.7 V Positive Supply Current I DD VIH = +5 V or VIL = 0 V 15 40 µA Negative Supply Current I SS VSS = –5 V 15 40 µA Power Dissipation 9 PDISS VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = –5 V 0.2 mW Power Supply Sensitivity PSS ∆VDD = +5 V ± 10% –0.01 0.001 +0.01 %/% DYNAMIC CHARACTERISTICS 7, 10 Bandwidth –3 dB BW_10 kΩ RAB = 10 kΩ, Code = 10H 600 kHz BW_50 kΩ RAB = 50 kΩ, Code = 10H 100 kHz Total Harmonic Distortion THD W VA = 1 V rms, VB = 0 V, f = 1 kHz, R AB = 10 kΩ 0.003 % VW Settling Time (10 kΩ/50 kΩ)t S VA = 5 V, VB = 0 V, ± 1 LSB Error Band 2/9 µs Resistor Noise Voltage Density e N_WB RWB = 5 kΩ, RS = 0 9 nV √Hz NOTES 1Typicals represent average readings at 25 °C and VDD = 5 V, VSS = 0 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both V DD = +2.7 V, VSS = –2.7 V. 3 VAB = VDD, Wiper (V W) = No connect. 4 Six bits are needed for 33 positions even though it is not a 64-position device. 5 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. 6 Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 7 Guaranteed by design and not subject to production test. 8 Measured at the A terminal. A terminal is open-circuited in shutdown mode. 9 PDISS is calculated from (I DD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use V DD = 5 V, VSS = 0 V. Specifications subject to change without notice.
REV. B AD5200/AD5201 –5– ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C, unless otherwise noted) Package Power Dissipation = (T J Max – TA)/θJA NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Max current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. Please refer to TPC 31 and TPC 32 for detail. PIN CONFIGURATION TOP VIEW (Not to Scale) AD5200/ AD5201 B VSS GND CS SDI A W VDD SHDN CLK CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5200/AD5201 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PIN FUNCTION DESCRIPTIONS Pin Name Description 1 B B Terminal. 2V SS Negative Power Supply, specified for opera- tion from 0 V to –2.7 V. 3 GND Ground. 4 CS Chip Select Input, Active Low. When CS returns high, data will be loaded into the DAC register. 5 SDI Serial Data Input. 6 CLK Serial Clock Input, positive edge triggered. 7 SHDN Active Low Input. Terminal A open circuit. Shutdown controls Variable Resistors of RDAC to temporary infinite. DD Positive Power Supply (Sum of V DD + VSS ≤ 5.5 V). 9 W Wiper Terminal. 10 A A Terminal. ORDERING GUIDE Temperature Package Package Full Branding Model RES k /H9024Range Description Option Reel Qty. Information AD5200BRM10-REEL7 256 10 –40°C/+85°C µSOIC-10 RM-10 5000 DLA AD5200BRM50-REEL7 256 50 –40°C/+85°C µSOIC-10 RM-10 5000 DLB AD5201BRM10-REEL7 33 10 –40°C/+85°C µSOIC-10 RM-10 5000 DMA AD5201BRM50-REEL7 33 50 –40°C/+85°C µSOIC-10 RM-10 5000 DMB
REV. B–6– AD5200/AD5201–Typical Performance Characteristics CODE – Decimal /H115460.20 RDNL – LSB 224 /H115460.15 /H115460.10 /H115460.05 0.00 0.05 0.10 0.15 0.20 1921601289664320 256 VDD = 2.7V, VSS = 0V VDD = 5.5V, VSS = 0V VDD = +2.7V, VSS = –2.7V TPC 1. AD5200 10 kΩ RDNL vs. Code CODE – Decimal RDNL – LSB –0.02 –0.01 0.00 0.01 0.02 0.03 242016128403 2 –0.03 VDD = 2.7V, VSS = 0V VDD = 5.5V, VSS = 0V VDD = +2.7V, VSS = –2.7V TPC 2. AD5201 10 kΩ RDNL vs. Code CODE – Decimal RINL – LSB 224 0.0 0.1 0.2 0.3 0.5 0.7 1921601289664320 256 –0.1 VDD = 2.7V, VSS = 0V VDD = 5.5V, VSS = 0V VDD = +2.7V, VSS = –2.7V 0.6 0.4 TPC 3. AD5200 10 kΩ RINL vs. Code CODE – Decimal RINL – LSB 0.00 0.02 0.04 0.06 0.08 0.12 242016128403 2 –0.02 VDD = +2.7V VSS = –2.7V VDD = 2.7V, VSS = 0V VDD = 5.5V, VSS = 0V 0.10 TPC 4. AD5201 10 kΩ RINL vs. Code CODE – Decimal DNL – LSB 224 –0.25 –0.20 –0.15 –0.10 –0.05 0.10 1921601289664320 256 –0.30 VDD = +2.7V, VSS = –2.7V VDD = 5.5V, VSS = 0V VDD = 2.7V, VSS = 0V 0.00 0.05 TPC 5. AD5200 10 kΩ DNL vs. Code CODE – Decimal DNL – LSB –0.005 0.000 0.005 0.010 0.020 242016128403 2 –0.010 VDD = +2.7V, VSS = –2.7V VDD = 5.5V, VSS = 0V VDD = 2.7V, VSS = 0V 0.015 TPC 6. AD5201 10 kΩ DNL vs. Code
REV. B AD5200/AD5201 –7– CODE – Decimal INL – LSB 224 –0.2 –0.1 0.0 0.1 0.3 1921601289664320 256 –0.3 VDD = +2.7V, VSS = –2.7V VDD = 5.5V, VSS = 0V VDD = 2.7V, VSS = 0V 0.2 –0.4 –0.5 TPC 7. AD5200 10 kΩ INL vs. Code CODE – Decimal INL – LSB 0.005 0.010 0.020 242016128403 2 0.000 VDD = +2.7V, VSS = –2.7V VDD = 5.5V, VSS = 0V VDD = 2.7V, VSS = 0V 0.015 –0.005 –0.010 TPC 8. AD5201 10 kΩ INL vs. Code VIH – V IDD/ISS – mA 0.01 0.1 0.001 1.0 IDD @ VDD/VSS = 5V/0V IDD @ VDD/VSS = 3V/0V IDD @ VDD/VSS = /H115502.5V ISS @ VDD/VSS = /H115502.5V TPC 9. Supply Current vs. Logic Input Voltage TEMPERATURE – /H11543C IDD SUPPLY CURRENT – /H9262A –40 –20 0 20 40 60 80 100 VIL = VSS VIH = VDD VDD = 5.5V VDD = 2.7V TPC 10. Supply Current vs. Temperature TEMPERATURE – /H11543C IA SHUTDOWN CURRENT – nA –40 –20 0 20 40 60 80 100 VDD = 5.5V TPC 11. Shutdown Current vs. Temperature VSUPPLY – V RON – /H9024 160 140 120 100 54321 VDD = 2.7V VDD = 5.5V SEE TEST CIRCUIT 13 TA = 25/H11543C TPC 12. Wiper ON Resistance vs. VSUPPLY
REV. B AD5200/AD5201 –8– FREQUENCY – Hz IDD/ISS – /H9262A 500 10k 450 400 350 300 250 200 150 100 100k 1M 10M CODE FFH ISS @ VDD/VSS = /H115502.5V IDD @ VDD/VSS = /H115502.5V IDD @ VDD/VSS = 5V/0V IDD @ VDD/VSS = 3V/0V TPC 13. AD5200 10 kΩ Supply Current vs. Clock Frequency FREQUENCY – Hz IDD/ISS – /H9262A 500 10k 450 400 350 300 250 200 150 100 100k 1M 10M CODE 55H ISS @ VDD/VSS = /H115502.5V IDD @ VDD/VSS = /H115502.5V IDD @ VDD/VSS = 5V/0V IDD @ VDD/VSS = 3V/0V TPC 14. AD5200 10 kΩ Supply Current vs. Clock Frequency FREQUENCY – Hz PSRR – dB 100 1k 10k 1M +PSRR @ VDD = 5V DC /H1155010% p-p AC 100k +PSRR @ VDD = 3V DC /H1155010% p-p AC –PSRR @ VDD = 3V DC /H1155010% p-p AC CODE = 80H, VA = VDD, VB = 0V TPC 15. Power Supply Rejection Ratio vs. Frequency FREQUENCY – Hz –54 GAIN – dB 1k 10k 100k 1M –48 –42 –36 –30 –24 –18 –12 80H 40H 20H 10H 08H 04H 02H 01H TPC 16. AD5200 10 kΩ Gain vs. Frequency vs. Code FREQUENCY – Hz –54 GAIN – dB 1k 10k 100k 1M –48 –42 –36 –30 –24 –18 –12 80H 40H 20H 10H 08H 04H 02H 01H TPC 17. AD5200 50 kΩ Gain vs. Frequency vs. Code FREQUENCY – Hz –54 GAIN – dB 1k 10k 100k 1M –48 –42 –36 –30 –24 –18 –12 10H TPC 18. AD5201 10 kΩ Gain vs. Frequency vs. Code
REV. B AD5200/AD5201 –9– FREQUENCY – Hz –54 GAIN – dB 1k 10k 100k 1M –48 –42 –36 –30 –24 –18 –12 10H TPC 19. AD5201 50 kΩ Gain vs. Frequency vs. Code FREQUENCY – Hz –48 GAIN – dB 1k 10k 100k 1M –42 –36 –30 –24 –18 –12 10k/H9024 VIN = 100mV rms VDD = 5V RL = 1M/H9024 50k/H9024 TPC 20. AD5200 –3 dB Bandwidth FREQUENCY – Hz –48 GAIN – dB 1k 10k 100k 1M –42 –36 –30 –24 –18 –12 10k/H9024 VIN = 100mV rms VDD = 5V RL = 1M/H9024 50k/H9024 TPC 21. AD5201 –3 dB Bandwidth FREQUENCY – Hz –48 NORMALIZED GAIN FLATNESS – 0.1dB/DIV 10 10k 100k 1M –42 –36 –30 –24 –18 –12 100 1k 50k/H9024 10k/H9024 SEE TEST CIRCUIT 10 CODE = 80H VDD = 5V TA = 25/H11543C TPC 22. Normalized Gain Flatness vs. Frequency FREQUENCY – Hz –48 NORMALIZED GAIN FLATNESS – 0.1dB/DIV 10 10k 100k 1M –42 –36 –30 –24 –18 –12 100 1k 50k/H9024 10k/H9024 SEE TEST CIRCUIT 10 CODE = 10H VDD = 5V TA = 25/H11543C TPC 23. AD5201 Normalized Gain Flatness vs. Frequency VW (20mV/DIV) CS (5V/DIV) TPC 24. One Position Step Change at Half Scale
REV. B AD5200/AD5201 –10– OUTPUT (2V/DIV) INPUT (5V/DIV) TPC 25. Large Signal Settling Time VOUT (20mV/DIV) TPC 26. Digital Feedthrough vs. Time CODE – Decimal 4000 /H11546500 POTENTIOMETER MODE TEMPCO – ppm//H11543C 3500 3000 2500 2000 1500 1000 500 32 64 96 128 160 192 224 256 TPC 27. AD5200 ∆VWB/∆T Potentiometer Mode Temperature Coefficient CODE – Decimal /H11546500 RHEOSTAT MODE TEMPCO – ppm//H11543C 3500 3000 2500 2000 1500 1000 500 32 64 96 128 160 192 224 256 TPC 28. AD5200 ∆RWB/∆T Rheostat Mode Temperature Coefficient CODE – Decimal POTENTIOMETER MODE TEMPCO – ppm//H11543C 3000 2500 2000 1500 1000 500 –500 4 8 12 16 20 24 28 32 TPC 29. AD5201 Potentiometer Mode Temperature Coefficient CODE – Decimal POTENTIOMETER MODE TEMPCO – ppm//H11543C –20 4 8 12 16 20 24 28 32 –10 TPC 30. AD5201 ∆VWB/∆T Potentiometer Mode Tempco
REV. B AD5200/AD5201 –11– CODE – Decimal 100.0 10.0 0.1 03 2 THEORETICAL IMAX – mA 1.0 64 96 128 160 192 224 256 RAB = 10k/H9024 RAB = 50k/H9024 TPC 31. AD5200 IMAX vs. Code CODE – Decimal 100.0 10.0 0.1 THEORETICAL IMAX – mA 1.0 81 2 16 20 24 28 32 RAB = 10k/H9024 RAB = 50k/H9024 TPC 32. AD5201 IMAX vs. Code OPERATION The AD5200/AD5201 provide 255 and 33 positions digitally- controlled variable resistor (VR) devices. Changing the programmed VR settings is accomplished by clocking in an 8-bit serial data word for AD5200, and a 6-bit serial data word for AD5201, into the SDI (Serial Data Input) pins. Table I provides the serial register data word format. The AD5200/AD5201 are preset to a midscale internally during power-on condition. In addition, the AD5200/AD5201 contain power shutdown SHDN pins that place the RDAC in a zero power consump- tion state where the immediate switches next to Terminals A and B are open-circuited. Meanwhile, the wiper W is connected to B terminal, resulting in only leakage current consumption in the VR structure. During shutdown, the VR latch contents are maintained when the RDAC is inactive. When the part is returned from shutdown, the stored VR setting will be applied to the RDAC. Table I. AD5200 Serial-Data Word Format 7B6 B5 B4 B3 B2 B1 B0 B 7D6 D5 D4 D3 D2 D1 D0 D BSMB SL 27 20 Table II. AD5201 Serial-Data Word Format 5B * 4B3 B2 B1 B0 B 5D * 4D3 D2 D1 D0 D BSMB SL 25 20 *Six data bits are needed for 33 positions. PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between Terminals A and B are available with values of 10 k Ω and 50 kΩ. The final two digits of the part number determine the nominal resistance value, e.g., 10 kΩ = 10 and 50 kΩ = 50. The nominal resistance (RAB) of AD5200 has 256 contact points accessed by the wiper terminal. The 8-bit data word in the RDAC latch of AD5200 is decoded to select one of the 256 possible settings. In both parts, the wiper’s first connection starts at the B terminal for data 00 H. This B-terminal connection has a wiper contact resistance of 50 Ω as long as valid VDD/VSS is applied, regardless of the nominal resistance. For a 10 kΩ part, the second connection of AD5200 is the first tap point with 89Ω [RWB = RAB/255 + RW = 39 Ω + 50 Ω] for data 01H. The third connection is the next tap point representing 78 + 50 = 128Ω for data 02H. Due to its unique internal structure, AD5201 has 5-bit + 1 resolution, but needs a 6-bit data word to achieve the full 33 steps resolution. The 6-bit data word in the RDAC latch is decoded to select one of the 33 possible settings. Data 34 to 63 will automatically be equal to Position 33. The wiper 00 H connection of AD5201 gives 50 Ω. Similarly, for a 10 kΩ part, the first tap point of AD5201 yields 363 Ω for data 01 H, 675 Ω for data 02H. For both AD5200 and AD5201, each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached. Figures 2a and 2b show the simplified diagrams of the equivalent RDAC circuits.
1 LSB = V+/2N
Figure 6. Potentiometer Divider Nonlinearity Error Test Figure 7. Resistor Position Nonlinearity Error Figure 8. Wiper Resistance Test Circuit Figure 9. Power Supply Sensitivity Test Circuit Figure 10. Inverting Gain Test Circuit Figure 11. Noninverting Gain Test Circuit Figure 12. Gain vs. Frequency Test Circuit Figure 13. Incremental ON Resistance Test Circuit Figure 14. Common-Mode Leakage Current Test Circuit
REV. B AD5200/AD5201 –15– DIGITAL POTENTIOMETER SELECTION GUIDE Number Resolution Power of VRs Terminal Interface Nominal (Number Supply Part per Voltage Data Resistance Of Wiper Current Number Package Range Control (k /H9024) Positions) (I DD) Packages Comments AD5201 1 ±3 V, +5.5 V 3-Wire 10, 50 33 60 µA µSOIC-10 Full AC Specs, Dual Supply, Pwr-On-Reset, Low Cost AD5220 1 5.5 V Up/Down 10, 50, 100 128 40 µA PDIP, SO-8, µSOIC-8 No Rollover, Pwr-On-Reset AD7376 1 ±15 V, +28 V 3-Wire 10, 50, 100, 1000 128 100 µA PDIP-14, SOL-16, Single 28 V or Dual ±15 V TSSOP-14 Supply Operation AD5200 1 ±3 V, +5.5 V 3-Wire 10, 50 256 60 µA µSOIC-10 Full AC Specs, Dual Supply, Pwr-On-Reset AD8400 1 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA SO-8 Full AC specs AD5241* 1 ±3 V, +5.5 V 2-Wire 10, 100, 1000 256 5 µA SO-14, TSSOP-14 I 2C-Compatible, TC < 50 ppm/°C AD5231* 1 ±3 V, +5.5 V 3-Wire 10, 50, 100 1024 10 µA TSSOP-16 Nonvolatile Memory, Direct Program, I/D, ±6 dB Settability AD5222 2 ±3 V, +5.5 V Up/Down 10, 50, 100, 1000 128 80 µA SO-14, TSSOP-14 No Rollover, Stereo, Pwr-On- Reset, TC < 50 ppm/ °C AD8402 2 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA PDIP, SO-14, Full AC Specs, nA TSSOP-14 Shutdown Current AD5232* 2 ±3 V, +5.5 V 3-Wire 10, 50, 100 256 10 µA TSSOP-16 Nonvolatile Memory, Direct Program, I/D, ±6 dB Settability AD5242* 2 ±3 V, +5.5 V 2-Wire 10, 100, 1000 256 5 µA SO-16, TSSOP-16 I 2C-Compatible, TC < 50 ppm/°C AD5262* 2 ±5 V, +12 V 3-Wire 10, 50, 100 256 60 µA TSSOP-16 Medium Voltage Operation, TC < 50 ppm/°C AD5203 4 5.5 V 3-Wire 10, 100 64 5 µA PDIP, SOL-24, Full AC specs, nA TSSOP-24 Shutdown Current AD5233* 4 ±3 V, +5.5 V 3-Wire 10, 50, 100 64 10 µA TSSOP-16 Nonvolatile Memory, Direct Program, I/D, ±6 dB Settability AD5204 4 ±3 V, +5.5 V 3-Wire 10, 50, 100 256 5 µA PDIP, SOL-24, Full AC Specs, Dual Supply, TSSOP-24 Pwr-On-Reset AD8403 4 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA PDIP, SOL-24, Full AC Specs, nA TSSOP-24 Shutdown Current AD5206 6 ±3 V, +5.5 V 3-Wire 10, 50, 100 256 5 µA PDIP, SOL-24, Full AC Specs, Dual Supply, TSSOP-24 Pwr-On-Reset *Future product, consult factory for latest status.
–16– C02188–0–8/01(B) PRINTED IN U.S.A. REV. B 10-Lead /H9262SOIC (RM-10) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 0.022 (0.56) 0.021 (0.53) 6/H11543 0/H11543 10 6 0.0197 (0.50) BSC 0.124 (3.15) 0.112 (2.84) 0.124 (3.15) 0.112 (2.84) 0.199 (5.05) 0.187 (4.75) PIN 1 0.122 (3.10) 0.110 (2.79) 0.006 (0.15) 0.002 (0.05) 0.016 (0.41) 0.006 (0.15) 0.038 (0.97) 0.030 (0.76) SEATING PLANE 0.043 (1.09) 0.037 (0.94) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). AD5200/AD5201
Revision History
Data Sheet changed from REV. A to REV. B. 02/01—Data Sheet changed from REV. O to REV. A.