AD5122BRUZ10

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Dual Channel, 128-/256-Position, SPI, Nonvolatile Digital Potentiometer Data Sheet AD5122/AD5142 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

10 kΩ and 100 kΩ resistance options Resistor tolerance: 8% maximum Wiper current: ±6 mA Low temperature coefficient: 35 ppm/°C Wide bandwidth: 3 MHz Fast start-up time < 75 µs Linear gain setting mode Single- and dual-supply operation Independent logic supply: 1.8 V to 5.5 V Wide operating temperature: −40°C to +125°C 3 mm × 3 mm package option 4 kV ESD protection

APPLICATIONS

Portable electronics level adjustment LCD panel brightness and contrast controls Programmable filters, delays, and time constants Programmable power supplies FUNCTIONAL BLOCK DIAGRAM VDD INDEP VSSGND VLOGIC SERIAL INTERFACE POWER-ON RESET RDAC1 INPUT REGISTER 1 RDAC2 INPUT REGISTER 2 EEPROM MEMORY AD5122/ AD5142 SYNC SCLK SDI SDO RESET 10880-001 Figure 1. GENERAL DESCRIPTION The AD5122/AD5142 potentiometers provides a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins. The low resistor tolerance and low nominal temperature coefficient simplify open-loop applications as well as applications requiring tolerance matching. The linear gain setting mode allows independent programming of the resistance between the digital potentiometer terminals, through the R AW and RWB string resistors, allowing very accurate resistor matching. The high bandwidth and low total harmonic distortion (THD) ensure optimal performance for ac signals, making these devices suitable for filter design. The low wiper resistance of only 40 Ω at the ends of the resistor array allows for pin-to-pin connection. The wiper values can be set through an SPI-compatible digital interface that is also used to read back the wiper register and EEPROM contents. The AD5122/AD5142 is available in a compact, 16-lead, 3 mm × 3 mm LFCSP and a 16-lead TSSOP . The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Table 1. Family Models 1 Two potentiometers and two rheostats.

Rev. 0 | Page 2 of 32 TABLE OF CONTENTS

REVISION HISTORY

10/12—Revision 0: Initial Version

Rev. 0 | Page 3 of 32 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5122 otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution N 7 Bits Resistor Integral Nonlinearity2 R-INL RAB = 10 kΩ VDD ≥ 2.7 V −1 ±0.1 +1 LSB VDD < 2.7 V −2.5 ±1 +2.5 LSB RAB = 100 kΩ VDD < 2.7 V −1 ±0.25 +1 LSB Resistor Differential Nonlinearity2 R-DNL −0.5 ±0.1 +0.5 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 ±1 +8 % Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C Wiper Resistance3 RW Code = zero scale RAB = 10 kΩ 55 125 Ω RAB = 100 kΩ 130 400 Ω Bottom Scale or Top Scale RBS or RTS RAB = 10 kΩ 40 80 Ω RAB = 100 kΩ 60 230 Ω Nominal Resistance Match RAB1/RAB2 Code = 0xFF −1 ±0.2 +1 % DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity4 INL RAB = 10 kΩ −0.5 ±0.1 +0.5 LSB RAB = 100 kΩ −0.25 ±0.1 +0.25 LSB Differential Nonlinearity4 DNL −0.25 ±0.1 +0.25 LSB Full-Scale Error VWFSE RAB = 10 kΩ −1.5 −0.1 LSB RAB = 100 kΩ −0.5 ±0.1 +0.5 LSB Zero-Scale Error VWZSE RAB = 10 kΩ 1 1.5 LSB RAB = 100 kΩ 0.25 0.5 LSB Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±5 ppm/°C

Rev. 0 | Page 4 of 32 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit RESISTOR TERMINALS Maximum Continuous Current IA, IB, and IW RAB = 10 kΩ −6 +6 mA RAB = 100 kΩ −1.5 +1.5 mA Terminal Voltage Range5 VSS VDD V Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ 25 pF RAB = 100 kΩ 12 pF Capacitance W3 CW f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ 12 pF RAB = 100 kΩ 5 pF Common-Mode Leakage Current3 VA = VW = VB −500 ±15 +500 nA DIGITAL INPUTS Input Logic3 High VINH VLOGIC = 1.8 V to 2.3 V 0.8 × VLOGIC V VLOGIC = 2.3 V to 5.5 V 0.7 × VLOGIC V Low VINL 0.2 × VLOGIC V Input Hysteresis3 VHYST 0.1 × VLOGIC V Input Current3 IIN ±1 µA Input Capacitance3 CIN 5 pF DIGITAL OUTPUTS Output High Voltage3 VOH RPULL-UP = 2.2 kΩ to VLOGIC VLOGIC V Output Low Voltage3 VOL ISINK = 3 mA 0.4 V ISINK = 6 mA, VLOGIC > 2.3 V 0.6 V Three-State Leakage Current −1 +1 µA Three-State Output Capacitance 2 pF POWER SUPPLIES Single-Supply Power Range VSS = GND 2.3 5.5 V Dual-Supply Power Range ±2.25 ±2.75 V Logic Supply Range Single supply, VSS = GND 1.8 VDD V Dual supply, VSS < GND 2.25 VDD V Positive Supply Current IDD VIH = VLOGIC or VIL = GND VDD = 5.5 V 0.7 5.5 µA VDD = 2.3 V 400 nA Negative Supply Current ISS VIH = VLOGIC or VIL = GND −5.5 −0.7 µA EEPROM Store Current3, 6 IDD_EEPROM_STORE VIH = VLOGIC or VIL = GND 2 mA EEPROM Read Current3, 7 IDD_EEPROM_READ VIH = VLOGIC or VIL = GND 320 µA Logic Supply Current ILOGIC VIH = VLOGIC or VIL = GND 1 120 nA Power Dissipation8 PDISS VIH = VLOGIC or VIL = GND 3.5 µW Power Supply Rejection Ratio PSRR ∆VDD/∆VSS = VDD ± 10%, code = full scale −66 −60 dB

Rev. 0 | Page 5 of 32 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DYNAMIC CHARACTERISTICS9 Bandwidth BW −3 dB RAB = 10 kΩ 3 MHz RAB = 100 kΩ 0.43 MHz Total Harmonic Distortion THD VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 kΩ −80 dB RAB = 100 kΩ −90 dB Resistor Noise Density eN_WB Code = half scale, TA = 25°C, f = 10 kHz RAB = 10 kΩ 7 nV/√Hz RAB = 100 kΩ 20 nV/√Hz VW Settling Time tS VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.5 LSB error band RAB = 10 kΩ 2 µs RAB = 100 kΩ 12 µs Crosstalk (CW1/CW2) CT RAB = 10 kΩ 10 nV-sec RAB = 100 kΩ 25 nV-sec Analog Crosstalk CTA −90 dB Endurance10 TA = 25°C 1 Mcycles 100 kcycles Data Retention11 50 Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory.

Rev. 0 | Page 6 of 32 ELECTRICAL CHARACTERISTICS—AD5142 otherwise noted. Table 3. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution N 8 Bits Resistor Integral Nonlinearity2 R-INL RAB = 10 kΩ VDD ≥ 2.7 V −2 ±0.2 +2 LSB VDD < 2.7 V −5 ±1.5 +5 LSB RAB = 100 kΩ VDD ≥ 2.7 V −1 ±0.1 +1 LSB VDD < 2.7 V −2 ±0.5 +2 LSB Resistor Differential Nonlinearity2 R-DNL −0.5 ±0.2 +0.5 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 ±1 +8 % Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C Wiper Resistance3 RW Code = zero scale RAB = 10 kΩ 55 125 Ω RAB = 100 kΩ 130 400 Ω Bottom Scale or Top Scale RBS or RTS RAB = 10 kΩ 40 80 Ω RAB = 100 kΩ 60 230 Ω Nominal Resistance Match RAB1/RAB2 Code = 0xFF −1 ±0.2 +1 % DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity4 INL RAB = 10 kΩ −1 ±0.2 +1 LSB RAB = 100 kΩ −0.5 ±0.1 +0.5 LSB Differential Nonlinearity4 DNL −0.5 ±0.2 +0.5 LSB Full-Scale Error VWFSE RAB = 10 kΩ −2.5 −0.1 LSB RAB = 100 kΩ −1 ±0.2 +1 LSB Zero-Scale Error VWZSE RAB = 10 kΩ 1.2 3 LSB RAB = 100 kΩ 0.5 1 LSB Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±5 ppm/°C

Rev. 0 | Page 7 of 32 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit RESISTOR TERMINALS Maximum Continuous Current IA, IB, and IW RAB = 10 kΩ −6 +6 mA RAB = 100 kΩ −1.5 +1.5 mA Terminal Voltage Range5 VSS VDD V Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ 25 pF RAB = 100 kΩ 12 pF Capacitance W3 CW f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ 12 pF RAB = 100 kΩ 5 pF Common-Mode Leakage Current3 VA = VW = VB −500 ±15 +500 nA DIGITAL INPUTS Input Logic3 High VINH VLOGIC = 1.8 V to 2.3 V 0.8 × VLOGIC V VLOGIC = 2.3 V to 5.5 V 0.7 × VLOGIC V Low VINL 0.2 × VLOGIC V Input Hysteresis3 VHYST 0.1 × VLOGIC V Input Current3 IIN ±1 µA Input Capacitance3 CIN 5 pF DIGITAL OUTPUTS Output High Voltage3 VOH RPULL-UP = 2.2 kΩ to VLOGIC VLOGIC V Output Low Voltage3 VOL ISINK = 3 mA 0.4 V ISINK = 6 mA, VLOGIC > 2.3 V 0.6 V Three-State Leakage Current −1 +1 µA Three-State Output Capacitance 2 pF POWER SUPPLIES Single-Supply Power Range VSS = GND 2.3 5.5 V Dual-Supply Power Range ±2.25 ±2.75 V Logic Supply Range Single supply, VSS = GND 1.8 VDD V Dual supply, VSS < GND 2.25 VDD V Positive Supply Current IDD VIH = VLOGIC or VIL = GND VDD = 5.5 V 0.7 5.5 µA VDD = 2.3 V 400 nA Negative Supply Current ISS VIH = VLOGIC or VIL = GND −5.5 −0.7 µA EEPROM Store Current3, 6 IDD_EEPROM_STORE VIH = VLOGIC or VIL = GND 2 mA EEPROM Read Current3, 7 IDD_EEPROM_READ VIH = VLOGIC or VIL = GND 320 µA Logic Supply Current ILOGIC VIH = VLOGIC or VIL = GND 1 120 nA Power Dissipation8 PDISS VIH = VLOGIC or VIL = GND 3.5 µW Power Supply Rejection Ratio PSRR ∆VDD/∆VSS = VDD ± 10%, code = full scale −66 −60 dB

Rev. 0 | Page 8 of 32 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DYNAMIC CHARACTERISTICS9 Bandwidth BW −3 dB RAB = 10 kΩ 3 MHz RAB = 100 kΩ 0.43 MHz Total Harmonic Distortion THD VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 kΩ −80 dB RAB = 100 kΩ −90 dB Resistor Noise Density eN_WB Code = half scale, TA = 25°C, f = 10 kHz RAB = 10 kΩ 7 nV/√Hz RAB = 100 kΩ 20 nV/√Hz VW Settling Time tS VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.5 LSB error band RAB = 10 kΩ 2 µs RAB = 100 kΩ 12 µs Crosstalk (CW1/CW2) CT RAB = 10 kΩ 10 nV-sec RAB = 100 kΩ 25 nV-sec Analog Crosstalk CTA −90 dB Endurance10 TA = 25°C 1 Mcycles 100 kcycles Data Retention11 50 Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory.

VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. SPI Interface 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Refer to tEEPROM_PROGRAM and tEEPROM_READBACK for memory commands operations (see Table 5). 3 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF. Table 5. Control Pins 1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles. 2 Maximum time after VDD − VSS is equal to 2.3 V.

TA = 25°C, unless otherwise noted.

1 Maximum terminal current is bounded by the maximum current handling of

3 Includes programming of EEPROM memory. 4 Human body model (HBM) classification. dependent on the test board and test environment. Table 7. Thermal Resistance 1 JEDEC 2S2P test board, still air (0 m/sec airflow).

11 SCLK

12 SDI

10 VLOGIC

9 VDD

Figure 6. 16-Lead LFCSP Pin Configuration Table 8. 16-Lead LFCSP Pin Function Descriptions 1 GND Ground Pin, Logic Ground Reference. 2 A1 Terminal A of RDAC1. VSS ≤ VA ≤ VDD. 3 W1 Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD. 4 B1 Terminal B of RDAC1. VSS ≤ VB ≤ VDD. 5 VSS Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. 6 A2 Terminal A of RDAC2. VSS ≤ VA ≤ VDD. 7 W2 Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD. 8 B2 Terminal B of RDAC2. VSS ≤ VB ≤ VDD. 9 VDD Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. 10 VLOGIC Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. 11 SCLK Serial Clock Line. Data is clocked in at the logic low transition. 13 SDO Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor. 14 SYNC Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register. memory location. If INDEP is enabled, it cannot be disabled by software. not used, tie RESET to VLOGIC. EPAD Internally Connect the Exposed Pad to VSS.

Figure 7. 16-Lead TSSOP, SPI Interface Pin Configuration Table 9. 16-Lead TSSOP, SPI Interface Pin Function Descriptions memory location. If INDEP is enabled, it cannot be disabled by software. not used, tie RESET to VLOGIC. 3 GND Ground Pin, Logic Ground Reference. 4 A1 Terminal A of RDAC1. VSS ≤ VA ≤ VDD. 5 W1 Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD. 6 B1 Terminal B of RDAC1. VSS ≤ VB ≤ VDD. 7 VSS Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. 8 A2 Terminal A of RDAC2. VSS ≤ VA ≤ VDD. 9 W2 Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD. 10 B2 Terminal B of RDAC2. VSS ≤ VB ≤ VDD. 11 VDD Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. 12 VLOGIC Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. 13 SCLK Serial Clock Line. Data is clocked in at the logic low transition. 15 SDO Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor. 16 SYNC Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register.

Rev. 0 | Page 20 of 32 THEORY OF OPERATION The AD5122/AD5142 digital programmable potentiometers are designed to operate as true variable resistors for analog signals within the terminal voltage range of VSS < VTERM < VDD. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register that allows unlimited changes of resistance settings. A secondary register (the input register) can be used to preload the RDAC register data. The RDAC register can be programmed with any position setting using the SPI interface (depending on the model). When a desirable wiper position is found, this value can be stored in the EEPROM memory. Thereafter, the wiper position is always restored to that position for subsequent power-ups. The storing of EEPROM data takes approximately 15 ms; during this time, the device is locked and does not acknowledge any new command, preventing any changes from taking place. RDAC REGISTER AND EEPROM The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with 0x80 (AD5142, 256 taps), the wiper is connected to half scale of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. It is possible to both write to and read from the RDAC register using the digital interface (see Table 10). The contents of the RDAC register can be stored to the EEPROM using Command 9 (see Table 16). Thereafter, the RDAC register always sets at that position for any future on-off-on power supply sequence. It is possible to read back data saved into the EEPROM with Command 3 (see Table 10). Alternatively, the EEPROM can be written to independently using Command 11 (see Table 16). INPUT SHIFT REGISTER For the AD5122/AD5142, the input shift register is 16 bits wide, as shown in Figure 2. The 16-bit word consists of four control bits, followed by four address bits and by eight data bits. If the AD5122 RDAC or EEPROM registers are read from or written to, the lowest data bit (Bit 0) is ignored. Data is loaded MSB first (Bit 15). The four control bits determine the function of the software command as listed in Table 10 and Table 16. SPI SERIAL DATA INTERFACE The AD5122/AD5142 contain a 4-wire, SPI-compatible digital interface (SDI, SYNC, SDO, and SCLK). The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the SDI pin. Data is loaded in at the SCLK falling edge transition, as shown in Figure 3 and Figure 4. When SYNC returns high, the serial data-word is decoded according to the instructions in Table 16. To minimize power consumption in the digital input buffers when the part is enabled, operate all serial interface pins close to the VLOGIC supply rails. SYNC Interruption In a standalone write sequence for the AD5122/AD5142, the SYNC line is kept low for 16 falling edges of SCLK, and the instruction is decoded when SYNC is pulled high. However, if the SYNC line is kept low for less than 16 falling edges of SCLK, the input shift register content is ignored, and the write sequence is considered invalid. SDO Pin The serial data output pin (SDO) serves two purposes: to read back the contents of the control, EEPROM, RDAC, and input registers using Command 3 (see Table 10 and Table 16), and to connect the AD5122/AD5142 to daisy-chain mode. The SDO pin contains an internal open-drain output that needs an external pull-up resistor. The SDO pin is enabled when SYNC is pulled low, and the data is clocked out of SDO on the rising edge of SCLK, as shown in Figure 3 and Figure 4.

Table 10. Reduced Commands Operation Truth Table 0 0 0 0 0 X X X X X X X X X X X X NOP: do nothing.

0 Normal mode

1 Shutdown mode

Table 11. Reduced Address Bits Table

1 X1 X1 X1 All channels Not applicable

for these universal adjustment devices (see Table 16 and Table 18).

• Input register
• Linear gain setting mode
• Low wiper resistance feature
• Lineal increment and decrement instructions
• ±6 dB increment and decrement instructions
• Reset
• Shutdown mode Input Register The AD5122/AD5142 include one input register per RDAC register. These registers allow preloading of the value for the associated RDAC register. These registers can be written to using Command 2 and read back from using Command 3 (see Table 16). This feature allows a synchronous update of one or all the RDAC registers at the same time. The transfer from the input register to the RDAC register is done synchronously by Command 8 (see Table 16). If new data is loaded into an RDAC register, this RDAC register automatically overwrites the associated input register. Linear Gain Setting Mode The patented architecture of the AD5122/AD5142 allows the independent control of each string resistor, RAW, and RWB. To enable this feature, use Command 16 (see Table 16) to set Bit D2 of the control register (see Table 18). This mode of operation can control the potentiometer as two independent rheostats connected at a single point, W terminal, as opposed to potentiometer mode where each resistor is complementary, RAW = RAB − RWB. This feature enables a second input and an RDAC register per channel, as shown in Table 17; however, the actual RDAC contents remain unchanged. The same operations are valid for potentiometer mode and linear gain setting mode. If the INDEP pin is pulled high, the device powers up in linear gain setting mode and loads the values stored in the associated memory locations for each channel (see Table 17). The INDEP pin and D2 bit are connected internally to a logic OR gate, if any or both are 1, the parts cannot operate in potentiometer mode. Low Wiper Resistance Feature The AD5122/AD5142 include two commands to reduce the wiper resistance between the terminals when the devices achieve full scale or zero scale. These extra positions are called bottom scale, BS, and top scale, TS. The resistance between Terminal A and Terminal W at top scale is specified as RTS. Similarly, the bottom scale resistance between Terminal B and Terminal W is specified as RBS. The contents of the RDAC registers are unchanged by entering in these positions. There are three ways to exit from top scale and bottom scale: by using Command 12 or Command 13 (see Table 16); by loading new data in an RDAC register, which includes increment/decrement operations; or by entering shutdown mode, Command 15 (see Table 16). Table 12 and Table 13 show the truth tables for the top scale position and the bottom scale position, respectively, when the potentiometer or linear gain setting mode is enabled.

Table 12. Top Scale Truth Table Table 13. Bottom Scale Truth Table all wiper positions are changed at the same time. can be executed in a single channel or multiple channels.

and the −6 dB decrement is activated by Command 7 (see Table 16). full-scale position (see Table 14). large adjustments than to small adjustments. Table 14. Detailed Left Shift and Right Shift Functions for with the contents of the EEPROM and takes approximately 30 µs. Table 15. Truth Table for Shutdown Mode

0 N/A1 Open Open RBS

1 Open N/A1 N/A1 N/A1

EEPROM and RDAC registers independently. the EEPROM into the RDAC register. the pin is pulled low, the part powers up in potentiometer mode. potentiometer mode (see Table 18).

Table 16. Advance Command Operation Truth Table

Table 17. Address Bits

1 X1 X1 X1 All channels All channels All channels All channels Not applicable

Table 18. Control Register Bit Descriptions

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

COMPLIANT TOJEDEC STANDARDS MO-220-WEED-6. Figure 46. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP]

Rev. 0 | Page 30 of 32 ORDERING GUIDE Model1, 2 RAB (kΩ) Resolution Interface Temperature Range Package Description Package Option Branding AD5122BCPZ10-RL7 10 128 SPI −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DH8 AD5122BCPZ100-RL7 100 128 SPI −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DH9 AD5122BRUZ10 10 128 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5122BRUZ100 100 128 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5122BRUZ10-RL7 10 128 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5122BRUZ100-RL7 100 128 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5142BCPZ10-RL7 10 256 SPI −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DH5 AD5142BCPZ100-RL7 100 256 SPI −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DH6 AD5142BRUZ10 10 256 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5142BRUZ100 100 256 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5142BRUZ10-RL7 10 256 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5142BRUZ100-RL7 100 256 SPI −40°C to +125°C 16-Lead TSSOP RU-16 EVAL-AD5142DBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all of the available resistor value options.

Rev. 0 | Page 31 of 32 NOTES

Rev. 0 | Page 32 of 32 NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective own ers. D10880-0-10/12(0)