AD5122A_V01 AD | Alldatasheet
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Dual Channel, 128-/256-Position, I2C, Nonvolatile Digital Potentiometer Rev. D DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►10 kΩ and 100 kΩ resistance options ►Resistor tolerance: 8% maximum ►Wiper current: ±6 mA ►Low temperature coefficient: 35 ppm/°C ►Wide bandwidth: 3 MHz ►Fast start-up time < 75 µs ►Linear gain setting mode ►Single- and dual-supply operation ►Independent logic supply: 1.8 V to 5.5 V ►Wide operating temperature: −40°C to +125°C ►3 mm × 3 mm package option ►Qualified for automotive applications
APPLICATIONS
►Portable electronics level adjustment ►LCD panel brightness and contrast controls ►Programmable filters, delays, and time constants ►Programmable power supplies FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The AD5122A/AD5142A potentiometers provide a nonvolatile solu- tion for 128-/256-position adjustment applications, offering guaran- teed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins. The low resistor tolerance and low nominal temperature coefficient simplify open-loop applications as well as applications requiring tolerance matching. The linear gain setting mode allows independent programming of the resistance between the digital potentiometer terminals, through RAW and RWB the string resistors, allowing very accurate resistor matching. The high bandwidth and low total harmonic distortion (THD) ensure optimal performance for ac signals, making it suitable for filter design. The low wiper resistance of only 40 Ω at the ends of the resistor array allows for pin-to-pin connection. The wiper values can be set through an I2C-compatible digital interface that is also used to read back the wiper register and EEPROM contents. The AD5122A/AD5142A are available in a compact, 16-lead, 3 mm × 3 mm LFCSP and a 16-lead TSSOP. The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Table 1. Family Models 1 Two potentiometers and two rheostats.
Data Sheet AD5122A/AD5142A TABLE OF CONTENTS analog.com Rev. D | 2 of 29 RAB (KΩ), Resolution, and Interface Options... 28
REVISION HISTORY
8/2024—Rev. C to Rev. D 5/2022—Rev. B to Rev. C Changes to Nominal Resistance Match Parameter, Single-Supply Power Range Parameter, Dual- Changes to Nominal Resistance Match Parameter, Single-Supply Power Range Parameter, Dual-
Data Sheet AD5122A/AD5142A SPECIFICATIONS analog.com Rev. D | 3 of 29 ELECTRICAL CHARACTERISTICS—AD5122A otherwise noted. Table 2. Parameter Symbol Test Conditions/CommentsMin Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution N 7 Bits Resistor Integral Nonlinearity2 R-INL RAB = 10 kΩ VDD ≥ 2.7 V −1 ±0.1 +1 LSB VDD < 2.7 V −2.5 ±1 +2.5 LSB RAB = 100 kΩ VDD < 2.7 V −1 ±0.25 +1 LSB Resistor Differential Nonlinearity2 R-DNL −0.5 ±0.1 +0.5 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 ±1 +8 % Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C Wiper Resistance3 RW Code = zero scale RAB = 10 kΩ 55 125 Ω RAB = 100 kΩ 130 400 Ω Bottom Scale or Top Scale RBS or RTS RAB = 10 kΩ 40 80 Ω RAB = 100 kΩ 60 230 Ω Nominal Resistance Match RAB1/RAB2 Code = full scale −1 ±0.2 +1 % DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity4 INL RAB = 10 kΩ −0.5 ±0.1 +0.5 LSB RAB = 100 kΩ −0.25 ±0.1 +0.25 LSB Differential Nonlinearity4 DNL −0.25 ±0.1 +0.25 LSB Full-Scale Error VWFSE RAB = 10 kΩ −1.5 −0.1 LSB RAB = 100 kΩ −0.5 ±0.1 +0.5 LSB Zero-Scale Error VWZSE RAB = 10 kΩ 1 1.5 LSB RAB = 100 kΩ 0.25 0.5 LSB Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±5 ppm/°C RESISTOR TERMINALS Maximum Continuous Current IA, IB, and IW RAB = 10 kΩ −6 +6 mA RAB = 100 kΩ −1.5 +1.5 mA Terminal Voltage Range5 VSS VDD V Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ 25 pF RAB = 100 kΩ 12 pF Capacitance W3 CW f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ 12 pF
Table 2. (Continued)
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. ±1 LSB maximum are guaranteed monotonic operating conditions. referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. with junction temperature in the Flash/EE memory. 12 50 years apply to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years.
Table 3. (Continued)
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. ±1 LSB maximum are guaranteed monotonic operating conditions. referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. with junction temperature in the Flash/EE memory. 12 50 years apply to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years.
Data Sheet AD5122A/AD5142A SPECIFICATIONS analog.com Rev. D | 8 of 29 INTERFACE TIMING SPECIFICATIONS VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter1 Test Conditions/CommentsMin Typ Max Unit Description fSCL2 Standard mode 100 kHz Serial clock frequency Fast mode 400 kHz t1 Standard mode 4.0 µs SCL high time, tHIGH Fast mode 0.6 µs t2 Standard mode 4.7 µs SCL low time, tLOW Fast mode 1.3 µs t3 Standard mode 250 ns Data setup time, tSU; DAT Fast mode 100 ns t4 Standard mode 0 3.45 µs Data hold time, tHD; DAT Fast mode 0 0.9 µs t5 Standard mode 4.7 µs Setup time for a repeated start condition, tSU; STA Fast mode 0.6 µs t6 Standard mode 4 µs Hold time (repeated) for a start condition, tHD; STA Fast mode 0.6 µs t7 Standard mode 4.7 µs Bus free time between a stop and a start condition, tBUF Fast mode 1.3 µs t8 Standard mode 4 µs Setup time for a stop condition, tSU; STO Fast mode 0.6 µs t9 Standard mode 1000 ns Rise time of SDA signal, tRDA Fast mode 20 + 0.1 CL 300 ns t10 Standard mode 300 ns Fall time of SDA signal, tFDA Fast mode 20 + 0.1 CL 300 ns t11 Standard mode 1000 ns Rise time of SCL signal, tRCL Fast mode 20 + 0.1 CL 300 ns t11A Standard mode 1000 ns Rise time of SCL signal after a repeated start condition and after an acknowledge bit, tRCL1 (not shown in Figure 3) Fast mode 20 + 0.1 CL 300 ns t12 Standard mode 300 ns Fall time of SCL signal, tFCL Fast mode 20 + 0.1 CL 300 ns tSP3 Fast mode 0 50 ns Pulse width of suppressed spike (not shown in Figure 3) tRESET 0.1 10 µs RESET low time (not shown in Figure 3) tEEPROM_PROGRAM4 15 50 ms Memory program time (not shown in Figure 3) tEEPROM_READBACK 7 30 µs Memory readback time (not shown in Figure 3) tPOWER_UP5 75 µs Power-on EEPROM restore time (not shown in Figure 3) tRESET 30 µs Reset EEPROM restore time (not shown in Figure 3) 1 Maximum bus capacitance is limited to 400 pF. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode. 4 The EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles. 5 Maximum time after VDD − VSS is equal to 2.3 V.
TA = 25°C, unless otherwise noted.
1 Maximum terminal current is bounded by the maximum current handling of the
voltage across any two of the A, B, and W terminals at a given resistance. 3 Includes programming of EEPROM memory. ing conditions for extended periods may affect product reliability. JEDEC natural convection environment. center line, measured in a JEDEC θJB environment. Table 6. Thermal Resistance
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD-51. sitive devices in and ESD-protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. model (CDM) per ANSI/ESDA/JEDEC JS-002. Table 7. AD5122A/AD5142A, 16-Lead TSSOP and 16-Lead LFCSP Table 8. AD5122AW/AD5142AW, 16-Lead LFCSP damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
register) can be used to preload the RDAC register data. there is no restriction on the number of changes allowed. the digital interface (see Table 10). with Command 3 (see Table 10). followed by four address bits and by eight data bits. written to, the lowest data bit (Bit 0) is ignored. Table 10. Reduced Commands Operation Truth Table
0 Normal mode
1 Shutdown mode
Table 11. Reduced Address Bits Table
1 X1 X1 X1 All channels Not applicable
diagram of a typical write sequence. addressing and general call addressing.
- The controller initiates a data transfer by establishing a start
R/W bit is set low, the controller writes to the target device.
- Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit). period of SCL and remain stable during the high period of SCL.
- When all data bits have been read from or written to, a stop
for the ninth clock pulse (that is, the SDA line remains high). Table 12. Device Address Selection Figure 38. AD5122A/AD5142A Interface Write Command
Figure 39. AD5122A/AD5142A Interface Multiple Write
can be repeated until it succeeds. using Command 3 (see Table 13). prepared to receive data by pulling SDA low. of these data bytes are acknowledged by the AD5122A/AD5142A. The AD5122A/AD5142A do not support repeat readback. Figure 40. AD5122A/AD5142A Interface Read Command
for these universal adjustment devices (see Table 13 and Table 15). Table 13. Advanced Command Operation Truth Table
Table 14. Address Bits
1 X1 X1 X1 All channels All channels All channels All channels Not applicable
Table 15. Control Register Bit Descriptions
and read back from using Command 3 (see Table 13). synchronously by Command 8 (see Table 13). automatically overwrites the associated input register. to set Bit D2 of the control register (see Table 15). ter and linear gain setting mode. set to 1, the parts cannot operate in potentiometer mode. or linear gain setting mode is enabled. Table 16. Top Scale Truth Table Table 17. Bottom Scale Truth Table executed in a single channel or in multiple channels. large adjustments than to small adjustments. Table 18. Detailed Left Shift and Right Shift Functions for the ±6 dB Step
following consecutive bytes as data bytes for the command. the RDAC register are unchanged by entering shutdown mode. LSB (D0) to 0 to exit shutdown mode. Table 19. Truth Table for Shutdown Mode any update to these registers. This can be done by using software. EEPROM into the RDAC register. pin is pulled low, the part powers up in potentiometer mode. potentiometer mode (see Table 15). Figure 41. AD5122A/AD5142A Simplified RDAC Circuit
Data Sheet AD5122A/AD5142A OUTLINE DIMENSIONS analog.com Rev. D | 28 of 29 Package Drawing (Option) Package Type Package Description CP-16-22 LFCSP 16-Lead Lead Frame Chip Scale Package RU-16 TSSOP 16-Lead Thin Shrink Small Outline Package For the latest package outline information and land patterns (footprints), go to Package Index. Updated: March 08, 2022 ORDERING GUIDE Model1, 2 Temperature Range Package Description Packing Quantity Package Option Marking Code AD5122ABCPZ100-RL7 -40°C to +125°C 16-Lead LFCSP (3mm x 3mm w/ EP)Reel, 1500 CP-16-22 DHG AD5122ABCPZ10-RL7 -40°C to +125°C 16-Lead LFCSP (3mm x 3mm w/ EP)Reel, 1500 CP-16-22 DHA AD5122ABRUZ10 -40°C to +125°C 16-Lead TSSOP Tube, 96 RU-16 AD5122ABRUZ100 -40°C to +125°C 16-Lead TSSOP Tube, 96 RU-16 AD5122ABRUZ100-RL7-40°C to +125°C 16-Lead TSSOP Reel, 1000 RU-16 AD5122ABRUZ10-RL7 -40°C to +125°C 16-Lead TSSOP Reel, 1000 RU-16 AD5122AWBCPZ10-RL7-40°C to +125°C 16-Lead LFCSP (3mm x 3mm w/ EP)Reel, 1500 CP-16-22 DN1 AD5142ABCPZ100-RL7 -40°C to +125°C 16-Lead LFCSP (3mm x 3mm w/ EP)Reel, 1500 CP-16-22 DH4 AD5142ABCPZ10-RL7 -40°C to +125°C 16-Lead LFCSP (3mm x 3mm w/ EP)Reel, 1500 CP-16-22 DH7 AD5142ABRUZ10 -40°C to +125°C 16-Lead TSSOP Tube, 96 RU-16 AD5142ABRUZ100 -40°C to +125°C 16-Lead TSSOP Tube, 96 RU-16 AD5142ABRUZ100-RL7-40°C to +125°C 16-Lead TSSOP Reel, 1000 RU-16 AD5142ABRUZ10-RL7 -40°C to +125°C 16-Lead TSSOP Reel, 1000 RU-16 AD5142AWBCPZ10-RL7-40°C to +125°C 16-Lead LFCSP (3mm x 3mm w/ EP)Reel, 1500 CP-16-22 DMZ 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. RAB (KΩ), RESOLUTION, AND INTERFACE OPTIONS Model1, 2 RAB (kΩ) Resolution Interface AD5122ABCPZ10-RL7 10 128 I2C AD5122ABCPZ100-RL7 100 128 I2C AD5122AWBCPZ10-RL7 10 128 I2C AD5122ABRUZ10 10 128 I2C AD5122ABRUZ100 100 128 I2C AD5122ABRUZ10-RL7 10 128 I2C AD5122ABRUZ100-RL7 100 128 I2C AD5142ABCPZ10-RL7 10 256 I2C AD5142ABCPZ100-RL7 100 256 I2C AD5142AWBCPZ10-RL7 10 256 I2C AD5142ABRUZ10 10 256 I2C AD5142ABRUZ100 100 256 I2C AD5142ABRUZ10-RL7 10 256 I2C AD5142ABRUZ100-RL7 100 256 I2C 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications.
Data Sheet AD5122A/AD5142A OUTLINE DIMENSIONS ©2012-2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. D | 29 of 29 EVALUATION BOARDS Model1, 2 Description EVAL-AD5142ADBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with both of the available resistor value options. AUTOMOTIVE PRODUCTS The AD5122AW/AD5142AW models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).