AD5121/AD5141 (Rev.F)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 30
Technical content
Single-Channel, 128-/256-Position, I2C/SPI, Nonvolatile Digital Potentiometer Rev. F DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. All Analog Devices products contained herein are subject to release and availability.
FEATURES
►10 kΩ and 100 kΩ resistance options ►Resistor tolerance: 8% maximum ►Wiper current: ±6 mA ►Low temperature coefficient: 35 ppm/°C ►Wide bandwidth: 3 MHz ►Fast start-up time < 75 µs ►Linear gain setting mode ►Single- and dual-supply operation ►Independent logic supply: 1.8 V to 5.5 V ►Wide operating temperature: −40°C to +125°C ►3 mm × 3 mm LFCSP ►Qualified for automotive applications
APPLICATIONS
►Portable electronics level adjustment ►LCD panel brightness and contrast controls ►Programmable filters, delays, and time constants ►Programmable power supplies FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The AD5121/AD5141 potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the A, B, and W pins. The low resistor tolerance and low nominal temperature coefficient simplify open-loop applications as well as applications requiring tolerance matching. The linear gain setting mode allows independent programming of the resistance between the digital potentiometer terminals, through RAW and RWB string resistors, allowing very accurate resistor matching. The high bandwidth and low total harmonic distortion (THD) ensure optimal performance for ac signals, making it suitable for filter design. The low wiper resistance of only 40 Ω at the ends of the resistor array allows for pin-to-pin connection. The wiper values can be set through an SPI-/I2C-compatible digital interface that is also used to read back the wiper register and EEPROM contents. The AD5121/AD5141 are available in a compact, 16-lead, 3 mm × 3 mm LFCSP. The devices are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Table 1. Family Models 1 Two potentiometers and two rheostats.
analog.com Rev. F | 2 of 30 RAB (kΩ), Resolution, and Interface Options....30
REVISION HISTORY
4/2025—Rev. E to Rev. F 7/2024—Rev. D to Rev. E 5/2022—Rev. C to Rev. D Changes to Single-Supply Power Range Parameter, Dual-Supply Power Range Parameter, and Logic Changes to Single-Supply Power Range Parameter, Dual-Supply Power Range Parameter, Logic
analog.com Rev. F | 3 of 30 ELECTRICAL CHARACTERISTICS—AD5121 otherwise noted. Table 2. Parameter Symbol Test Conditions/CommentsMin Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution N 7 Bits Resistor Integral Nonlinearity2 R-INL RAB = 10 kΩ VDD ≥ 2.7 V −1 ±0.1 +1 LSB VDD < 2.7 V −2.5 ±1 +2.5 LSB RAB = 100 kΩ VDD < 2.7 V −1 ±0.25 +1 LSB Resistor Differential Nonlinearity2 R-DNL −0.5 ±0.1 +0.5 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 ±1 +8 % Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C Wiper Resistance3 RW Code = zero scale RAB = 10 kΩ 55 125 Ω RAB = 100 kΩ 130 400 Ω Bottom Scale or Top Scale RBS or RTS RAB = 10 kΩ 40 80 Ω RAB = 100 kΩ 60 230 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity4 INL RAB = 10 kΩ −0.5 ±0.1 +0.5 LSB RAB = 100 kΩ −0.25 ±0.1 +0.25 LSB Differential Nonlinearity4 DNL −0.25 ±0.1 +0.25 LSB Full-Scale Error VWFSE RAB = 10 kΩ −1.5 −0.1 LSB RAB = 100 kΩ −0.5 ±0.1 +0.5 LSB Zero-Scale Error VWZSE RAB = 10 kΩ 1 1.5 LSB RAB = 100 kΩ 0.25 0.5 LSB Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±5 ppm/°C RESISTOR TERMINALS Maximum Continuous Current IA, IB, and IW RAB = 10 kΩ −6 +6 mA RAB = 100 kΩ −1.5 +1.5 mA Terminal Voltage Range5 VSS VDD V Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ 25 pF RAB = 100 kΩ 12 pF Capacitance W3 CW f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ 12 pF RAB = 100 kΩ 5 pF
Table 2. (Continued)
analog.com Rev. F | 5 of 30 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 12 50 years applies to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years. ELECTRICAL CHARACTERISTICS—AD5141 otherwise noted. Table 3. Parameter Symbol Test Conditions/CommentsMin Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution N 8 Bits Resistor Integral Nonlinearity2 R-INL RAB = 10 kΩ VDD ≥ 2.7 V −2 ±0.2 +2 LSB VDD < 2.7 V −5 ±1.5 +5 LSB RAB = 100 kΩ VDD ≥ 2.7 V −1 ±0.1 +1 LSB VDD < 2.7 V −2 ±0.5 +2 LSB Resistor Differential Nonlinearity2 R-DNL −0.5 ±0.2 +0.5 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 ±1 +8 % Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C Wiper Resistance3 RW Code = zero scale RAB = 10 kΩ 55 125 Ω RAB = 100 kΩ 130 400 Ω Bottom Scale or Top Scale RBS or RTS RAB = 10 kΩ 40 80 Ω RAB = 100 kΩ 60 230 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity4 INL RAB = 10 kΩ −1 ±0.2 +1 LSB RAB = 100 kΩ −0.5 ±0.1 +0.5 LSB Differential Nonlinearity4 DNL −0.5 ±0.2 +0.5 LSB Full-Scale Error VWFSE RAB = 10 kΩ −2.5 −0.1 LSB RAB = 100 kΩ −1 ±0.2 +1 LSB
Table 3. (Continued)
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor integral nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. ±1 LSB maximum are guaranteed monotonic operating conditions. referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. with junction temperature in the Flash/EE memory. 12 50 years applies to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years. VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. SPI Interface
Table 4. SPI Interface (Continued) 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Refer to tEEPROM_PROGRAM and tEEPROM_READBACK for memory commands operations (see Table 6). 3 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF. Table 5. I2C Interface 1 Maximum bus capacitance is limited to 400 pF. 3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
Figure 6. Control Pins Timing Diagram
TA = 25°C, unless otherwise noted.
1 Maximum terminal current is bounded by the maximum current handling of the
voltage across any two of the A, B, and W terminals at a given resistance. 3 Includes programming of EEPROM memory. ing conditions for extended periods may affect product reliability. JEDEC natural convection environment. centerline, measured in a JEDEC θJB environment. Table 8. Thermal Resistance
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD-51. sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. model (CDM) per ANSI/ESDA/JEDEC JS-002. Table 9. AD5121/AD5141, 16-Lead LFCSP damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 7. Pin Configuration Table 10. Pin Function Descriptions 1 GND Ground Pin, Logic Ground Reference. 2 A Terminal A of RDAC. VSS ≤ VA ≤ VDD. 3 W Wiper terminal of RDAC. VSS ≤ VW ≤ VDD. 4 B Terminal B of RDAC. VSS ≤ VB ≤ VDD. 5 VSS Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. 6 SYNC/ADDR0 Programmable Address (ADDR0) for Multiple Package Decoding, DIS = 1. Synchronization Data Input, Active Low. When SYNC returns high, data is loaded into the RDAC register, DIS = 0. 8 DIS Digital Interface Select (SPI/I2C Select). This pin cannot be left floating. 9 VDD Positive Power Supply. Decouple this pin with 0.1µF ceramic capacitors and 10 µF capacitors. 10 VLOGIC Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. 11 SCLK/SCL SPI Serial Clock Line (SCLK). Data is clocked in at logic low transition. I2C Serial Clock Line (SCL). Data is clocked in at logic low transition. 12 SDI/SDA Serial Data Input/Output (SDA), when DIS = 1. Serial Data Input (SDI), when DIS = 0. 14 SDO/ADDR1 Programmable Address (ADDR1) for Multiple Package Decoding, when DIS = 1. Serial Data Output (SDO). This is an open-drain output pin, and it needs an external pull-up resistor when DIS = 0. low. If this pin is not used, tie LRDAC to VLOGIC. that the pad be thermally connected to a copper plane for enhanced thermal performance.
be used to preload the RDAC register data. any changes from taking place. there is no restriction on the number of changes allowed. the digital interface (see Table 13). with Command 3 (see Table 13). followed by four address bits and by eight data bits. to the lowest data bit (Bit 0) is ignored. Table 11. Simple Command Operation Truth Table
0 Normal mode
1 Shutdown mode
Figure 43. AD5121/AD5141 Interface Multiple Write
can be repeated until it succeeds. to receive data by pulling SDA low. enables readback of the RDAC register and EEPROM memory. are both acknowledged by the controller, as shown in Figure 44. The AD5121/AD5141 do not support repeat readback. Figure 44. AD5121/AD5141 Interface Read Command
for these universal adjustment devices (see Table 13 and Table 15). Table 13. Advance Commands Operation Truth Table
Table 14. Address Bits
1 X1 X1 X1 All channels All channels All channels All channels Not applicable
Table 15. Control Register Bit Descriptions The AD5121/AD5141 include one input register per RDAC register. or all the RDAC registers at the same time. from using Command 3 (see Table 13). automatically overwrites the associated input register. control register (see Table 15). ter and linear gain setting modes. the devices cannot operate in potentiometer mode. resistance between Terminal B and Terminal W is specified as RBS.
increment/decrement operations and a shutdown command. gain setting mode is enabled. Table 16. Top Scale Truth Table Table 17. Bottom Scale Truth Table command can be executed in a single channel or multiple channels. large adjustments than to small adjustments. Table 18. Detailed Left Shift and Right Shift Functions for the ±6 dB Step the consecutive bytes as data bytes for the first command. with the contents of the EEPROM and takes approximately 30 µs. Table 13) and set the LSB (D0) to 0 to exit shutdown mode. Table 19. Truth Table for Shutdown Mode
0 N/A1 Open Open RBS
1 Open N/A1 N/A1 N/A1
RAB is the end-to-end resistance. RAB is the end-to-end resistance. RAB is the end-to-end resistance. destruction of the internal switch contact can occur. and precision applications). fractional part, as shown in Table 20. resistance can be calculated as follows. 0.6875, and therefore, tolerance = −2.6875%, and RAB = 9.731 kΩ. A to B, as shown in Figure 47. Figure 47. Potentiometer Mode Configuration RWB(D) can be obtained from Equation 1 and Equation 2. RAW(D) can be obtained from Equation 3 and Equation 4. internal resistors, RAW and RWB, and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/°C.
©2012-2025 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. F | 30 of 30 Package Drawing (Option) Package Type Package Description CP-16-22 LFCSP 16-Lead Lead Frame Chip Scale Package For the latest package outline information and land patterns (footprints), go to Package Index. Updated: March 16, 2022 ORDERING GUIDE Model1, 2 Temperature Range Package Description Packing Quantity Package Option Marking Code AD5121BCPZ100-RL7 -40°C to +125°C 16-Lead LFCSP (3mm x 3mm w/ EP)Reel, 1500 CP-16-22 DHF AD5121BCPZ10-RL7 -40°C to +125°C 16-Lead LFCSP (3mm x 3mm w/ EP)Reel, 1500 CP-16-22 DHE AD5141BCPZ100-RL7 -40°C to +125°C 16-Lead LFCSP (3mm x 3mm w/ EP)Reel, 1500 CP-16-22 DHD AD5141BCPZ10-RL7 -40°C to +125°C 16-Lead LFCSP (3mm x 3mm w/ EP)Reel, 1500 CP-16-22 DHC AD5141WBCPZ10-RL7 -40°C to +125°C 16-Lead LFCSP (3mm x 3mm w/ EP)Reel, 1500 CP-16-22 DN3 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. RAB (KΩ), RESOLUTION, AND INTERFACE OPTIONS Model1, 2 RAB Resolution Interface AD5121BCPZ100-RL7 100 128 SPI/I2C AD5121BCPZ10-RL7 10 128 SPI/I2C AD5141BCPZ100-RL7 100 256 SPI/I2C AD5141BCPZ10-RL7 10 256 SPI/I2C AD5141WBCPZ10-RL7 10 256 SPI/I2C 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. EVALUATION BOARDS Model1, 2 Package Description EVAL-AD5141DBZ Evaluation Board 1 The evaluation board is shipped with the 10 kΩ RAB resistor option. However, the board is compatible with all of the available resistor value options. 2 Z = RoHS Compliant Part. AUTOMOTIVE PRODUCTS The AD5121W/AD5141W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors)