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Single-Channel, 128-/64-/32-Position, I2C, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer Data Sheet AD5110/AD5112/AD5114 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
FEATURES
Single-channel, 128-/64-/32-position resolution 5 kΩ, 10 kΩ, 80 kΩ nominal resistance Maximum ±8% nominal resistor tolerance error Low wiper resistance ±6 mA maximum wiper current density Resistor tolerance stored in EEPROM (0.1% accuracy) Rheostat mode temperature coefficient: 35 ppm/°C Potentiometer mode temperature coefficient: 5 ppm/°C 2.3 V to 5.5 V single-supply operation 1.8 V to 5.5 V logic supply operation Power-on EEPROM refresh time < 50 μs I 2C-compatible interface Wiper setting and EEPROM readback 50-year typical data retention at 125°C 1 million write cycles Wide operating temperature: −40°C to +125°C Thin, 2 mm × 2 mm × 0.55 mm 8-lead LFCSP package
APPLICATIONS
Mechanical potentiometer replacement Portable electronics level adjustment Audio volume control Low resolution DAC LCD panel brightness and contrast control Programmable voltage to current conversion Programmable filters, delays, time constants Feedback resistor programmable power supply Sensor calibration FUNCTIONAL BLOCK DIAGRAM POWER-ON RESET VLOGIC VDD DATA DATA SDA A W B SCL EEPROM AD5110/AD5112/AD5114 RDAC REGISTER GND I2C SERIAL INTERFACE 09582-001 Figure 1. GENERAL DESCRIPTION The AD5110/AD5112/AD5114 provide a nonvolatile solution for 128-/64-/32-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the A, B, and W pins. The low resistor tolerance, low nominal temperature coefficient and high bandwidth simplify open-loop applications, as well as tolerance matching applications. The new low wiper resistance feature minimizes the wiper resistance in the extremes of the resistor array to only 45 Ω, typical. The wiper settings are controllable through an I 2C-compatible digital interface that is also used to readback the wiper register and EEPROM content. Resistor tolerance is stored within EEPROM, providing an end-to-end tolerance accuracy of 0.1%. The AD5110/AD5112/AD5114 are available in a 2 mm × 2 mm LFCSP package. The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Table 1. ±8% Resistance Tolerance Family
AD5110/AD5112/AD5114 Data Sheet Rev. 0 | Page 2 of 28 TABLE OF CONTENTS
REVISION HISTORY
10/11—Revision 0: Initial Version
Data Sheet AD5110/AD5112/AD5114 Rev. 0 | Page 3 of 28 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5110 10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V , VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V , −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resolution N 7 Bits RAB = 10 kΩ, VDD = 2.7 V to 5.5 V −1 ±0.25 +1 LSB RAB = 80 kΩ −0.5 ±0.1 +0.5 LSB Resistor Differential Nonlinearity2 R-DNL −1 ±0.25 +1 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 +8 % Resistance Temperature Coefficient3 (ΔR AB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C Wiper Resistance RW Code = zero scale 70 140 Ω R BS Code = bottom scale 45 80 Ω R TS Code = top scale 70 140 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 INL −0.5 ±0.15 +0.5 LSB Differential Nonlinearity4 DNL −0.5 ±0.15 +0.5 LSB Full-Scale Error VWFSE R AB = 10 kΩ −2.5 LSB RAB = 80 kΩ −1.5 LSB Zero-Scale Error VWZSE R AB = 10 kΩ 1.5 LSB RAB = 80 kΩ 0.5 LSB Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 R AB = 10 kΩ −6 +6 mA R AB = 80 kΩ −1.5 +1.5 mA Terminal Voltage Range5 GND V DD V Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND, code = half scale, VW = VA = 2.5 V or VW = VB = 2.5 V 20 pF Capacitance W3 CW f = 1 MHz, measured to GND, code = half scale, VA = VB = 2.5 V 35 pF Common-Mode Leakage Current3 V A = VW = VB −500 ±15 +500 nA DIGITAL INPUTS Input Logic3 High V INH V LOGIC = 1.8 V to 2.3 V 0.8 × VLOGIC V VLOGIC = 2.3 V to 5.5 V 0.7 × VLOGIC V Low V INL V LOGIC = 1.8 V to 2.3 V 0.2 × V LOGIC V VLOGIC = 2.3 V to 5.5 V 0.3 × V LOGIC V Input Hysteresis3 VHYST 0.1 × VLOGIC V Input Current3 IN ±1 μA Input Capacitance3 CIN 5 pF DIGITAL OUTPUT (SDA) Output Low Voltage3 VOL I SINK = 3 mA 0.2 V ISINK = 6 mA 0.4 V Three-State Leakage Current −1 +1 μA Three-State Output Capacitance3 2 pF
AD5110/AD5112/AD5114 Data Sheet Rev. 0 | Page 4 of 28 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit POWER SUPPLIES Single-Supply Power Range 2.3 5.5 V Logic Supply Range 1.8 V DD V Positive Supply Current IDD V DD = 5 V 750 nA EEMEM Store Current3, 6 IDD_NVM_STORE 2 mA EEMEM Read Current3, 7 IDD_NVM_READ 320 μA Logic Supply Current ILOGIC V IH = VLOGIC or VIL = GND 30 nA Power Dissipation8 P DISS V IH = VLOGIC or VIL = GND 5 μW Power Supply Rejection3 PSR ∆V DD/∆VSS = 5 V ± 10% RAB = 10 kΩ −50 dB RAB = 80 kΩ −64 dB DYNAMIC CHARACTERISTICS3, 9 Bandwidth BW Code = half scale, −3 dB RAB = 10 kΩ 2 MHz RAB = 80 kΩ 200 kHz Total Harmonic Distortion THD VA = VDD/2 +1 V rms, VB = VDD/2, f = 1 kHz, code = half scale RAB = 10 kΩ −80 dB RAB = 80 kΩ −85 dB VW Settling Time ts V A = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 10 kΩ 3 μs RAB = 80 kΩ 12 μs Resistor Noise Density eN_WB Code = half scale, TA = 25°C, f = 100 kHz RAB = 10 kΩ 9 nV/√Hz RAB = 80 kΩ 20 nV/√Hz FLASH/EE MEMORY RELIABILITY3 Endurance10 T A = 25°C 1 MCycles 100 kCycles Data Retention11 50 Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Different from operating current; supply current for NVM program lasts approximately 30 ms. 7 Different from operating current; supply current for NVM read lasts approximately 20 μs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V. 10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory.
Data Sheet AD5110/AD5112/AD5114 Rev. 0 | Page 5 of 28 ELECTRICAL CHARACTERISTICS—AD5112 5 kΩ, 10 kΩ, and 80 kΩ versions: VDD = 2.3 V to 5.5 V , VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V , −40°C < TA < +125°C, unless otherwise noted. Table 3. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resolution N 6 Bits RAB = 5 kΩ, VDD = 2.7 V to 5.5 V −1 ±0.25 +1 LSB RAB = 10 kΩ −1 ±0.25 +1 LSB RAB = 80 kΩ −0.25 ±0.1 +0.25 LSB Resistor Differential Nonlinearity2 R-DNL +1 ±0.25 +1 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 +8 % Resistance Temperature Coefficient3 (ΔR AB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C Wiper Resistance RW Code = zero scale 70 140 Ω R BS Code = bottom scale 45 80 Ω R TS Code = top scale 70 140 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 INL −0.5 ±0.15 +0.5 LSB Differential Nonlinearity4 DNL −0.5 ±0.15 +0.5 LSB Full-Scale Error VWFSE R AB = 5 kΩ −2.5 LSB RAB =10 kΩ −1.5 LSB RAB = 80 kΩ −1 LSB Zero-Scale Error VWZSE R AB = 5 kΩ 1.5 LSB RAB =10 kΩ 1 LSB RAB = 80 kΩ 0.25 LSB Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 R AB = 5 kΩ, 10 kΩ −6 +6 mA R AB = 80 kΩ −1.5 +1.5 mA Terminal Voltage Range5 GND V DD V Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND, code = half scale, VW = VA = 2.5 V or VW = VB = 2.5 V 20 pF Capacitance W3 CW f = 1 MHz, measured to GND, code = half scale, V A = VB = 2.5 V 35 pF Common-Mode Leakage Current3 V A = VW = VB −500 ±15 +500 nA DIGITAL INPUTS Input Logic3 High V INH V LOGIC = 1.8 V to 2.3 V 0.8 × VLOGIC V VLOGIC = 2.3 V to 5.5 V 0.7 × V LOGIC V Low V INL V LOGIC = 1.8 V to 2.3 V 0.2 × V LOGIC V VLOGIC = 2.3 V to 5.5 V 0.3 × V LOGIC V Input Hysteresis3 VHYST 0.1 × VLOGIC V Input Current3 IN ±1 μA Input Capacitance3 CIN 5 pF DIGITAL OUTPUT (SDA) Output Low Voltage3 VOL I SINK = 3 mA 0.2 V ISINK = 6 mA 0.4 V Three-State Leakage Current −1 +1 μA Three-State Output Capacitance3 2 pF
AD5110/AD5112/AD5114 Data Sheet Rev. 0 | Page 6 of 28 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit POWER SUPPLIES Single-Supply Power Range 2.3 5.5 V Logic Supply Range 1.8 V DD V Positive Supply Current IDD V DD = 5 V 750 nA EEMEM Store Current3, 6 IDD_NVM_STORE 2 mA EEMEM Read Current3, 7 IDD_NVM_READ 320 μA Logic Supply Current ILOGIC V IH = VLOGIC or VIL = GND 30 nA Power Dissipation8 P DISS V IH = VLOGIC or VIL = GND 5 μW Power Supply Rejection3 PSR ∆V DD/∆VSS = 5 V ± 10% RAB = 5 kΩ −43 dB RAB =10 kΩ −50 dB RAB = 80 kΩ −64 dB DYNAMIC CHARACTERISTICS3, 9 Bandwidth BW Code = half scale − 3 dB RAB = 5 kΩ 4 MHz RAB = 10 kΩ 2 MHz RAB = 80 kΩ 200 kHz Total Harmonic Distortion THD VA = VDD/2 + 1 V rms, VB = VDD/2, f = 1 kHz, code = half scale RAB = 5 kΩ −75 dB RAB = 10 kΩ −80 dB RAB = 80 kΩ −85 dB VW Settling Time ts V A = 5 V, VB = 0 V, ±0.5 LSB error band μ s RAB = 5 kΩ 2.5 μs RAB = 10 kΩ 3 μs RAB = 80 kΩ 10 μs Resistor Noise Density eN_WB Code = half scale, TA = 25°C, f = 100 kHz RAB = 5 kΩ 7 nV/√Hz RAB = 10 kΩ 9 nV/√Hz RAB = 80 kΩ 20 nV/√Hz FLASH/EE MEMORY RELIABILITY3 Endurance10 T A = 25°C 1 MCycles 100 kCycles Data Retention11 50 Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Different from operating current; supply current for NVM program lasts approximately 30 ms. 7 Different from operating current; supply current for NVM read lasts approximately 20 μs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V. 10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory.
Data Sheet AD5110/AD5112/AD5114 Rev. 0 | Page 7 of 28 ELECTRICAL CHARACTERISTICS—AD5114 10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V , VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V , −40°C < TA < +125°C, unless otherwise noted. Table 4. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resolution N 5 Bits Resistor Integral Nonlinearity2 R-INL −0.5 +0.5 LSB Resistor Differential Nonlinearity2 R-DNL −0.25 +0.25 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 +8 % Resistance Temperature Coefficient3 (ΔR AB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C Wiper Resistance RW Code = zero scale 70 140 Ω R BS Code = bottom scale 45 80 Ω R TS Code = top scale 70 140 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 INL −0.25 +0.25 LSB Differential Nonlinearity4 DNL −0.25 +0.25 LSB Full-Scale Error VWFSE R AB = 10 kΩ −1 LSB RAB = 80 kΩ −0.5 LSB Zero-Scale Error VWZSE R AB = 10 kΩ 1 LSB RAB = 80 kΩ 0.25 LSB Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 R AB = 10 kΩ −6 +6 mA R AB = 80 kΩ −1.5 +1.5 mA Terminal Voltage Range5 GND V DD V Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND, code = half scale, VW = VA = 2.5 V or VW = VB = 2.5 V 20 pF Capacitance W3 CW f = 1 MHz, measured to GND, code = half scale, V A = VB = 2.5 V 35 pF Common-Mode Leakage Current3 V A = VW = VB −500 ±15 +500 nA DIGITAL INPUTS Input Logic3 High V INH V LOGIC = 1.8 V to 2.3 V 0.8 × VLOGIC V VLOGIC = 2.3 V to 5.5 V 0.7 × VLOGIC V Low V INL V LOGIC = 1.8 V to 2.3 V 0.2 × V LOGIC V VLOGIC = 2.3 V to 5.5 V 0.3 × V LOGIC V Input Hysteresis3 VHYST 0.1 × VLOGIC V Input Current3 IN ±1 μA Input Capacitance3 CIN 5 pF DIGITAL OUTPUT (SDA) Output Low Voltage3 VOL I SINK = 3 mA 0.2 V ISINK = 6 mA 0.4 V Three-State Leakage Current −1 +1 μA Three-State Output Capacitance3 2 pF
AD5110/AD5112/AD5114 Data Sheet Rev. 0 | Page 8 of 28 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit POWER SUPPLIES Single-Supply Power Range 2.3 5.5 V Logic Supply Range 1.8 V DD V Positive Supply Current IDD V DD = 5 V 750 nA EEMEM Store Current3, 6 IDD_NVM_STORE 2 mA EEMEM Read Current3,7 IDD_NVM_READ 320 μA Logic Supply Current ILOGIC V IH = VLOGIC or VIL = GND 30 nA Power Dissipation8 P DISS V IH = VLOGIC or VIL = GND 5 μW Power Supply Rejection3 PSR ∆V DD/∆VSS = 5 V ± 10% RAB = 10 kΩ −50 dB RAB = 80 kΩ −64 dB DYNAMIC CHARACTERISTICS3, 9 Bandwidth BW Code = half scale, −3 dB RAB = 10 kΩ 2 MHz RAB = 80 kΩ 200 kHz Total Harmonic Distortion THD VA = VDD/2 + 1 V rms, VB = VDD/2, f = 1 kHz, code = half scale RAB = 10 kΩ −80 dB RAB = 80 kΩ −85 dB VW Settling Time ts V A = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 10 kΩ 2.7 μs RAB = 80 kΩ 9.5 μs Resistor Noise Density eN_WB Code = half scale, TA = 25°C, f = 100 kHz RAB = 10 kΩ 9 nV/√Hz RAB = 80 kΩ 20 nV/√Hz FLASH/EE MEMORY RELIABILITY3 Endurance10 T A = 25°C 1 MCycles 100 kCycles Data Retention11 50 Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Different from operating current; supply current for NVM program lasts approximately 30 ms. 7 Different from operating current; supply current for NVM read lasts approximately 20 μs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V. 10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory.
Data Sheet AD5110/AD5112/AD5114 Rev. 0 | Page 9 of 28 INTERFACE TIMING SPECIFICATIONS VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter1 Test Conditions/ Comments Min Typ Max Unit Description fSCL2 Standard mode 100 kHz Serial clock frequency Fast mode 400 kHz t1 Standard mode 4.0 µs tHIGH, SCL high time Fast mode 0.6 µs t2 Standard mode 4.7 µs tLOW, SCL low time Fast mode 1.3 µs t3 Standard mode 250 ns tSU;DAT, data setup time Fast mode 100 ns t4 Standard mode 0 3.45 µs tHD;DAT, data hold time Fast mode 0 0.9 µs t5 Standard mode 4.7 µs tSU;STA, setup time for a repeated start condition Fast mode 0.6 µs t6 Standard mode 4 µs tHD;STA, hold time (repeated) start condition Fast mode 0.6 µs t7 Standard mode 4.7 µs tBUF, bus free time between a stop and a start condition Fast mode 1.3 µs t8 Standard mode 4 µs tSU;STO, setup time for stop condition Fast mode 0.6 µs t9 Standard mode 1000 ns tRDA, rise time of SDA signal Fast mode 20 + 0.1 CL 300 ns t10 Standard mode 300 ns tFDA, fall time of SDA signal Fast mode 20 + 0.1 CL 300 ns t11 Standard mode 1000 ns tRCL, rise time of SCL signal Fast mode 20 + 0.1 CL 300 ns t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit. Fast mode 20 + 0.1 CL 300 ns t12 Standard mode 300 ns tFCL, fall time of SCL signal Fast mode 20 + 0.1 CL 300 ns tSP3 Fast mode 0 50 ns Pulse width of suppressed spike tEEPROM_PROGRAM 4 15 50 ms Memory program time tPOWER_UP5 50 µs Power-on EEPROM restore time tRESET 25 µs Reset EEPROM restore time 1 Maximum bus capacitance is limited to 400 pF. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode. 4 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles. 5 Maximum time after VDD is equal to 2.3 V.
TA = 25°C, unless otherwise noted.
1 Maximum terminal current is bounded by the maximum current handling of
3 Includes programming of EEPROM memory. dependent on the test board and test environment. Table 7. Thermal Resistance 1 JEDEC 2S2P test board, still air (0 m/sec air flow).
6 SCL
5 GND
8 VLOGIC
7 SDA
- THE EXPOSED PAD IS INTERNALLY FLOATING.
Figure 4. Pin Configuration Table 8. Pin Function Descriptions 2 A Terminal A of RDAC. GND ≤ VA ≤ VDD. 3 W Wiper Terminal of RDAC. GND ≤ VW ≤ VDD. 4 B Terminal B of RDAC. GND ≤ VB ≤ VDD. 5 GND Ground Pin, Logic Ground Reference. EPAD Exposed Pad. The exposed pad is internally floating.
register that allows unlimited changes of resistance settings. is found, this value can be stored in the EEPROM memory. 2C interface (see Table 10). the data saved into the EEPROM with Command 6 in Table 10. to-end tolerance, providing an accuracy of 0.1%. Figure 3 for a timing diagram of a typical write sequence. 10-bit addressing and general call addressing.
- The master initiates data transfer by establishing a start
the ninth clock pulse (this is termed the acknowledge bit).
- Data is transmitted over the serial bus in sequences of nine
- When all data bits have been read or written, a stop
address options available. See Table 9 for a list of slave addresses. Table 9. Device Address Selection
DB1 are don’t cares. Data is loaded MSB first (Bit DB15). typical AD5110/AD5112/AD5114 write sequence. are the values that are loaded into the decoded register. Table 10. Command Operation Truth Table 2 In the AD5114, this bit is a don’t care. 3 In the AD5112, this bit is a don’t care.
interface by using Command 6 (see Table 10). the user must first issue a readback command to the device. factory, and initial power-up is, accordingly, at midscale. the software shutdown command, Command 3 (see Table 10). Figure 45. AD5110 Interface Read Command
produces a digitally controlled complementary resistance, RWA. RAB is the end-to-end resistance. RTS is the wiper resistance at top scale. current of ±6 mA or to the pulse current specified in Table 6. tolerance matching, and precision applications. read back by executing Command 6 and setting Bit DB0 (A0). three LSBs, as shown in Table 11. Table 11. Tolerance Format to-A, and W-to-B can be at either polarity. Figure 48. Potentiometer Mode Configuration RWB(D) can be obtained from Equation 1 to Equation 6. RAW(D) can be obtained from Equation 7 to Equation 15.
0.20 REF
0.05 MAX
0.02 NOM
0.50 BSC
Figure 51. 8-Lead Frame Chip Scale Package[LFCSP_UD]
AD5110/AD5112/AD5114 Data Sheet Rev. 0 | Page 28 of 28 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09582-0-10/11(0)