AD5111_V01 AD | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 24
Technical content
Single-Channel, 128-/64-/32-Position, Up/Down, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer Data Sheet AD5111/AD5113/AD5115 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2011–2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Nominal resistor tolerance error: ±8% maximum Wiper current: ±6 mA Rheostat mode temperature coefficient: 35 ppm/°C Low power consumption: 2.5 µA max @ 2.7 V and 125°C Wide bandwidth: 4 MHz (5 kΩ option) Power-on EEPROM refresh time < 50 μs 50-year typical data retention at 125°C 1 million write cycles 2.3 V to 5.5 V supply operation Chip select enable multiple device operation Wide operating temperature: −40°C to +125°C Thin, 2 mm × 2 mm × 0.55 mm 8-lead LFCSP package
APPLICATIONS
Mechanical potentiometer replacement Portable electronics level adjustment Audio volume control Low resolution DAC LCD panel brightness and contrast control Programmable voltage to current conversion Programmable filters, delays, time constants Feedback resistor programmable power supply Sensor calibration FUNCTIONAL BLOCK DIAGRAM GND RDAC REGISTER UP/DOWN CONTROL LOGIC POWER-ON RESET VDD U/D CLK CS EEPROM DATA DATA A W B EN AD5111/ AD5113/ AD5115 09654-001 Figure 1. Table 1. ±8% Resistance Tolerance Family or high speed digital control with clock rates up to 50 MHz. extended industrial temperature range of −40°C to +125°C.
AD5111/AD5113/AD5115 Data Sheet Rev. B | Page 2 of 24 TABLE OF CONTENTS
REVISION HISTORY
11/12—Rev. A to Rev. B 4/12—Rev. 0 to Rev. A 10/11—Revision 0: Initial Version
Data Sheet AD5111/AD5113/AD5115 Rev. B | Page 3 of 24 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5111 10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V , VA = VDD, VB = 0 V , −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resolution N 7 Bits RAB = 10 kΩ, VDD = 2.7 V to 5.5 V −1 ±0.25 +1 LSB RAB = 80 kΩ −0.5 ±0.1 +0.5 LSB Resistor Differential Nonlinearity2 R-DNL −1 ±0.25 +1 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 +8 % Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 35 ppm/°C Wiper Resistance RW Code = zero scale 70 140 Ω RBS Code = bottom scale 45 80 Ω RTS Code = top scale 70 140 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 INL −0.5 ±0.15 +0.5 LSB Differential Nonlinearity4 DNL −0.5 ±0.15 +0.5 LSB Full-Scale Error VWFSE RAB = 10 kΩ −2.5 LSB RAB = 80 kΩ −1.5 LSB Zero-Scale Error VWZSE RAB = 10 kΩ 1.5 LSB RAB = 80 kΩ 0.5 LSB Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 RAB = 10 kΩ −6 +6 mA RAB = 80 kΩ −1.5 +1.5 mA Terminal Voltage Range5 GND VDD V Capacitance A, Capacitance B3, 6 CA, CB f = 1 MHz, measured to GND, code = half scale 20 pF Capacitance W3, 6 CW f = 1 MHz, measured to GND, code = half scale 35 pF Common-Mode Leakage Current3 VA = VW = VB −500 ±15 +500 nA DIGITAL INPUTS Input Logic3 High VINH 2 V Low VINL 0.8 V Input Current3 IN ±1 µA Input Capacitance3 CIN 5 pF POWER SUPPLIES Single-Supply Power Range 2.3 5.5 V Positive Supply Current IDD VIH = VDD or VIL = GND, VDD = 5 V 0.75 3.5 µA VIH = VDD or VIL = GND, VDD = 2.7 V 2.5 µA VIH = VDD or VIL = GND, VDD = 2.3 V 2.4 µA EEMEM Store Current3, 7 IDD_NVM_STORE 2 mA EEMEM Read Current3, 8 IDD_NVM_READ 320 µA Power Dissipation9 PDISS VIH = VDD or VIL = GND 5 µW Power Supply Rejection3 PSR ∆VDD/∆VSS = 5 V ± 10% RAB = 10 kΩ −50 dB RAB = 80 kΩ −64 dB
AD5111/AD5113/AD5115 Data Sheet Rev. B | Page 4 of 24 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DYNAMIC CHARACTERISTICS3, 10 Bandwidth BW Code = half scale, −3 dB RAB = 10 kΩ 2 MHz RAB = 80 kΩ 200 kHz Total Harmonic Distortion THD VA = VDD/2 + 1 V rms, VB = VDD/ 2, f = 1 kHz, code = half scale RAB = 10 kΩ −80 dB RAB = 80 kΩ −85 dB VW Settling Time ts VA = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 10 kΩ 3 µs RAB = 80 kΩ 12 µs Resistor Noise Density eN_WB Code = half scale, TA = 25°C, f = 100 kHz RAB = 10 kΩ 9 nV/√Hz RAB = 80 kΩ 20 nV/√Hz FLASH/EE MEMORY RELIABILITY3 Endurance11 TA = 25°C 1 MCycles 100 kCycles Data Retention12 50 Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB. 3 Guaranteed by design and characterization; not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on current direction with respect to each other. 6 CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V. 7 Different from operating current; supply current for NVM program lasts approximately 30 ms. 8 Different from operating current; supply current for NVM read lasts approximately 20 µs. 9 PDISS is calculated from (IDD × VDD). 10 All dynamic characteristics use VDD = 5.5 V and VLOGIC = 5 V. 11 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 12 Retention lifetime equivalent at junction temperature (TJ) is 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory.
Data Sheet AD5111/AD5113/AD5115 Rev. B | Page 5 of 24 ELECTRICAL CHARACTERISTICS—AD5113 5 kΩ, 10 kΩ, and 80 kΩ versions: VDD = 2.3 V to 5.5 V , VA = VDD, VB = 0 V , −40°C < TA < +125°C, unless otherwise noted. Table 3. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resolution N 6 Bits RAB = 5 kΩ, VDD = 2.7 V to 5.5 V −1 ±0.25 +1 LSB RAB = 10 kΩ −1 ±0.25 +1 LSB RAB = 80 kΩ −0.25 ±0.1 +0.25 LSB Resistor Differential Nonlinearity2 R-DNL −1 ±0.25 +1 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 +8 % Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 35 ppm/°C Wiper Resistance RW Code = zero scale 70 140 Ω RBS Code = bottom scale 45 80 Ω RTS Code = top scale 70 140 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 INL −0.5 ±0.15 +0.5 LSB Differential Nonlinearity4 DNL −0.5 ±0.15 +0.5 LSB Full-Scale Error VWFSE RAB = 5 kΩ −2.5 LSB RAB =10 kΩ −1.5 LSB RAB = 80 kΩ −1 LSB Zero-Scale Error VWZSE RAB = 5 kΩ 1.5 LSB RAB =10 kΩ 1 LSB RAB = 80 kΩ 0.25 LSB Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 RAB = 5 kΩ, 10 kΩ −6 +6 mA RAB = 80 kΩ −1.5 +1.5 mA Terminal Voltage Range5 GND VDD V Capacitance A, Capacitance B3, 6 CA, CB f = 1 MHz, measured to GND, code = half scale 20 pF Capacitance W3, 6 CW f = 1 MHz, measured to GND, code = half scale 35 pF Common-Mode Leakage Current3 VA = VW = VB −500 ±15 +500 nA DIGITAL INPUTS Input Logic3 High VINH 2 V Low VINL 0.8 V Input Current3 IN ±1 µA Input Capacitance3 CIN 5 pF POWER SUPPLIES Single-Supply Power Range 2.3 5.5 V Positive Supply Current IDD VIH = VDD or VIL = GND, VDD = 5 V 0.75 3.5 µA VIH = VDD or VIL = GND, VDD = 2.7 V 2.5 µA VIH = VDD or VIL = GND, VDD = 2.3 V 2.4 µA EEMEM Store Current3, 7 IDD_NVM_STORE 2 mA EEMEM Read Current3, 8 IDD_NVM_READ 320 µA Power Dissipation9 PDISS VIH = VDD or VIL = GND 5 µW Power Supply Rejection3 PSR ∆VDD/∆VSS = 5 V ± 10% RAB = 5 kΩ −43 dB RAB =10 kΩ −50 dB RAB = 80 kΩ −64 dB
AD5111/AD5113/AD5115 Data Sheet Rev. B | Page 6 of 24 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DYNAMIC CHARACTERISTICS3, 10 Bandwidth BW Code = half scale, −3 dB RAB = 5 kΩ 4 MHz RAB = 10 kΩ 2 MHz RAB = 80 kΩ 200 kHz Total Harmonic Distortion THD VA = VDD/2 + 1 V rms, VB = VDD/2, f = 1 kHz, code = half scale RAB = 5 kΩ −75 dB RAB = 10 kΩ −80 dB RAB = 80 kΩ −85 dB VW Settling Time ts VA = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 5 kΩ 2.5 µs RAB = 10 kΩ 3 µs RAB = 80 kΩ 10 µs Resistor Noise Density eN_WB Code = half scale, TA = 25°C, f = 100 kHz RAB = 5 kΩ 7 nV/√Hz RAB = 10 kΩ 9 nV/√Hz RAB = 80 kΩ 20 nV/√Hz FLASH/EE MEMORY RELIABILITY3 Endurance11 TA = 25°C 1 MCycles 100 kCycles Data Retention12 50 Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB. 3 Guaranteed by design and characterization; not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on current direction with respect to each other. 6 CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V. 7 Different from operating current; supply current for NVM program lasts approximately 30 ms. 8 Different from operating current; supply current for NVM read lasts approximately 20 µs. 9 PDISS is calculated from (IDD × VDD). 10 All dynamic characteristics use VDD = 5.5 V and VLOGIC = 5 V. 11 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 12 Retention lifetime equivalent at junction temperature (TJ) is 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory.
Data Sheet AD5111/AD5113/AD5115 Rev. B | Page 7 of 24 ELECTRICAL CHARACTERISTICS—AD5115 10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V , VA = VDD, VB = 0 V , −40°C < TA < +125°C, unless otherwise noted. Table 4. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resolution N 5 Bits Resistor Integral Nonlinearity2 R-INL −0.5 +0.5 LSB Resistor Differential Nonlinearity2 R-DNL −0.25 +0.25 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 +8 % Resistance Temperature Coefficient3 (ΔR AB/RAB)/ΔT × 106 35 ppm/°C Wiper Resistance RW Code = zero scale 70 140 Ω R BS Code = bottom scale 45 80 Ω R TS Code = top scale 70 140 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 INL −0.25 +0.25 LSB Differential Nonlinearity4 DNL −0.25 +0.25 LSB Full-Scale Error VWFSE R AB = 10 kΩ −1 LSB RAB = 80 kΩ −0.5 LSB Zero-Scale Error VWZSE R AB = 10 kΩ 1 LSB RAB = 80 kΩ 0.25 LSB Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 R AB = 10 kΩ −6 +6 mA RAB = 80 kΩ −1.5 +1.5 mA Terminal Voltage Range5 GND V DD V Capacitance A, Capacitance B3, 6 CA, CB f = 1 MHz, measured to GND, code = half scale 20 pF Capacitance W3, 6 CW f = 1 MHz, measured to GND, code = half scale 35 pF Common-Mode Leakage Current3 V A = VW = VB −500 ±15 +500 nA DIGITAL INPUTS Input Logic3 High V INH 2 V Low V INL 0.8 V Input Current3 IN ±1 μA Input Capacitance3 CIN 5 pF POWER SUPPLIES Single-Supply Power Range 2.3 5.5 V Positive Supply Current IDD V IH = VDD or VIL = GND, VDD = 5 V 0.75 3.5 μA VIH = VDD or VIL = GND, VDD = 2.7 V 2.5 μA VIH = VDD or VIL = GND, VDD = 2.3 V 2.4 μA EEMEM Store Current3, 7 IDD_NVM_STORE 2 mA EEMEM Read Current3, 8 IDD_NVM_READ 320 μA Power Dissipation9 P DISS V IH = VDD or VIL = GND 5 μW Power Supply Rejection3 PSR ∆V DD/∆VSS = 5 V ± 10% RAB = 10 kΩ −50 dB RAB = 80 kΩ −64 dB
AD5111/AD5113/AD5115 Data Sheet Rev. B | Page 8 of 24 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DYNAMIC CHARACTERISTICS3, 10 Bandwidth BW Code = half scale, −3 dB RAB = 10 kΩ 2 MHz RAB = 80 kΩ 200 kHz Total Harmonic Distortion THD VA = VDD/2 + 1 V rms, VB = VDD/2, f = 1 kHz, code = half scale RAB = 10 kΩ −80 dB RAB = 80 kΩ −85 dB VW Settling Time ts V A = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 10 kΩ 2.7 μs RAB = 80 kΩ 9.5 μs Resistor Noise Density eN_WB Code = half scale, TA = 25°C, f = 100 kHz RAB = 10 kΩ 9 nV/√Hz RAB = 80 kΩ 20 V FLASH/EE MEMORY RELIABILITY3 Endurance11 T A = 25°C 1 MCycles 100 kCycles Data Retention12 50 Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB. 3 Guaranteed by design and characterization; not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on current direction with respect to each other. 6 CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V. 7 Different from operating current; supply current for NVM program lasts approximately 30 ms. 8 Different from operating current; supply current for NVM read lasts approximately 20 μs. 9 PDISS is calculated from (IDD × VDD). 10 All dynamic characteristics use VDD = 5.5 V and VLOGIC = 5 V. 11 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 12 Retention lifetime equivalent at junction temperature (TJ) is 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory.
TA = 25°C, unless otherwise noted.
1 Maximum terminal current is bounded by the maximum current handling of
3 Includes programming of EEPROM memory. dependent on the test board and test environment. Table 7. Thermal Resistance 1 JEDEC 2S2P test board, still air (0 m/sec air flow).
6 CLK
5 GND
7 U/D
- THE EXPOSED PAD IS INTERNALLY
Figure 5. Pin Configuration Table 8. Pin Function Descriptions 1 VDD Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. 2 A Terminal A of RDAC. GND ≤ VA ≤ VDD. 3 W Wiper Terminal of RDAC. GND ≤ VW ≤ VDD. 4 B Terminal B of RDAC. GND ≤ VB ≤ VDD. 5 GND Ground Pin, Logic Ground Reference. by the state of the U/D pin. CLK is a negative edge trigger. Data can be transferred at rates up to 50 MHz. 7 U/D Up/Down Selection Counter Control. 8 CS Chip Select. Active Low. EPAD Exposed Pad. The exposed pad is internally floating.
register that allows unlimited changes of resistance settings. position is found, this value can be stored in the EEPROM. speed digital control with clock rates up to 50 MHz. there is no restriction on the number of changes allowed. supply sequence or recall operation. scale or full-scale position has been reached. the INL, DNL, R-INL, and R-DNL specifications. D pin, when CLK is high and CS is enabled. shutdown position if any other operation is performed. position is found, this value can be saved into the EEPROM. any future power-up sequence or a memory recall operation. Figure 3. The write cycle takes approximately 20 ms.
produces a digitally controlled complementary resistance, RWA. RDAC register; 128, 64, and 32 refer to top scale step. RAB is the end-to-end resistance. RTS is the wiper resistance at top scale. or ±1.5 mA (80 kΩ), or pulse current specified in Table 6. and W-to-B can be in either direction. Figure 44. Potentiometer Mode Configuration produces an output voltage at W to B ranging from 0 V to 5 V. RWB(D) can be obtained from Equation 1 to Equation 6. RAW(D) can be obtained from Equation 7 to Equation 14.
AD5111/AD5113/AD5115 Data Sheet Rev. B | Page 22 of 24 OUTLINE DIMENSIONS 1.70 1.60 1.50 0.425 0.350 0.275 TOP VIEW 0.30 0.25 0.20 BOTTOM VIEW PIN 1 INDEX AREA 2.00 BSC SQ SEATING PLANE 0.60 0.55 0.50 1.10 1.00 0.90
0.20 REF
0.175 REF
0.05 MAX
0.02 NOM
0.50 BSC
(R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 07-11-2011-B Figure 47. 8-Lead Frame Chip Scale Package [LFCSP_UD]
Description
AD5111BCPZ10-RL7 10 128 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7S AD5111BCPZ10-500R7 10 128 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7S AD5111BCPZ80-RL7 80 128 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7T AD5111BCPZ80-500R7 80 128 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7T AD5113BCPZ5-RL7 5 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 85 AD5113BCPZ5-500R7 5 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 85 AD5113BCPZ10-RL7 10 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 84 AD5113BCPZ10-500R7 10 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 84 AD5113BCPZ80-RL7 80 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 86 AD5113BCPZ80-500R7 80 64 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 86 AD5115BCPZ10-RL7 10 32 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7Y AD5115BCPZ10-500R7 10 32 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7Y AD5115BCPZ80-RL7 80 32 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7Z AD5115BCPZ80-500R7 80 32 −40°C to +125°C 8-Lead LFCSP_UD CP-8-10 7Z EVAL-AD5111SDZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The EVAL-AD5111SDZ has an RAB of 10 kΩ.
Data Sheet AD5111/AD5113/AD5115 Rev. B | Page 23 of 24 NOTES
AD5111/AD5113/AD5115 Data Sheet Rev. B | Page 24 of 24 NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09654-0-11/12(B)