AD5110_V01 AD | Alldatasheet
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Technical content
Single-Channel, 128-/64-/32-Position, I2C, 8% Resistor Tolerance, Nonvolatile Digital Potentiometer Rev. D DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►Nominal resistor tolerance error: ±8% maximum ►Wiper current: ±6 mA ►Rheostat mode temperature coefficient: 35 ppm/°C ►Low power consumption: 2.5 µA max @ 2.7 V and 125°C ►Wide bandwidth: 4 MHz (5 kΩ option) ►Power-on EEPROM refresh time < 50 μs ►50-year typical data retention at 125°C ►1 million write cycles ►2.3 V to 5.5 V analog supply operation ►1.8 V to 5.5 V logic supply operation ►Wide operating temperature: −40°C to +125°C ►Thin, 2 mm × 2 mm × 0.55 mm 8-lead LFCSP package
APPLICATIONS
►Mechanical potentiometer replacement ►Portable electronics level adjustment ►Audio volume control ►Low resolution DAC ►LCD panel brightness and contrast control ►Programmable voltage to current conversion ►Programmable filters, delays, time constants ►Feedback resistor programmable power supply ►Sensor calibration FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The AD5110/AD5112/AD5114 provide a nonvolatile solution for 128-/64-/32-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the A, B, and W pins. The low resistor tolerance, low nominal temperature coefficient and high bandwidth simplify open- loop applications, as well as tolerance matching applications. The new low wiper resistance feature minimizes the wiper resist- ance in the extremes of the resistor array to only 45 Ω, typical. The wiper settings are controllable through an I2C-compatible digital interface that is also used to readback the wiper register and EEPROM content. Resistor tolerance is stored within EEPROM, providing an end-to-end tolerance accuracy of 0.1%. The AD5110/AD5112/AD5114 are available in a 2 mm × 2 mm LFCSP package. The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Table 1. ±8% Resistance Tolerance Family
Data Sheet AD5110/AD5112/AD5114 TABLE OF CONTENTS analog.com Rev. D | 2 of 28 RAB (kΩ), Resolution, and I2C Address
REVISION HISTORY
5/2024—Rev. C to Rev. D 1/2022—Rev. B to Rev. C Changes to Single-Supply Power Range Parameter, Logic Supply Range Parameter, and Bandwidth Changes to Single-Supply Power Range Parameter, Logic Supply Range Parameter, and Bandwidth Changes to Single-Supply Power Range Parameter, Logic Supply Range Parameter, and Bandwidth
Data Sheet AD5110/AD5112/AD5114 SPECIFICATIONS analog.com Rev. D | 3 of 28 ELECTRICAL CHARACTERISTICS—AD5110 10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resolution N 7 Bits RAB = 10 kΩ, VDD = 2.7 V to 5.5 V −1 ±0.25 +1 LSB RAB = 80 kΩ −0.5 ±0.1 +0.5 LSB Resistor Differential Nonlinearity2 R-DNL −1 ±0.25 +1 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 +8 % Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C Wiper Resistance RW Code = zero scale 70 140 Ω RBS Code = bottom scale 45 80 Ω RTS Code = top scale 70 140 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 INL −0.5 ±0.15 +0.5 LSB Differential Nonlinearity4 DNL −0.5 ±0.15 +0.5 LSB Full-Scale Error VWFSE RAB = 10 kΩ −2.5 LSB RAB = 80 kΩ −1.5 LSB Zero-Scale Error VWZSE RAB = 10 kΩ 1.5 LSB RAB = 80 kΩ 0.5 LSB Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 RAB = 10 kΩ −6 +6 mA RAB = 80 kΩ −1.5 +1.5 mA Terminal Voltage Range5 GND VDD V Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND, code = half scale, VW = VA = 2.5 V or VW = VB = 2.5 V 20 pF Capacitance W3 CW f = 1 MHz, measured to GND, code = half scale, VA = VB = 2.5 V 35 pF Common-Mode Leakage Current3 VA = VW = VB −500 ±15 +500 nA DIGITAL INPUTS Input Logic3 High VINH VLOGIC = 1.8 V to 2.3 V 0.8 × VLOGIC V VLOGIC = 2.3 V to 5.5 V 0.7 × VLOGIC V Low VINL VLOGIC = 1.8 V to 2.3 V 0.2 × VLOGIC V VLOGIC = 2.3 V to 5.5 V 0.3 × VLOGIC V Input Hysteresis3 VHYST 0.1 × VLOGIC V Input Current3 IN ±1 µA Input Capacitance3 CIN 5 pF DIGITAL OUTPUT (SDA) Output Low Voltage3 VOL ISINK = 3 mA 0.2 V ISINK = 6 mA 0.4 V Three-State Leakage Current −1 +1 µA Three-State Output Capacitance3 2 pF
Table 2. (Continued) 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB. 3 Guaranteed by design and characterization, not subject to production test. ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Different from operating current; supply current for NVM program lasts approximately 30 ms. 7 Different from operating current; supply current for NVM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V. 10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. with junction temperature in the Flash/EE memory.
Data Sheet AD5110/AD5112/AD5114 SPECIFICATIONS analog.com Rev. D | 5 of 28 ELECTRICAL CHARACTERISTICS—AD5112 5 kΩ, 10 kΩ, and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 3. Parameter Symbol Test Conditions/CommentsMin Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resolution N 6 Bits RAB = 5 kΩ, VDD = 2.7 V to 5.5 V −1 ±0.25 +1 LSB RAB = 10 kΩ −1 ±0.25 +1 LSB RAB = 80 kΩ −0.25 ±0.1 +0.25 LSB Resistor Differential Nonlinearity2 R-DNL +1 ±0.25 +1 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 +8 % Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C Wiper Resistance RW Code = zero scale 70 140 Ω RBS Code = bottom scale 45 80 Ω RTS Code = top scale 70 140 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 INL −0.5 ±0.15 +0.5 LSB Differential Nonlinearity4 DNL −0.5 ±0.15 +0.5 LSB Full-Scale Error VWFSE RAB = 5 kΩ −2.5 LSB RAB =10 kΩ −1.5 LSB RAB = 80 kΩ −1 LSB Zero-Scale Error VWZSE RAB = 5 kΩ 1.5 LSB RAB =10 kΩ 1 LSB RAB = 80 kΩ 0.25 LSB Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 RAB = 5 kΩ, 10 kΩ −6 +6 mA RAB = 80 kΩ −1.5 +1.5 mA Terminal Voltage Range5 GND VDD V Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND, code = half scale, VW = VA = 2.5 V or VW = VB = 2.5 V 20 pF Capacitance W3 CW f = 1 MHz, measured to GND, code = half scale, VA = VB = 2.5 V 35 pF Common-Mode Leakage Current3 VA = VW = VB −500 ±15 +500 nA DIGITAL INPUTS Input Logic3 High VINH VLOGIC = 1.8 V to 2.3 V 0.8 × VLOGIC V VLOGIC = 2.3 V to 5.5 V 0.7 × VLOGIC V Low VINL VLOGIC = 1.8 V to 2.3 V 0.2 × VLOGIC V VLOGIC = 2.3 V to 5.5 V 0.3 × VLOGIC V Input Hysteresis3 VHYST 0.1 × VLOGIC V Input Current3 IN ±1 µA Input Capacitance3 CIN 5 pF DIGITAL OUTPUT (SDA) Output Low Voltage3 VOL ISINK = 3 mA 0.2 V ISINK = 6 mA 0.4 V
Table 3. (Continued) 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB. 3 Guaranteed by design and characterization, not subject to production test. ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
Data Sheet AD5110/AD5112/AD5114 SPECIFICATIONS analog.com Rev. D | 7 of 28 6 Different from operating current; supply current for NVM program lasts approximately 30 ms. 7 Different from operating current; supply current for NVM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V. 10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory. ELECTRICAL CHARACTERISTICS—AD5114 10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 4. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resolution N 5 Bits Resistor Integral Nonlinearity2 R-INL −0.5 +0.5 LSB Resistor Differential Nonlinearity2 R-DNL −0.25 +0.25 LSB Nominal Resistor Tolerance ΔRAB/RAB −8 +8 % Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C Wiper Resistance RW Code = zero scale 70 140 Ω RBS Code = bottom scale 45 80 Ω RTS Code = top scale 70 140 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 INL −0.25 +0.25 LSB Differential Nonlinearity4 DNL −0.25 +0.25 LSB Full-Scale Error VWFSE RAB = 10 kΩ −1 LSB RAB = 80 kΩ −0.5 LSB Zero-Scale Error VWZSE RAB = 10 kΩ 1 LSB RAB = 80 kΩ 0.25 LSB Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 RAB = 10 kΩ −6 +6 mA RAB = 80 kΩ −1.5 +1.5 mA Terminal Voltage Range5 GND VDD V Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND, code = half scale, VW = VA = 2.5 V or VW = VB = 2.5 V 20 pF Capacitance W3 CW f = 1 MHz, measured to GND, code = half scale, VA = VB = 2.5 V 35 pF Common-Mode Leakage Current3 VA = VW = VB −500 ±15 +500 nA DIGITAL INPUTS Input Logic3 High VINH VLOGIC = 1.8 V to 2.3 V 0.8 × VLOGIC V VLOGIC = 2.3 V to 5.5 V 0.7 × VLOGIC V Low VINL VLOGIC = 1.8 V to 2.3 V 0.2 × VLOGIC V VLOGIC = 2.3 V to 5.5 V 0.3 × VLOGIC V Input Hysteresis3 VHYST 0.1 × VLOGIC V Input Current3 IN ±1 µA Input Capacitance3 CIN 5 pF
Table 4. (Continued) 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB. 3 Guaranteed by design and characterization, not subject to production test. ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Different from operating current; supply current for NVM program lasts approximately 30 ms. 7 Different from operating current; supply current for NVM read lasts approximately 20 µs.
Data Sheet AD5110/AD5112/AD5114 SPECIFICATIONS analog.com Rev. D | 9 of 28 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V. 10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory. INTERFACE TIMING SPECIFICATIONS VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter1 Test Conditions/ Comments Min Typ Max Unit Description fSCL2 Standard mode 100 kHz Serial clock frequency Fast mode 400 kHz t1 Standard mode 4.0 µs tHIGH, SCL high time Fast mode 0.6 µs t2 Standard mode 4.7 µs tLOW, SCL low time Fast mode 1.3 µs t3 Standard mode 250 ns tSU;DAT, data setup time Fast mode 100 ns t4 Standard mode 0 3.45 µs tHD;DAT, data hold time Fast mode 0 0.9 µs t5 Standard mode 4.7 µs tSU;STA, setup time for a repeated start condition Fast mode 0.6 µs t6 Standard mode 4 µs tHD;STA, hold time (repeated) start condition Fast mode 0.6 µs t7 Standard mode 4.7 µs tBUF, bus free time between a stop and a start condition Fast mode 1.3 µs t8 Standard mode 4 µs tSU;STO, setup time for stop condition Fast mode 0.6 µs t9 Standard mode 1000 ns tRDA, rise time of SDA signal Fast mode 20 + 0.1 CL 300 ns t10 Standard mode 300 ns tFDA, fall time of SDA signal Fast mode 20 + 0.1 CL 300 ns t11 Standard mode 1000 ns tRCL, rise time of SCL signal Fast mode 20 + 0.1 CL 300 ns t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit. Fast mode 20 + 0.1 CL 300 ns t12 Standard mode 300 ns tFCL, fall time of SCL signal Fast mode 20 + 0.1 CL 300 ns tSP3 Fast mode 0 50 ns Pulse width of suppressed spike tEEPROM_PROGRAM4 15 50 ms Memory program time tPOWER_UP5 50 µs Power-on EEPROM restore time tRESET 25 µs Reset EEPROM restore time 1 Maximum bus capacitance is limited to 400 pF. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode.
TA = 25°C, unless otherwise noted.
1 Maximum terminal current is bounded by the maximum current handling of the
voltage across any two of the A, B, and W terminals at a given resistance. 2 d is the pulse duty factor. 3 Includes programming of EEPROM memory. ing conditions for extended periods may affect product reliability. dependent on the test board and test environment. Table 7. Thermal Resistance 1 JEDEC 2S2P test board, still air (0 m/sec air flow). damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 4. Pin Configuration Table 8. Pin Function Descriptions 2 A Terminal A of RDAC. GND ≤ VA ≤ VDD. 3 W Wiper Terminal of RDAC. GND ≤ VW ≤ VDD. 4 B Terminal B of RDAC. GND ≤ VB ≤ VDD. 5 GND Ground Pin, Logic Ground Reference. 6 SCL Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 16-bit input registers. open-drain data line that should be pulled to the supply with an external pull-up resistor. 8 VLOGIC Logic Power Supply; 1.8 V to VDD. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors. EPAD Exposed Pad. The exposed pad is internally floating.
changes of resistance settings. restriction on the number of changes allowed. the I2C interface (see Table 10). mum resistance between Terminal W and Terminal A or Terminal B. scale, the typical wiper resistance decreases from 70 Ω to 45 Ω. decreased by 1 LSB, and the total resistance is reduced to 70 Ω. INL, DNL, R-INL, and R‑ DNL specifications. for a timing diagram of a typical write sequence. addressing and general call addressing.
- The controller initiates data transfer by establishing a start
be written to, or read from, its shift register.
- If the R/W bit is set high, the controller reads from the target
- Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit). period of SCL and remain stable during the high period of SCL.
- When all data bits have been read or written, a stop condition
during the 10th clock pulse to establish a stop condition. dress options available. See Table 9 for a list of target addresses. Table 9. Device Address Selection that are loaded into the decoded register.
Table 10. Command Operation Truth Table 2 In the AD5114, this bit is a don’t care. 3 In the AD5112, this bit is a don’t care.
Figure 44. AD5110 Interface Multiple Write
can be repeated until it succeeds. using Command 6 (see Table 10). prepared to receive data by pulling SDA low. The AD5110/AD5112/AD5114 do not support repeat readback. Figure 45. AD5110 Interface Read Command
RAB is the end-to-end resistance. RTS is the wiper resistance at top scale. possible destruction of the internal switch contact can occur. Table 11. Tolerance Format Figure 48. Potentiometer Mode Configuration RWB(D) can be obtained from Equation 1 to Equation 6. RAW(D) can be obtained from Equation 7 to Equation 15. internal resistors, RAW and RWB, and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/°C.
Figure 51. 8-Lead Frame Chip Scale Package [LFCSP]
Data Sheet AD5110/AD5112/AD5114 OUTLINE DIMENSIONS ©2011-2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. D | 28 of 28 Model1 RAB (kΩ) Resolution I2C Address AD5110BCPZ80-1-RL7 80 128 0101100 AD5110BCPZ80-500R7 80 128 0101111 AD5110BCPZ80-RL7 80 128 0101111 AD5112BCPZ10-1-RL7 10 64 0101100 AD5112BCPZ10-500R7 10 64 0101111 AD5112BCPZ10-RL7 10 64 0101111 AD5112BCPZ5-1-RL7 5 64 0101100 AD5112BCPZ5-500R7 5 64 0101111 AD5112BCPZ5-RL7 5 64 0101111 AD5112BCPZ80-1-RL7 80 64 0101100 AD5112BCPZ80-500R7 80 64 0101111 AD5112BCPZ80-RL7 80 64 0101111 AD5114BCPZ10-1-RL7 10 32 0101100 AD5114BCPZ10-500R7 10 32 0101111 AD5114BCPZ10-RL7 10 32 0101111 AD5114BCPZ80-1-RL7 80 32 0101100 AD5114BCPZ80-500R7 80 32 0101111 AD5114BCPZ80-RL7 80 32 0101111 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1, 2 Description EVAL-AD5110SDZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The EVAL-AD5110SDZ has an RAB of 10 kΩ. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).