AD5065BRUZ

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Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP AD5025/AD5045/AD5065 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.

FEATURES

Low power dual 12-/14-/16-bit DAC, ±1 LSB INL Individual voltage reference pins Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to zero scale or midscale Power down to 400 nA @ 5 V 3 power-down functions Per channel power-down Low glitch upon power-up Hardware power-down lockout capability Hardware LDAC with software LDAC override function CLR function to programmable code SDO daisy-chaining option 14-lead TSSOP

APPLICATIONS

Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION The AD5025/AD5045/AD5065 are low power, dual 12-/14-/16-bit buffered voltage output nanoDAC® DACs offering relative accuracy specifications of ±1 LSB INL with individual reference pins, and can operate from a single 4.5 V to 5.5 V supply. The AD5025/ AD5045/AD5065 also offer a differential accuracy specification of ±1 LSB. The parts use a versatile 3-wire, low power Schmitt trigger serial interface that operates at clock rates up to 50 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The reference for the AD5025/ AD5045/AD5065 are supplied from an external pin and a refer- ence buffer is provided on chip. The AD5025/AD5045/AD5065 incorporate a power-on reset circuit that ensures the DAC output powers up zero scale or midscale and remains there until a valid write takes place to the device. The AD5025/AD5045/AD5065 contain a power-down feature that reduces the current consump- tion of the device to typically 400 nA at 5 V and provides software selectable output loads while in power-down mode. The parts are put into power-down mode over the serial interface. T otal unad- justed error for the parts is <2.5 mV . The parts exhibit very low glitch on power-up. The outputs of all DACs can be updated simultaneously using the LDAC function, with the added functionality of user-selectable DAC channels to simultaneously update. There is also an asynchronous CLR that clears all DACs to a software-selectable code—0 V , midscale, or full scale. The parts also feature a power-down lockout pin, PDL , which can be used to prevent the DAC from entering power-down under any circumstances over the serial interface. PRODUCT HIGHLIGHTS 1. Dual channel available in a 14-lead TSSOP package with individual voltage reference pins. 2. 12-/14-/16-bit accurate, ±1 LSB INL. 3. Low glitch on power-up. 4. High speed serial interface with clock speeds up to 50 MHz. 5. Three power-down modes available to the user. 6. Reset to known output voltage (zero scale or midscale). 7. Power-down lockout capability. Table 1. Related Devices

Rev. 0 | Page 2 of 28 TABLE OF CONTENTS Using a Reference as a Power Supply for the Using the AD5025/AD5045/AD5065 with a

REVISION HISTORY

10/08—Revision 0: Initial Version

Rev. 0 | Page 3 of 28 SPECIFICATIONS VDD = 4.5 V to 5.5 V , RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD, unless otherwise specified. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter B Grade1 A Grade1, 2 Unit Conditions/Comments Min Typ Max Min Typ Max STATIC PERFORMANCE3 Resolution AD5065 16 16 Bits AD5045 14 AD5025 12 Relative Accuracy AD5065 ±0.4 ±1 ±0.5 ±4 LSB T A = −40°C to +105°C AD5065 +0.4 ±2 ±0.5 ±4 T A = −40°C to +125°C AD5045 ±0.1 ±0.5 LSB TA = −40°C to +105°C AD5045 ±0.1 ±1 TA = −40°C to +125°C AD5025 ±0.05 ±0.25 LSB TA = −40°C to +105°C AD5025 ±0.05 ±0.5 T A = −40°C to +125°C Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Offset Error ±0.2 ±1.8 ±0.2 ±1.8 mV Code 512 (AD5065), Code 128 (AD5045), Code 32 (AD5025) loaded to DAC register Offset Error Drift4 ±2 ±2 μV/°C Full-Scale Error ±0.01 ±0.07 ±0.01 ±0.07 % FSR All 1s loaded to DAC register, VREF < VDD Gain Error ±0.005 ±0.05 ±0.005 ±0.05 % FSR Gain Temperature Coefficient4 ±1 ±1 ppm Of FSR/°C DC Crosstalk4 40 40 μV Due to single channel full-scale output change, RL = 5 kΩ to GND or VDD 40 40 μV/mA Due to load current change 40 40 μV Due to powering down (per channel) OUTPUT CHARACTERISTICS4 Output Voltage Range 0 V DD 0 V DD V Capacitive Load Stability 1 1 nF R L = 5 kΩ, RL = 100 kΩ, and RL = ∞ DC Output Impedance Normal Mode 0.5 0.5 Ω Power-Down Mode Output Connected to 100 kΩ Network 100 100 kΩ Output impedance tolerance ± 400 Ω Output Connected to 1 kΩ Network 1 1 kΩ Output impedance tolerance ± 20 Ω Short-Circuit Current 60 60 mA DAC = full scale, output shorted to GND 45 45 mA DAC = zero-scale, output shorted to V DD Power-Up Time 4.5 4.5 μs Time to exit power-down mode to normal mode of AD5024/AD5044/ AD5064, 32nd clock edge to 90% of DAC midscale value, output unloaded DC PSRR −92 −92 dB V DD ± 10%, DAC = full scale, VREF < VDD REFERENCE INPUTS Reference Input Range 2.2 V DD 2.2 V DD V Reference Current 35 50 35 50 μA Per DAC channel Reference Input Impedance 120 120 kΩ

Rev. 0 | Page 4 of 28 Parameter B Grade1 A Grade1, 2 Unit Conditions/Comments Min Typ Max Min Typ Max LOGIC INPUTS Input Current5 ±1 ±1 μA Input Low Voltage, VINL 0.8 0.8 V Input High Voltage, VINH 2.2 2.2 V Pin Capacitance4 4 4 pF LOGIC OUTPUTS (SDO)3, 4 Output Low Voltage, VOL 0.4 0.4 V I SINK = 2 mA Output High Voltage, VOH V DD − 1 V DD − 1 I SOURCE = 2 mA High Impedance Leakage Current4 High Impedance Output Capacitance 7 7 pF POWER REQUIREMENTS VDD 4.5 5.5 4.5 5.5 V IDD6 DAC active, excludes load current Normal Mode 2.2 2.7 2.2 2.7 mA V IH = VDD and VIL = GND All Power-Down Modes7 0.4 2 0.4 2 μA T A = −40°C to +105°C 30 30 μA T A = −40°C to +125°C 1 Temperature range is −40°C to +125°C, typical at 25°C. 2 A grade offered in AD5065 only. 3 Linearity calculated using a reduced code range—AD5065: Code 512 to Code 65,024; AD5045: Code 128 to Code 16,256; AD5025: Code 32 to Code 4064. Output unloaded. 4 Guaranteed by design and characterization; not production tested. 5 Current flowing into or out of individual digital pins. 6 Interface inactive. All DACs active. DAC outputs unloaded. 7 Both DACs powered down. AC CHARACTERISTICS Table 3. Parameter1 Min Typ Max Unit Conditions/Comments2 Output Voltage Settling Time 5.8 8 μs ¼ to ¾ scale settling to ±1 LSB, RL = 5 kΩ single-channel update including DAC calibration sequence Output Voltage Settling Time 10.7 13 μs ¼ to ¾ scale settling to ±1 LSB, RL = 5 kΩ all channel update including DAC calibration sequence Slew Rate 1.5 V/μs Digital-to-Analog Glitch Impulse3 4 nV-sec 1 LSB change around major carry Reference Feedthrough3 −90 dB V REF = 3 V ± 0.86 V p-p, frequency = 100 Hz to 100 kHz SDO Feedthrough 0.07 nV-sec Daisy-chain mode; SDO load is 10 pF Digital Feedthrough3 0.1 nV-sec Digital Crosstalk3 1.9 nV-sec Analog Crosstalk3 1.2 nV-sec DAC-to-DAC Crosstalk3 2.1 nV-sec Multiplying Bandwidth3 340 kHz V REF = 3 V ± 0.86 V p-p Total Harmonic Distortion3 −80 dB V REF = 3 V ± 0.86 V p-p, frequency = 10 kHz Output Noise Spectral Density 64 nV/√Hz DAC code = 0x8400, 1 kHz 60 nV/√Hz DAC code = 0x8400, 10 kHz Output Noise 6 μV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization; not production tested. 2 Temperature range is −40°C to + 125°C, typical at 25°C. 3 See the Terminology section.

Rev. 0 | Page 7 of 28 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter Rating VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V VOUTA or VOUTB to GND −0.3 V to VDD + 0.3 V VREFA or VREFB to GND −0.3 V to VDD + 0.3 V Operating Temperature Range, Industrial −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ MAX) 150°C Power Dissipation (TJ MAX − TA)/θJA θJA Thermal Impedance 150.4°C/W Reflow Soldering Peak Temperature SnPb 240°C Pb-Free 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 5. Pin Configuration Table 6. Pin Function Descriptions high after pulsing. This allows all DAC outputs to simultaneously update. SYNC acts as an interrupt and the write sequence is ignored by the device. with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 4 V REFA DAC A Reference Input. This is the reference voltage input pin for DAC A. 5 V OUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. edge of SCLK and is valid on the falling edge of the clock. contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 9 V REFB DAC B Reference Input. This is the reference voltage input pin for DAC B. 10 V OUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 11 GND Ground Reference Point for All Circuitry on the Part. software power-down over the serial interface while Logic 1 is applied to the PDL pin. the previous code in the DAC register before the device entered software power-down. edge of the serial clock input. can be transferred at rates of up to 50 MHz.

Rev. 0 | Page 15 of 28 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. Figure 6, Figure 7, and Figure 8 show plots of typical INL vs. code. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed mono- tonic by design. Figure 9, Figure 10, and Figure 11 show plots of typical DNL vs. code. Offset Error Offset error is a measure of the difference between the actual V OUT and the ideal VOUT, expressed in millivolts in the linear region of the transfer function. Offset error is measured on the part with Code 512 (AD5065), Code 128 (AD5045), and Code 32 (AD5025) loaded into the DAC register. It can be negative or positive and is expressed in millivolts. Offset Error Drift Offset error drift is a measure of the change in offset error with a change in temperature. It is expressed in microvolts per degree Celsius. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. Gain Temperature Coefficient Gain error drift is a measure of the change in gain error with changes in temperature. It is expressed in parts per million of full-scale range per degree Celsius. Measured with V REF < VDD. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be V DD − 1 LSB. Full-scale error is expressed as a percentage of the full-scale range. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nanovolt- seconds and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 25. DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V OUT to a change in VDD for full-scale output of the DAC. It is measured in decibels. VREF is held at 2.5 V , and VDD is varied ±10%. Measured with VREF < VDD. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in microvolts. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in microvolts per milliamp. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (that is, LDAC is high). It is expressed in decibels. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device but is measured when the DAC is not being written to (SYNC held high). It is specified in nanovolt-seconds. It is measured with one simultaneous data and clock pulse loaded to the DAC. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nanovolt-seconds.

Rev. 0 | Page 16 of 28 Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s or vice versa) while keeping LDAC high, and then pulsing LDAC low and monitoring the output of the DAC whose digital code has not changed. The area of the glitch is expressed in nanovolt-seconds. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nanovolt-seconds. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) Total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels.

current consumption to typically 400 nA. the DAC register (0 to 65,535 for the 16-bit AD5065).

15 EQUAL SEGMENTS

Figure 40. DAC Ladder Structure The AD5025/AD5045/AD5065 operate with an external reference. buffered reference for the DAC core. to ¾ scale settling time of 13 μs. Figure 3 for a timing diagram of a typical write sequence. Table 7. Address Commands Table 8. Command Definitions

must be brought high again just before the next write sequence. 32nd falling edge, this acts as an interrupt to the write sequence. The input register is reset, and the write sequence is seen as invalid. the operating mode occurs (see Figure 44). mode is enabled by setting a bit (DB1) in the DCEN register. The default setting is standalone mode, where DB1 = 0. Table 9. DCEN (Daisy-Chain Enable) Register

0 X Standalone mode (default)

1 X DCEN mode

where N is the total number of devices in the chain. part, it is considered an invalid frame and the data is discarded. and SYNC must be taken high after the final clock to latch the data. Figure 44. SYNC Interrupt Facility Table 10. 32-Bit Input Register Contents for Daisy-Chain Enable

for this reset function (see Table 8). to the mode of operation of the device. Table 11. Modes of Operation the output of the amplifier to a resistor network of known values. circuited (three-state). The output stage is illustrated in Figure 45. Figure 45. Output Stage During Power-Down during power-down/power-up operation. DAC register before powering down (LDAC high). Table 12. 32-Bit Input Register Contents for Power-Up/Power-Down Function

to load zero scale, midscale, or full scale to all channels together. bits, Bit DB1 and Bit DB0, in the input register (see Table 13). reserved for loading the clear code register (see Table 8). Table 13. Clear Code Register the output starts to change, is typically 10.6 μs (see Figure 31). loading clear code register operation. synchronous or asynchronous mode, as shown in Figure 3. with the contents of the input register. Register n (see Table 7) and updating all DAC registers. Command 0010 is reserved for this software LDAC function. this channel update is controlled by the hardware LDAC pin. If DB0 or DB3 is set to 1, this channel updates synchronously. low (see Table 15 for the LDAC register mode of operation). channels are synchronously updating. Table 14. 32-Bit Input Register Contents for Clear Code Function Table 15. LDAC Overwrite Definitions 0 1, 0 Determined by LDAC pin. 1 X 1 DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0. Table 16. 32-Bit Input Register Contents for LDAC Overwrite Function

Rev. 0 | Page 22 of 28 POWER-DOWN LOCKOUT The AD5025/AD5045/AD5065 contain a digital input pin, PDL. When activated, the power-down lockout pin (PDL) disables software shutdown under any circumstances. The user should hardwire the PDL pin to a logic low (thus preventing subsequent software power-down) or logic high (the part can be placed in power-down mode over the serial interface). If the user transitions the PDL pin from logic high to a logic low during a valid write sequence, the device responds immediately and the current write sequence is aborted. Note the following PDL features. PDL During a Write Sequence If a PDL is generated (that is, a high-to-low transition) while a valid write sequence is ongoing, the write is aborted. The user must rewrite the current write command again. PDL While DACs in Power-Down Mode If a PDL is generated while the DAC(s) are in power-down mode, the DAC(s) come out of power-down (that is, all power- down bits are reset to 0000) to the last voltage output correspond- ing to the last valid stored DAC value. While PDL remains active, software power-down is disabled. PDL Low to High Transition After PDL is taken from a low to a high state, all DAC channels remain in normal mode, and the user must reissue a software power-down command to the control register to power down the required channels. Transitioning PDL from a low to a high disables the feature immediately. If PDL and CLR are generated at the same time, the CLR signal causes the DAC register to change as per the clear code register, and the DACs come out of power-down. If PDL, CLR, and LDAC are generated at the same time, CLR has higher precedence over LDAC and PDL. The user is recommended to hardwire the pin to a logic high or low, thereby either enabling or disabling the feature. POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board (PCB) containing the AD5025/AD5045/ AD5065 should have separate analog and digital sections. If the AD5025/AD5045/AD5065 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5025/AD5045/AD5065. Bypass the power supply to the AD5025/AD5045/AD5065 with 10 μF and 0.1 μF capacitors. The capacitors should physically be as close as possible to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitors are the tantalum bead type. It is important that the 0.1 μF capacitor has low effective series resistance (ESR) and low effective series inductance (ESI), which is typical of common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Shield clocks and other fast switching digital signals from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.

Figure 53. 14-Lead Thin Shrink Small Outline Package [TSSOP]

Rev. 0 | Page 26 of 28 NOTES

Rev. 0 | Page 27 of 28 NOTES

Rev. 0 | Page 28 of 28 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D06844-0-10/08(0)