AD5064BRUZ

AD5024 AD | Alldatasheet

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Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP AD5024/AD5044/AD5064 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.

FEATURES

Low power quad 12-/14-/16-bit DAC, ±1 LSB INL Individual and common voltage reference pin options Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to zero-scale or midscale 3 power-down functions Per-channel power-down Low glitch on power-up Hardware LDAC with LDAC override function CLR function to programmable code 16-lead TSSOP Internal reference buffer and internal output amplifier

APPLICATIONS

Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Table 1. Related Devices software selectable output loads while in power-down mode. Total unadjusted error for the parts is <2 mV .

1. Quad channel available in 16-lead TSSOP package.
2. 16-bit accurate, 1 LSB INL.
3. High speed serial interface with clock speeds up to 50 MHz.

AD5063/AD5062 5. Reset to known output voltage (zero scale or midscale).

Rev. 0 | Page 2 of 28 TABLE OF CONTENTS Using the AD5024/AD5044/AD5064 with a

REVISION HISTORY

8/08—Revision 0: Initial Version

Rev. 0 | Page 3 of 28 SPECIFICATIONS VDD = 4.5 V to 5.5 V , RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD, unless otherwise specified. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter B Grade1 A Grade1, 2 Unit Conditions/Comments Min Typ Max Min Typ Max STATIC PERFORMANCE3 Resolution 16 16 Bits AD5064

14 AD5044

12 AD5024

Relative Accuracy ±0.5 ±1 ±0.5 ±4 LSB AD5064; TA = −40°C to +105°C ±0.25 ±0.5 LSB AD5044; TA = −40°C to +105°C ±0.25 ±1 AD5044; TA = −40°C to +125°C ±0.12 ±0.25 LSB AD5024; TA = −40°C to +105°C Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Offset Error ±0.2 ±1.8 ±0.2 ±1.8 mV Code 512 (AD5064), Code 128 (AD5044), Code 32 (AD5024) loaded to DAC register Offset Error Drift4 ±2 ±2 μV/°C Gain Error ±0.005 ±0.05 ±0.005 ±0.05 % FSR Gain Temperature Coefficient4 ±1 ±1 ppm Of FSR/°C DC Crosstalk 40 40 μV Due to single channel full-scale output change, RL = 5 kΩ to GND or VDD 40 40 μV/mA Due to load current change 0.5 40 μV Due to powering down (per channel) OUTPUT CHARACTERISTICS4 Output Voltage Range 0 VDD 0 VDD V Capacitive Load Stability 1 1 nF RL = 5 kΩ, RL =100 kΩ, and RL = ∞ DC Output Impedance Normal Mode 0.5 0.5 Ω Power-Down Mode Output Connected to 100 kΩ Network 100 100 kΩ Output impedance tolerance ± 400 Ω Output Connected to 1 kΩ Network 1 1 kΩ Output impedance tolerance ± 20 Ω Short-Circuit Current 60 60 mA DAC = full scale, output shorted to GND 45 45 mA DAC = zero-scale, output shorted to VDD Power-Up Time 4.5 4.5 μs Time to exit power-down mode to normal mode of AD5024/AD5044/AD5064, 32 nd clock edge to 90% of DAC midscale value, output unloaded DC PSRR −92 −92 dB VDD ± 10%, DAC = full scale. VREF < VDD REFERENCE INPUTS Reference Input Range 2.5 VDD 2.5 VDD V Reference Current 35 50 35 50 μA Per DAC channel Reference Input Impedance 120 120 kΩ Individual reference option LOGIC INPUTS Input Current5 ±1 ±1 μA Input Low Voltage, VINL 0.8 0.8 V Input High Voltage, VINH 2.2 2.2 V Pin Capacitance4 4 4 pF

Rev. 0 | Page 4 of 28 Parameter B Grade1 A Grade1, 2 Unit Conditions/Comments Min Typ Max Min Typ Max POWER REQUIREMENTS VDD 4.5 5.5 4.5 5.5 V DAC active, excludes load current IDD6 VIH = VDD and VIL = GND Normal Mode 3 6 3 6 mA All Power-Down Modes7 0.4 2 0.4 2 μA TA = −40°C to +105°C 30 30 μA TA = −40°C to +125°C 1 Temperature range is −40°C to +125°C, typical at 25°C. 2 A grade offered in AD5064 only. 3 Linearity calculated using a reduced code range—AD5064: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064. Output unloaded. 4 Guaranteed by design and characterization; not production tested. 5 Current flowing into individual digital pins. 6 Interface inactive. All DACs active. DAC outputs unloaded. 7 All four DACs powered down.

Rev. 0 | Page 5 of 28 AC CHARACTERISTICS VDD = 4.5 V to 5.5 V , RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2 Min Typ Max Unit Conditions/Comments3 Output Voltage Settling Time 5.8 8 μs ¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ, single channel update including DAC calibration sequence 10.7 13 μs ¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ, all channel update including DAC calibration sequence Slew Rate 1.5 V/μs Digital-to-Analog Glitch Impulse 3 nV-s 1 LSB change around major carry Reference Feedthrough −90 dB VREF = 3 V ± 0.86 V p-p, frequency = 100 Hz to 100 kHz Digital Feedthrough 0.1 nV-s Digital Crosstalk 1.9 nV-s Analog Crosstalk 2 nV-s DAC-to-DAC Crosstalk 3.5 nV-s AC Crosstalk 6 nV-s Multiplying Bandwidth 340 kHz VREF = 3 V ± 0.86 V p-p Total Harmonic Distortion −80 dB VREF = 3 V ± 0.2 V p-p, frequency = 10 kHz Output Noise Spectral Density 64 nV/√Hz DAC code = 0x8400, 1 kHz 60 nV/√Hz DAC code = 0x8400, 10 kHz Output Noise 6 μV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +125°C, typical at 25°C.

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 4.5 V to 5.5 V . All specifications TMIN to TMAX, unless otherwise noted. 1 Guaranteed by design and characterization; not production tested. 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. Figure 2. Serial Write Operation

Rev. 0 | Page 7 of 28 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter Rating VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V VOUT to GND −0.3 V to VDD + 0.3 V VREF to GND −0.3 V to VDD + 0.3 V Operating Temperature Range Industrial −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ MAX) 150°C Power Dissipation (TJ MAX − TA)/θJA θJA Thermal Impedance 113°C/W Reflow Soldering Peak Temperature Pb Free 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 3. 16-Lead TSSOP (RU-16) Pin Configuration Table 6. Pin Function Descriptions allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low. of SYNC acts as an interrupt and the write sequence is ignored by the device. with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 4 V REFB DAC B Reference Input. This is the reference voltage input pin for DAC B. 5 V REFA DAC A Reference Input. This is the reference voltage input pin for DAC A. 6 V OUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 7 V OUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 9 V REFC DAC C Reference Input .This is the reference voltage input pin for DAC C. contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 11 V REFD DAC D Reference Input .This is the reference voltage input pin for DAC D. 12 V OUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 13 V OUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 14 GND Ground Reference Point for All Circuitry on the Part. edge of the serial clock input. 16 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz.

Figure 40. Glitch on Exiting Power-Down from Zero Scale, No load Figure 41. Glitch on Exiting Power-Down from Zero Scale,

Rev. 0 | Page 17 of 28 DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nanovolt-seconds. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) Total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels.

typical current consumption to less than 2 μA. the DAC register (0 to 65,535 for the 16-bit AD5064). DAC sections. A simplified circuit diagram is shown in Figure 42. of a 12-bit voltage mode R-2R ladder network.

15 EQUAL SEGMENTS

Figure 42. DAC Ladder Structure The AD5024/AD5044/AD5064 operate with an external reference. is then used to provide a buffered reference for the DAC core. must be brought high again just before the next write sequence. Table 7. Command Definitions Table 8. Address Commands

during power-on reset are ignored. setting the corresponding four bits (DB3, DB2, DB1, DB0) to 1. power-down/power-up operation. the output of the amplifier to a resistor network of known values. circuited (three-state). The output stage is illustrated in Figure 47. Table 9. Modes of Operation Table 10. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function Figure 47. Output Stage During Power-Down

Rev. 0 | Page 21 of 28 CLEAR CODE REGISTER The AD5024/AD5044/AD5064 have a hardware CLR pin that is an asynchronous clear input. The CLR input is falling edge sensitive. Bringing the CLR line low clears the contents of the input register and the DAC registers to the data contained in the user-configurable CLR register and sets the analog outputs accordingly (see ). This function can be used in system calibration to load zero scale, midscale, or full scale to all channels together. Note that zero scale and full scale are outside the linear region of the DAC. These clear code values are user-programmable by setting two bits, Bit DB1 and Bit DB0, in the control register (see ). The default setting clears the outputs to 0 V . Command 0101 is designated for loading the clear code register (see ). Table 11 Table 11 Table 7 The part exits clear code mode on the 32 nd falling edge of the next write to the part. If CLR is activated during a write sequence, the write is aborted. The CLR pulse activation time, which is the falling edge of CLR to when the output starts to change, is typically 10.6 μs. If outside the DAC linear region, it typically takes 10.6 μs after executing CLR for the output to start changing (see ). Figure 33 See Table 12 for contents of the input shift register during the loading clear code register operation. LDAC FUNCTION Hardware LDAC Pin The outputs of all DACs can be updated simultaneously using the hardware LDAC pin, as shown in . Figure 2 Synchronous LDAC: After new data is read, the DAC registers are updated on the falling edge of the 32nd SCLK pulse. LDAC can be permanently low or pulsed. Asynchronous LDAC: The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register. Software LDAC Function Alternatively, the outputs of all DACs can be updated simulta- neously using the software LDAC function by writing to Input Register n and updating all DAC registers. Command 0010 is reserved for this software LDAC function. The LDAC register gives the user extra flexibility and control over the hardware LDAC pin (see ). Setting the Table 14 LDAC bit register (DB0 to DB3) to 0 for a DAC channel means that this channel’s update is controlled by the hardware LDAC pin. If this bit is set to 1, this channel updates synchronously; that is, the DAC register is updated after new data is read, regardless of the state of the hardware LDAC pin. It effectively sees the hardware LDAC pin as being tied low. (See for the Table 13 LDAC register mode of operation.) This flexibility is useful in applications where the user wants to simul- taneously update select channels while the rest of the channels are synchronously updating. Writing to the DAC using Command 0110 loads the 4-bit LDAC register (DB3 to DB0). The default for each channel is 0; that is, the LDAC pin works normally. Setting the bits to 1 means that the DAC channel is updated regardless of the state of the LDAC pin. POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5024/AD5044/ AD5064 should have separate analog and digital sections. If the AD5024/AD5044/AD5064 is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5024/AD5044/AD5064. The power supply to the AD5024/AD5044/AD5064 should be bypassed with 10 μF and 0.1 μF capacitors. The capacitors should physically be as close as possible to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitors are the tantalum bead type. It is important that the 0.1 μF capacitor have low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip tech- nique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.

Table 11. Clear Code Register Table 12. 32-Bit Input Shift Register Contents for Clear Code Function Table 13. LDAC Overwrite Definition 1 X—don’t care DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0. Table 14. 32-Bit Input Shift Register Contents for LDAC Overwrite Function

Figure 55. 16-Lead Thin Shrink Small Outline Package [TSSOP]

Rev. 0 | Page 26 of 28 NOTES

Rev. 0 | Page 27 of 28 NOTES

Rev. 0 | Page 28 of 28 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D06803-0-8/08(0)