AD5063

AD5063 (Rev. D)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 18

Technical content

Fully Accurate 16-Bit VOUT nanoDAC SPI Interface 2.7 V to 5.5 V in an MSOP Data Sheet AD5063 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Single 16-bit DAC, 1 LSB INL Power-on reset to midscale Guaranteed monotonic by design 3 power-down functions Low power serial interface with Schmitt-triggered inputs 10-lead MSOP , low power Fast settling time of 1 µs maximum (AD5063-1 model) 2.7 V to 5.5 V power supply Low glitch on power-up Unbuffered voltage capable of driving 60 kΩ load SYNC interrupt facility

APPLICATIONS

Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators FUNCTIONAL BLOCK DIAGRAM AD5063 VDD VOUT VREF POWER-ON RESET DAC REGISTER DAC INPUT CONTROL LOGIC POWER-DOWN CONTROL LOGIC RESISTOR NETWORK REF(+) SCLK DIN 04766-001 SYNC DACGND BUF AGND RFB INV Figure 1. GENERAL DESCRIPTION The AD5063, a member of the Analog Device Inc., nanoDAC™ family, is a low power, single 16-bit, unbuffered voltage-output DAC that operates from a single 2.7 V to 5 V supply. The device offers a relative accuracy specification of ±1 LSB, and operation is guaranteed monotonic with a ±1 LSB DNL specification. The AD5063 comes with on-board resistors in a 10-lead MSOP , allowing bipolar signals to be generated with an output amplifier. The device uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and that is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The reference for the AD5063 is supplied from an external V REF pin. A reference buffer is also provided on-chip. The device incorporates a power-on reset circuit that ensures the DAC output powers up to midscale and remains there until a valid write to the device takes place. The device contains a power-down feature that reduces the current consumption of the device to typically 300 nA at 5 V and provides software- selectable output loads while in power-down mode. The device is put into power-down mode via the serial interface. Total unadjusted error for the device i s < 1 m V. This device exhibits very low glitch on power-up. PRODUCT HIGHLIGHTS 1. Available in 10-lead MSOP . 2. 16-bit accurate, 1 LSB INL. 3. Low glitch on power-up. 4. High speed serial interface with clock speeds up to 30 MHz. 5. Three power-down modes available to the user. Table 1. Related Devices

Rev. D | Page 2 of 18 TABLE OF CONTENTS Using the AD5063 with a Galvanically Isolated Interface

REVISION HISTORY

4/2018—Rev. C to Rev. D Changed Application Section to Applications Information Changes to Bipolar Operation Using the AD5063 Section and 8/2009—Rev. B to Rev. C Changes to Output Voltage Settling Time Parameter, Table 2 ... 3 3/2006—Rev. A to Rev. B 7/2005—Rev. 0 to Rev. A 4/2005—Revision 0: Initial Version

Rev. D | Page 3 of 18 SPECIFICATIONS Table 2. B Version1 Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 16 Bits Relative Accuracy (INL) ±0.5 ±1 LSB −40°C to + 85°C, B grade over all codes Total Unadjusted Error (TUE) ±500 ±800 µV Differential Nonlinearity (DNL) ±0.5 ±1 LSB Guaranteed monotonic Gain Error ±0.01 ±0.02 % FSR TA = −40°C to +85°C Gain Error Temperature Coefficient 1 ppm FSR/°C Zero-Code Error ±0.05 ±0.1 mV All 0s loaded to DAC register, TA = −40°C to +85°C Zero-Code Error Temperature Coefficient 0.05 µV/°C Offset Error ±0.05 ±0.1 mV TA = −40°C to +85°C Offset Error Temperature Coefficient 0.5 µV/°C Full-Scale Error ±500 ±800 µV All 1s loaded to DAC register, TA = −40°C to +85°C Bipolar Resistor Matching 1 Ω/Ω RFB/RINV, RFB = RINV = 30 kΩ typically Bipolar Zero Offset Error ±8 ±16 LSB Bipolar Zero Temperature Coefficient ±0.5 ppm FSR/°C Bipolar Gain Error ±16 ±32 LSB OUTPUT CHARACTERISTICS2 Output Voltage Range 0 VREF V Unipolar operation −VREF VREF V Bipolar operation Output Voltage Settling Time3 ¼ scale to ¾ scale code transition to ±1 LSB AD5063BRMZ 4 µs AD5063BRMZ-1 1 µs VDD = 4.5 V to 5.5 V 4 µs VDD = 2.7 V to 5.5 V Output Noise Spectral Density 64 nV/√Hz DAC code = midscale, 1 kHz Output Voltage Noise 6 µV p-p DAC code = midscale, 0.1 Hz to 10 Hz bandwidth Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry Digital Feedthrough 0.002 nV-s DC Output Impedance (Normal) 8 kΩ Output impedance tolerance ±10% DC Output Impedance (Power-Down) (Output Connected to 1 kΩ Network) 1 kΩ Output impedance tolerance ±400 Ω (Output Connected to 10 kΩ Network) 100 kΩ Output impedance tolerance ±20 kΩ REFERENCE INPUT/OUPUT VREF Input Range 2 VDD − 50 mV Input Current (Power-Down) ±1 µA Zero-scale loaded Input Current (Normal) ±1 µA DC Input Impedance 1 MΩ Bipolar/unipolar operation LOGIC INPUTS Input Current4 ±1 ±2 µA Input Low Voltage, VIL 0.8 V VDD = 4.5 V to 5.5 V 0.8 VDD = 2.7 V to 3.6 V Input High Voltage, VIH 2.0 V VDD = 2.7 V to 5.5 V 1.8 VDD = 2.7 V to 3.6 V Pin Capacitance 4 pF

Rev. D | Page 4 of 18 B Version1 Parameter Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS VDD 2.7 5.5 V All digital inputs at 0 V or VDD IDD (Normal Mode) DAC active and excluding load current VDD = 4.5 V to 5.5 V 0.65 0.7 mA VIN = VDD and VIL = GND, VDD = 5 V, VREF = 4.096 V, code = midscale VDD = 2.7 V to 3.6 V 0.5 mA VIH = VDD and VIL = GND, VDD = 3 V IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V 1 µA VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 1 µA VIH = VDD and VIL = GND Power Supply Rejection Ratio (PSRR) 0.5 LSB ∆VDD ± 10%, VDD = 5 V, unloaded 1 Temperature ranges for the B version: −40°C to +85°C, typical at +25°C, functional to +125°C. 2 Guaranteed by design and characterization, not production tested. 3 See the Ordering Guide. 4 Total current flowing into all pins.

VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency is 30 MHz. Figure 2. Timing Diagram

Rev. D | Page 6 of 18 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating VDD to GND −0.3 V to +7.0 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V VOUT to GND −0.3 V to VDD + 0.3 V VREF to GND −0.3 V to VDD + 0.3 V INV to GND −0.3 V to VDD + 0.3 V RFB to GND +7 V to −7 V Operating Temperature Range Industrial (B Version) −40°C to + 85°C1 Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Power Dissipation (TJ max − TA)/θJA θJA Thermal Impedance 206°C/W θJc Thermal Impedance 44°C/W Reflow Soldering (Pb-Free) Peak Temperature 260(0/−5)°C Time at Peak Temperature 10 sec to 40 sec ESD 1.5 kV

1 Temperature range for this device is −40°C to +85°C; however, the device is

still operational at 125°C. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.} This device is a high performance integrated circuit with an ESD rating of <2 kV , and it is ESD sensitive. Take proper precautions for handling and assembly. ESD CAUTION

Figure 3. Pin Configuration Table 5. Pin Function Descriptions 3 VREF Reference Voltage Input. 4 VOUT Analog Output Voltage from DAC. 6 RFB Feedback Resistor. In bipolar mode, connect this pin to the external op amp circuit. 7 AGND Ground Reference Point for Analog Circuitry. 8 DACGND Ground Input to the DAC. which case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. can be transferred at rates of up to 30 MHz.

Rev. D | Page 12 of 18 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. A typical INL error vs. code plot is shown in Figure 4. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL error vs. code plot is shown in Figure 7. Zero-Code Error Zero-code error is a measure of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output is 0 V . The zero-code error is always positive in the AD5063 because the output of the DAC cannot go below 0 V . This is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV . Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded to the DAC register. Ideally, the output is V DD − 1 LSB. Full-scale error is expressed as a percentage of the full-scale range. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal, expressed as a percentage of the full-scale range. Tot a l Una dju ste d E r ror ( T UE ) Total unadjusted error is a measure of the output error, taking all the various errors into account. A typical TUE vs. code plot is shown in Figure 5. Zero-Code Error Drift Zero-code error drift is a measure of the change in zero-code error with a change in temperature. It is expressed in μV/°C. Gain Error Drift Gain error drift is a measure of the change in gain error with a change in temperature. It is expressed in (ppm of full-scale range)/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. See Figure 17 and Figure 21. Figure 17 shows the glitch generated following completion of the calibration routine; Figure 21 zooms in on this glitch. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa.

The AD5063 is a single 16-bit, serial input, voltage-output DAC. the AD5063 in a 24-bit word format via a 3-wire serial interface. consumption to less than 1 μA. Figure 27. The four MSBs of the 16-bit data-word are decoded

15 EQUAL SEGMENTS

Figure 27. DAC Ladder Structure input voltage provides a buffered reference for the DAC core. (normal mode or any one of the three power-down modes). 24th falling edge, it acts as an interrupt to the write sequence. change in the operating mode occurs (see Figure 31).

000000 P D 1 P D 0

Figure 28. Input Register Contents

the reference is reflected in the DAC. any point within the operating temperature range to trim out error. performance at 8 µV p-p in the 0.1 Hz to 10 Hz range. Figure 36. ADR395 as a Reference to AD5063 supply to the AD5063 are shown in Table 7. Table 7. Recommended Precision References for the AD5063

0.1 Hz to 10 Hz

Figure 37. This circuit yields an output voltage range of ±4.096 V. where D represents the input code in decimal (0 to 65,536). Figure 37. Bipolar Operation

0.50 BSC

1.10 MAX

Figure 39. 10-Lead Mini Small Outline Package [MSOP] registered trademarks are the property of their respective owners.