AD5060YRJZ-1REEL7

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Fully Accurate 14-/16-Bit VOUT nanoDAC™ SPI Interface 2.7 V to 5.5 V, in an SOT-23 AD5040/AD5060 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005-2010 Analog Devices, Inc. All rights reserved.

FEATURES

Single 14-/16-bit DAC, 1 LSB INL Power-on reset to midscale or zero scale Guaranteed monotonic by design 3 power-down functions Low power serial interface with Schmitt-triggered inputs Small 8-lead SOT-23 package, low power Fast settling time of 4 μs typically 2.7 V to 5.5 V power supply Low glitch on power-up SYNC interrupt facility

APPLICATIONS

Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION The AD5040 and the AD5060, members of the ADI nanoDAC family, are low power, single 14-/16-bit buffered voltage-out DACs that operate from a single 2.7 V to 5.5 V supply. The AD5040/AD5060 parts offer a relative accuracy specification of ±1 LSB and operation are guaranteed monotonic with a ±1 LSB DNL specification. The parts use a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The reference for both the AD5040 and AD5060 is supplied from an external V REF pin. A reference buffer is also provided on-chip. The AD5060 incorporates a power-on reset circuit that ensures the DAC output powers up to midscale or zero scale and remains there until a valid write takes place to the device. The AD5040 and the AD5060 both contain a power-down feature that reduces the current con- sumption of the device to typically 330 nA at 5 V and provides software-selectable output loads while in power-down mode. The parts are put into power-down mode over the serial interface. Total unadjusted error for the parts is <2 mV . Both parts exhibit very low glitch on power-up. FUNCTIONAL BLOCK DIAGRAM AD5040/ AD5060 VDD VOUT VREF POWER-ON RESET DAC REGISTER DAC INPUT CONTROL LOGIC POWER-DOWN CONTROL LOGIC RESISTOR NETWORK REF(+) SCLK DIN 04767-001 SYNC DACGND BUF AGND OUTPUT BUFFER Figure 1. PRODUCT HIGHLIGHTS 1. Available in a small, 8-lead SOT-23 package. 2. 14-/16-bit accurate, 1 LSB INL. 3. Low glitch on power-up. 4. High speed serial interface with clock speeds up to 30 MHz. 5. Three power-down modes available to the user. 6. Reset to known output voltage (midscale, zero scale). Table 1. Related Devices

Rev. A | Page 2 of 24 TABLE OF CONTENTS Using the AD5040/AD5060 with a Galvanically Isolated

REVISION HISTORY

1/10—Rev. 0 to Rev. A Changes to Table 2, Relative Accuracy (INL) and Endnote 1 .... 3 10/05—Revision 0: Initial Version

Rev. A | Page 3 of 24 SPECIFICATIONS VDD = 5.5 V , VREF = 4.096 V @ RL = unloaded, CL = unloaded; TMIN to TMAX, unless otherwise noted. Table 2. A, B, and Y Grades1 Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 16 Bits AD5060

14 Bits AD5040

Relative Accuracy (INL)2 ±0.5 ±2 LSB −40°C to +85°C, AD5040/AD5060 A grade ±0.5 ±1 LSB −40°C to +85°C, AD5040/AD5060 B grade ±0.5 ±1.5 −40°C to +125°C, AD5060 Y grade Total Unadjusted Error (TUE)2 ±0.1 ±2.0 mV −40°C to +85°C, AD5040/AD5060 ±0.1 ±2.0 −40°C to +125°C, AD5060 Y grade Differential Nonlinearity (DNL)2 ±0.5 ±1 LSB Guaranteed monotonic, −40°C to +85°C, AD5040/AD5060 ±0.5 ±1 Guaranteed monotonic, −40°C to +125°C, Y grade Gain Error ±0.01 ±0.02 % of FSR T A = −40°C to +85°C, AD5040/AD5060 ±0.01 ±0.03 TA = −40°C to +125°C AD5060 Y grade Gain Error Temperature Coefficient 1 ppm of FSR/°C Offset Error ±0.02 ±1.5 mV TA = −40°C to + 85°C, AD5040/AD5060 ±0.02 ±2.0 TA = −40°C to + 125°C, AD5060 Y grade Offset Error Temperature Coefficient 0.5 μV/°C Full-Scale Error ±0.05 ±2.0 mV All 1s loaded to DAC register, AD5040 AD5060; TA = −40°C to +85°C ±0.05 ±2.0 All 1s loaded to DAC register, TA = −40°C to +125°C, AD5060 Y grade OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V REF V Output Voltage Settling Time 4 μs ¼ scale to ¾ scale code transition to ±1 LSB, RL = 5 kΩ Output Noise Spectral Density 64 nV/√Hz DAC code = midscale, 1 kHz Output Voltage Noise 6 μV p-p DAC code = midscale , 0.1 Hz to 10 Hz bandwidth Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around code 57386, RL = 5 kΩ, CL = 200 pF Digital Feedthrough 0. 003 nV-s DAC code = full scale DC Output Impedance (Normal) 0. 015 Ω Output impedance tolerance ±10% DC Output Impedance (Power-Down) (Output Connected to 1 kΩ Network)4 1 kΩ Output impedance tolerance ±400 Ω (Output Connected to 100 kΩ Network) 100 kΩ Output impedance tolerance ±20 kΩ Capacitive Load Stability 1 nF Loads used RL = 5 kΩ, RL = 100 kΩ, RL = ∞ Slew Rate 1. 2 V/μs ¼ scale to ¾ scale code transition to ±1 LSB, RL = 5 kΩ, CL = 200 pF Short-Circuit Current 60 ma DAC code = full scale, output shorted to GND, TA = 25°C

45 DAC code = zero scale, output shorted to

VDD, TA = 25°C DAC Power-Up Time 4.5 μs Time to exit power-down mode to normal mode of AD5060, 24th clock edge to 90% of DAC final value, output unloaded DC Power Supply Rejection Ratio −92.11 db VDD ± 10%, DAC code = full scale

Rev. A | Page 4 of 24 A, B, and Y Grades1 Parameter Min Typ Max Unit Test Conditions/Comments Wideband Spurious-Free Dynamic Range (SFDR) −67 db Output frequency = 10 kHz REFERENCE INPUT/OUTPUT VREF Input Range5 2 VDD − 50 mV Input Current (Power-Down) ±0.1 μA Zero scale loaded Input Current (Normal) ±0.5 μA DC Input Impedance 1 MΩ LOGIC INPUTS Input Current6 ±1 ±2 μA VIL, Input Low Voltage 0.8 V VDD = 4.5 V to 5.5 V 0.8 VDD = 2.7 V to 3.6 V VIH, Input High Voltage 2.0 V VDD = 2.7 V to 5.5 V 1.8 VDD = 2.7 V to 3.6 V Pin Capacitance 4 pF POWER REQUIREMENTS VDD 2.7 5.5 V All digital inputs at 0 V or VDD IDD (Normal Mode) DAC active and excluding load current VDD = 2.7 V to 5.5 V 1.0 0. 82 1.2 1. 0 mA VIN = VDD and VIL = GND, VDD = 5.0 V, VREF = 4.096 V, code = midscale VIN = VDD and VIL = GND, VDD = 3.0 V, VREF = 2.7 V, code = midscale IDD (All Power-Down Modes) VDD = 2.5 V to 5.5 V 0.33 μA VIH = VDD and VIL = GND, VDD = 5.5 V, VREF = 4.096 V, code = midscale 0.065 VIH = VDD and VIL = GND, VDD = 3.0 V, VREF = 4.096 V, code = midscale 1 Temperature range for the A and B grades is −40°C to + 85° C, typical at 25°C; temperature range for the Y grade is −40°C to +125°C. 2 Linearity calculated using a reduced code range (160 to code 65535 for AD5060 ) and (40 to code 16383 for AD5040). 3 Guaranteed by design and characterization, not production tested. 4 1 kΩ power-down network not available with the AD5040. 5 The typical output supply headroom performance for various reference voltages at −40°C can be seen in Figure 26. 6 Total current flowing into all pins.

VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency is 30 MHz. Figure 2. AD5060 Timing Diagram

Rev. A | Page 6 of 24 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating VDD to GND −0.3 V to +7.0 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V VOUT to GND −0.3 V to VDD + 0.3 V VREF to GND −0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A, B Grade) −40°C to +85°C Extended Automotive Temperature Range (Y Grade) −40°C to +125°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Power Dissipation (TJ max − TA)/θJA θJA Thermal Impedance 206°C/W θJc Thermal Impedance 91°C/W Reflow Soldering (Pb-free) Peak Temperature 260°C Time-at-Peak Temperature 10 sec to 40 sec ESD (AD5040/AD5060) 1. 5 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance integrated circuit with an ESD rating of <2 kV . It is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 3. Pin Configuration Table 5. Pin Function Descriptions 2 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and VDD should be decoupled to GND. 3 V REF Reference Voltage Input. 4 V OUT Analog Output Voltage from DAC. 5 AGND Ground Reference Point for Analog Circuitry. 6 DACGND Ground Input to the DAC Core. goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. be transferred at rates up to 30 MHz.

Rev. A | Page 14 of 24 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical AD5060 INL vs. code plot is shown in Figure 4. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical AD5060 DNL vs. code plot is shown in Figure 5. Offset Error Offset error is a measure of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V . The zero-code error is always positive in the AD5040/AD5060 because the output of the DAC cannot go below 0 V . This is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV . Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF AD5060, 0x3FFF AD5040) is loaded to the DAC register. Ideally, the output should be V DD − 1 LSB. Full-scale error is expressed in percent of full-scale range. Gain Error This is a measure of the span error of the DAC. It is the devia- tion in slope of the DAC transfer characteristic from ideal, expressed as a percent of the full-scale range. Tot a l Una dju ste d E r ror ( T UE ) Total unadjusted error is a measure of the output error taking all the various errors into account. A typical AD5060 TUE vs. code plot is shown in Figure 6. Offset Error Drift This is a measure of the change in zero-code error with a change in temperature. It is expressed in μV/°C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the worst case code 53786; see Figure 23 and Figure 24. The expanded view in Figure 23 shows the glitch generated following completion of the calibration routine; Figure 24 zooms in on this glitch. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus—that is, from all 0s to all 1s, and vice versa.

typical current consumption to less than 1 μa. Figure 40. The 4 MSBs of the 16-bit data-word are decoded to S0 to S11 of a 12-bit voltage mode R-2R ladder network.

15 EQUAL SEGMENTS

Figure 40. AD5060 DAC Ladder Structure The AD5040 andAD5060 operate with an external reference. buffered reference for the DAC core. MICROWIRE interface standards, as well as most DSPs. change in the mode of operation). The AD5060 input shift register is 24 bits wide; see Figure 41. modes (see the Power-Down Modes section for more detail). DAC register on the 24th falling edge of SCLK. Figure 41. AD5060 Input Register Content

The AD5040 input shift register is 16 bits wide; see Figure 42. register on the 16th falling edge of SCLK.

43 SYNC

contents nor a change in the operating mode occurs. state of the DAC while it is in the process of powering up. reset command is started in the AD5040 or AD5060. Figure 42. AD5040 Input Register Content Figure 43. AD5060 SYNC Interrupt Facility

Rev. A | Page 19 of 24 CHOOSING A REFERENCE FOR THE AD5040/ AD5060 To achieve the optimum performance from the AD5040/ AD5060, carefully choose a precision voltage reference. The AD5040/AD5060 have just one reference input, VREF. The voltage on the reference input is used to supply the positive input to the DAC. Therefore, any error in the reference is reflected in the DAC. There are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, ppm drift, long-term drift, and output voltage noise. Initial accuracy on the output voltage of the DAC leads to a full-scale error in the DAC. To minimize these errors, a reference with high initial accuracy is preferred. Also, choosing a reference with an output trim adjustment, such as an ADR43x device, allows a system designer to trim out system errors by setting a reference voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any errors. Because the supply current required by the AD5040/AD5060 is extremely low, the parts are ideal for low supply applications. The ADR395 voltage reference is recommended. This requires less than 100 μA of quiescent current and can, therefore, drive multiple DACs in one system, if required. It also provides very good noise performance at 8 μV p-p in the 0.1 Hz to 10 Hz range. SYNC SCLK DIN VOUT = 0V TO 5V ADR395 04767-036 3-WIRE SERIAL INTERFACE AD5040/ AD5060 Figure 50. ADR395 as Reference to AD5060/AD5040 voltage as practical for the system noise resolution required. supply to the AD5040/AD5060. Table 8. Precision References for the AD5040/AD5060

0.1 Hz to 10 Hz

2 RV1 R

2 R 1 R DV V DDDDO

corresponding to a +5 V output . Figure 51. Bipolar Operation with the AD5040/AD5060

0.65 BSC

0.15 MAX

0.05 MIN

1.45 MAX

0.95 MIN

0.22 MAX

0.08 MIN

0.38 MAX

0.22 MIN

Figure 53. 8-Lead Small Outline Transistor Package [SOT-23]

8 Lead SOT-23 RJ-8 D41

8 Lead SOT-23 RJ-8 D3X

Rev. A | Page 22 of 24 NOTES

Rev. A | Page 23 of 24 NOTES

Rev. A | Page 24 of 24 NOTES © 2005-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D04767-0-1/10(A)