AD5024_16 AD | Alldatasheet
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Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP Data Sheet AD5024/AD5044/AD5064 Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Low power quad 12-/14-/16-bit DAC, ±1 LSB INL Pin compatible and performance upgrade to AD5666 Individual and common voltage reference pin options Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to zero scale or midscale 3 power-down functions and per-channel power-down Hardware LDAC with software LDAC override function CLR function to programmable code SDO daisy-chaining option 14-/16-lead TSSOP Internal reference buffer and internal output amplifier
APPLICATIONS
Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators FUNCTIONAL BLOCK DIAGRAMS 06803-064 INTERFACE LOGIC AND SHIFT REGISTER INPUT REGISTER DIN SDO LDAC GND VDD LDAC VREFIN SYNC SCLK AD5064-1 CLR VOUTA VOUTB VOUTC VOUTD DAC REGISTER DAC A BUFFER INPUT REGISTER DAC REGISTER DAC B BUFFER INPUT REGISTER DAC REGISTER DAC C BUFFER INPUT REGISTER DAC REGISTER DAC D BUFFER POR POWER-DOWN LOGIC POWER-ON RESET Figure 1. AD5064-1 Functional Equivalent and Pin Compatible with AD5666 Figure 2. AD5024/AD5044/AD5064 with Individual Reference Pins down mode. Total unadjusted error for the devices is <2 mV .
- Quad channel available in 14-/16-lead TSSOPs.
- 16-bit accurate, 1 LSB INL.
- High speed serial interface with clock speeds up to 50 MHz.
- Reset to known output voltage (zero scale or midscale).
Table 1. Related Devices
16 LSB INL, TSSOP
1 LSB INL, TSSOP
AD5024/AD5044/AD5064 Data Sheet Rev. G | Page 2 of 28 TABLE OF CONTENTS LDAC Using the AD5024/AD5044/AD5064/AD5064-1 with a
REVISION HISTORY
6/2016—Rev. F to Rev. G 6/2013—Rev. E to Rev. F 5/2011—Rev. D to Rev. E 8/20—Rev. C to Rev. D Change to Minimum SYNC High Time (Single Channel 5/2010—Rev. B to Rev. C 6/2009—Rev. A to Rev. B 3/2009—Rev. 0 to Rev. A Changes to Features Section, General Description Section, Changes to Digital-to-Analog Converter Section, Reference Buffer Section, Output Amplifier Section, Serial Interface Added Modes of Operation Section, Daisy-Chaining Section, Changes to Bipolar Operation Section and Figure 56 to 8/2008—Revision 0: Initial Version
Data Sheet AD5024/AD5044/AD5064 Rev. G | Page 3 of 28 SPECIFICATIONS VDD = 4.5 V to 5.5 V , RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD, unless otherwise specified. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter B Grade1 A Grade1, 2 Unit Test Conditions/Comments Min Typ Max Min Typ Max STATIC PERFORMANCE3 Resolution 16 16 Bits AD5064/AD5064-1
14 Bits AD5044
12 Bits AD5024
Relative Accuracy (INL)4 ±0.5 ±1 ±0.5 ±4 LSB AD5064/AD5064-1; TA = −40°C to +105°C ±0.5 ±2 ±0.5 ±4 LSB AD5064/AD5064-1; TA = −40°C to +125°C ±0.25 ±1 LSB AD5044 ±0.12 ±0.5 LSB AD5024 Differential Nonlinearity (DNL)4 ±0.2 ±1 ±0.2 ±1 LSB Total Unadjusted Error ±2 ±2 mV V REF = 2.5 V, VDD = 5.5 V Offset Error4, 5 ±0.2 ±1.8 ±0.2 ±1.8 mV Offset Error Temperature Coefficient4, 6 ±2 ±2 μV/°C Full-Scale Error4 ±0.01 ±0.07 ±0.01 ±0.07 % FSR All 1s loaded to DAC register, VREF < VDD Gain Error4 ±0.005 ±0.05 ±0.005 ±0.05 % FSR VREF < VDD Gain Temperature Coefficient4, 6 ±1 ±1 ppm FSR/°C DC Crosstalk4, 6 40 40 μV Due to single-channel, full-scale output change, RL = 5 kΩ to GND or VDD 40 40 μV/mA Due to load current change 40 40 μV Due to powering down (per channel) OUTPUT CHARACTERISTICS6 Output Voltage Range 0 V DD 0 V DD V Capacitive Load Stability 1 1 nF R L = 5 kΩ, RL =100 kΩ, and RL = ∞ DC Output Impedance Normal Mode 0.5 0.5 Ω Power-Down Mode Output Connected to 100 kΩ Network 100 100 kΩ Output impedance tolerance ± 20 kΩ Output Connected to 1 kΩ Network 1 1 kΩ Output impedance tolerance ± 400 Ω Short-Circuit Current 60 60 mA DAC = full scale, output shorted to GND 45 45 mA DAC = zero scale, output shorted to V DD Power-Up Time7 4.5 4.5 μs DC PSRR −92 −92 dB VDD ± 10%, DAC = full scale, VREF < VDD REFERENCE INPUTS Reference Input Range 2.2 V DD 2.2 V DD V Reference Current 35 50 35 50 μA Per DAC channel; individual reference option 140 160 140 160 μA Single reference option Reference Input Impedance 120 120 kΩ Individual reference option 32 32 kΩ Single reference option LOGIC INPUTS Input Current8 ±1 ±1 μA Input Low Voltage, VINL 0.8 0.8 V Input High Voltage, VINH 2.2 2.2 V Pin Capacitance6 4 4 pF
AD5024/AD5044/AD5064 Data Sheet Rev. G | Page 4 of 28 Parameter B Grade1 A Grade1, 2 Unit Test Conditions/Comments Min Typ Max Min Typ Max LOGIC OUTPUTS (SDO)9 Output Low Voltage, VOL 0.4 0.4 V I SINK = 2 mA Output High Voltage, VOH V DD − 1 V DD − 1 I SOURCE = 2 mA High Impedance Leakage Current High Impedance Output Capacitance6 7 7 pF POWER REQUIREMENTS VDD 4.5 5.5 4.5 5.5 V DAC active, excludes load current IDD10 V IH = VDD, VIL = GND, Code = midscale Normal Mode 4 6 4 6 mA All Power-Down Modes11 0.4 2 0.4 2 μA T A = −40°C to +105°C 30 30 μA T A = −40°C to +125°C 1 Temperature range is −40°C to +125°C, typical at 25°C.
2 A grade offered in
AD5064 only. 3 Linearity and total unadjusted error are calculated using a reduced code range—AD5064/AD5064-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064. Output unloaded. 4 See the Terminology section. 5 Offset error calculated using a reduced code range—AD5064/AD5064-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064. Output unloaded 6 Guaranteed by design and characterization; not production tested. 7 Time to exit power-down mode to normal mode; 32nd clock edge to 90% of DAC midscale value, output unloaded. 8 Current flowing into individual digital pins. VDD = 5.5 V; VREF = 4.096 V; Code = midscale. 9 AD5064-1 only. 10 Interface inactive. All DACs active. DAC outputs unloaded. 11 All four DACs powered down. AC CHARACTERISTICS VDD = 4.5 V to 5.5 V , RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2 Min Typ Max Unit Test Conditions/Comments3 Output Voltage Settling Time 5.8 8 μs ¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ, single-channel update 10.7 13 μs ¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ, all channel update Slew Rate 1.5 V/μs Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry Reference Feedthrough −90 dB V REF = 3 V ± 0.86 V p-p, frequency = 100 Hz to 100 kHz Digital Feedthrough 0.1 nV-sec Digital Crosstalk 1.9 nV-sec Analog Crosstalk 2 nV-sec DAC-to-DAC Crosstalk 3.5 nV-sec AC Crosstalk 6 nV-sec Multiplying Bandwidth 340 kHz V REF = 3 V ± 0.86 V p-p Total Harmonic Distortion −80 dB V REF = 3 V ± 0.2 V p-p, frequency = 10 kHz Output Noise Spectral Density 64 nV/√ Hz DAC code = 0x8400, frequency = 1 kHz 60 nV/√Hz DAC code = 0x8400, frequency = 10 kHz Output Noise 6 μV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +125°C, typical at 25°C.
Data Sheet AD5024/AD5044/AD5064 Rev. G | Page 7 of 28 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter Rating VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to V DD + 0.3 V VOUT to GND −0.3 V to V DD + 0.3 V VREF to GND −0.3 V to V DD + 0.3 V Operating Temperature Range Industrial −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ MAX) 150°C TSSOP Power Dissipation (T J MAX − TA)/θJA θJA Thermal Impedance 113°C/W Reflow Soldering Peak Temperature Pb-Free 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
Figure 6. 14-Lead TSSOP (RU-14) Table 6. 14-Lead TSSOP (RU-14) Pin Function Descriptions all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode. SYNC acts as an interrupt and the write sequence is ignored by the device. decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 4 V OUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 5 V OUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. powers up all four DACs to midscale. 7 V REFIN This is a common pin for reference input for DAC A, DAC B, DAC C, and DAC D. is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 10 V OUTD Analog Output Voltage from DAC D. The outp ut amplifier has rail-to-rail operation. 11 V OUTB Analog Output Voltage from DAC B. The outp ut amplifier has rail-to-rail operation. 12 GND Ground Reference Point for All Circuitry on the Device. falling edge of the serial clock input. can be transferred at rates of up to 50 MHz.
Figure 7. 16-Lead TSSOP (RU-16) Pin Configuration Table 7. 16-Lead TSSOP (RU-16) Pin Function Descriptions all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode. SYNC acts as an interrupt and the write sequence is ignored by the device. decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 4 V REFB DAC B Reference Input. This is the reference voltage input pin for DAC B. 5 V REFA DAC A Reference Input. This is the reference voltage input pin for DAC A. 6 V OUTA Analog Output Voltage from DAC A. The outp ut amplifier has rail-to-rail operation. 7 V OUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 9 V REFC DAC C Reference Input. This is the reference voltage input pin for DAC C. contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 11 V REFD DAC D Reference Input. This is the reference voltage input pin for DAC D. 12 V OUTD Analog Output Voltage from DAC D. The outp ut amplifier has rail-to-rail operation. 13 V OUTB Analog Output Voltage from DAC B. The outp ut amplifier has rail-to-rail operation. 14 GND Ground Reference Point for All Circuitry on the Device. falling edge of the serial clock input. can be transferred at rates of up to 50 MHz.
AD5024/AD5044/AD5064 Data Sheet Rev. G | Page 18 of 28 DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nanovolt-seconds. Multiplying Bandwidth The multiplying bandwidth is a measure of the finite bandwidth of the amplifiers within the DAC. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth, expressed in kilohertz, is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) Total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels.
DACs. The devices operate from supply voltages of 4.5 V to 5.5 V . reduces the typical current consumption to typically 400 nA. DAC sections. A simplified circuit diagram is shown in Figure 46. 15 matched resistors to either GND or the VREF buffer output. switches of a 12-bit voltage mode R-2R ladder network.
15 EQUAL SEGMENTS
Figure 46. DAC Ladder Structure provide a reference for the DAC core. executed on individually selected DAC channels or on all DACs. Table 8. Command Definitions
1 Available in the
AD5064-1 14-lead TSSOP only. Table 9. Address Commands
supply current falls to 0.4 μA at 5 V . sequences for even lower power operation of the device. 32nd falling edge, this acts as an interrupt to the write sequence. default setting is standalone mode, where DB1 = 0. Table 10. DCEN (Daisy-Chain Enable) Register
0 X Standalone mode (default)
1 X DCEN mode
ripples out of the shift register and appears on the SDO line. the next DAC in the chain, a daisy-chain interface is constructed. frame and the data is discarded. must be taken high after the final clock to latch the data. Table 11. 32-Bit Shift Register Contents for Daisy-Chain Enable
output of the DAC while it is in the process of powering up. AD5064/AD5064-1 should take place during this time. when the power supplies have reached their final value. the bits corresponds to the mode of operation of the device. Table 12. Modes of Operation register during power-down/power-up operation. the output of the amplifier to a resistor network of known values. Figure 51. Output Stage During Power-Down exit power-down is typically 4.5 μs for VDD = 5 V (see Figure 30). Table 13. 32-Bit Shift Register Contents for Power-Up/Power-Down Function
loading the clear code register (see Table 8). Table 14. Clear Code Register during a write sequence, the write is aborted. pin, synchronously and asynchronously. writing to Input Register n and updating all DAC registers. remainder of the channels are synchronously updating. Table 15. LDAC 0 1 or 0 Determined by the LDAC pin.
1 X 1 DAC channels update, overrides
Table 16. 32-Bit Shift Register Contents for Clear Code Function Table 17. 32-Bit Shift Register Contents for LDAC Overwrite Function
AD5024/AD5044/AD5064 Data Sheet Rev. G | Page 24 of 28 POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board (PCB) containing the AD5024/AD5044/ AD5064/AD5064-1 should have separate analog and digital sections. If the AD5024/AD5044/AD5064/AD5064-1 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5024/AD5044/AD5064/AD5064-1. The power supply to the AD5024/AD5044/AD5064/AD5064-1 should be bypassed with 10 μF and 0.1 μF capacitors. The capaci- tors should be as physically close as possible to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitors are the tantalum bead type. It is important that the 0.1 μF capacitor have low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip tech- nique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.
0.65 BSC
Figure 59. 14-Lead Thin Shrink Small Outline Package [TSSOP] Figure 60. 16-Lead Thin Shrink Small Outline Package [TSSOP]
AD5024/AD5044/AD5064 Data Sheet Rev. G | Page 28 of 28 ORDERING GUIDE Model1 Temperature Range Accuracy Resolution Package Description Package Option AD5024BRUZ −40°C to +125°C ±0.5 LSB INL 12 Bits 16- Lead TSSOP RU-16 AD5024BRUZ-REEL7 −40°C to +125°C ±0.5 LSB INL 12 Bits 16-Lead TSSOP RU-16 AD5044BRUZ −40°C to +125°C ±1 LSB INL 14 Bits 16- Lead TSSOP RU-16 AD5044BRUZ-REEL7 −40°C to +125°C ±1 LSB INL 14 Bits 16-L ead TSSOP RU-16 AD5064ARUZ-1 −40°C to +125°C ±4 LSB INL 16 Bits 14- lead TSSOP RU-14 AD5064ARUZ-1REEL7 −40°C to +125°C ±4 LSB INL 16 Bits 14- lead TSSOP RU-14 AD5064BRUZ-1 −40°C to +125°C ±1 LSB INL 16 Bits 14- lead TSSOP RU-14 AD5064BRUZ-1REEL7 −40°C to +125°C ±1 LSB INL 16 Bits 14- lead TSSOP RU-14 AD5064BRUZ −40°C to +125°C ±1 LSB INL 16 Bits 16- Lead TSSOP RU-16 AD5064BRUZ-REEL7 −40°C to +125°C ±1 LSB INL 16 Bits 16- Lead TSSOP RU-16 EVAL-AD5064-1EBZ 14- Lead TSSOP Evaluation Board EVAL-AD5064EBZ 16- Lead TSSOP Evaluation Board 1 Z = RoHS Compliant Part. ©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06803-0-6/16(G)