AD4855 (Rev.0)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 68
Technical content
Buffered, 8-Channel Simultaneous Sampling, 16-Bit 250 kSPS DAS Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►Complete 16-bit data acquisition system ►Simultaneous sampling of 8 internally buffered channels ►250 kSPS per channel throughput ►Differential, wide common-mode range inputs ►±75 pA typical input leakage at 25°C ►Full-scale input step settling time < 300 ns ►Integrated reference and reference buffer (4.096 V) ►Integrated supply decoupling capacitors ►27 mW per channel at 250 kSPS, scales with throughput ►Minimal external signal conditioning ►Seamless high dynamic range ►Per sample, per channel automatic gain ranging ►Maintains ppm-level INL ►Per channel SoftSpan input ranges, bipolar or unipolar ►0 V to 40 V, 25 V, 20 V, 12.5 V, 10 V, 6.25 V, 5 V, 2.5 V ►Rail-to-rail input overdrive tolerance ►High performance ►INL: ±160 μV typical (±40 V range) ►SNR: 94.6 dB single-conversion typical (±40 V range) ►DR: 98.1 dB single-conversion typical (±40 V range) ►THD: −117 dB typical (±40 V range) ►CMRR: 120 dB typical ►Digital flexibility ►SPI CMOS (0.9 V to 5.25 V) and LVDS serial input and output ►Optional oversampling with 16-bit digital averaging ►Optional offset, gain, and phase correction ►7.00 mm × 7.00 mm, 64-ball BGA full solution footprint
APPLICATIONS
►Automatic test equipment ►Avionics and aerospace ►Instrumentation and control systems ►Semiconductor manufacturing ►Test and measurement FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram (Example Analog-Input Signal Use Cases Shown)
analog.com Rev. 0 | 2 of 68
REVISION HISTORY
8/2024—Revision 0: Initial Version
analog.com Rev. 0 | 3 of 68 The AD4855 is a fully buffered, 8-channel simultaneous sampling, 16-bit, 250 kSPS data acquisition system (DAS) with differential, wide common-mode range inputs. Its functional architecture is shown in Figure 1. Operating from a 5 V low voltage supply, flexible input buffer supplies, and using the precision low drift internal reference and reference buffer, the AD4855 allows the SoftSpan range of each channel to be independently configured to match the native application signal swing, minimizing additional external signal conditioning. To further maximize single-conversion dynamic range, the AD4855 incorporates seamless high dynamic range (SHDR) technology. When enabled, the input signal path gain of the channel is automatically optimized on a sample-by-sample basis, minimizing converter noise on each sample without impacting linearity. The 11 MHz bandwidth, picoamp input analog buffers, wide input common-mode range, and 120 dB common-mode rejection ratio (CMRR) of the AD4855 allow the DAS to directly digitize input signals with arbitrary swings on INx+ and INx−. Its input signal flexibility, combined with ±160 μV integral nonlinearity (INL), no missing codes at 16 bits, 94.6 dB signal to noise ratio (SNR), and 98.1 dB dynamic range, make the AD4855 an ideal choice for applications requiring high accuracy, throughput, and precision in a compact solution footprint. Enabling 16-bit oversampling offers fur- ther SNR and dynamic range improvements. Optional per channel offset, gain, and phase adjustment provide the ability to calibrate and remove system-level errors upstream to the DAS. The AD4855 features a serial peripheral interface (SPI) register configuration bus (0.9 V to 5.25 V) and supports both low voltage differential signaling buses (LVDS) and complementary metal-oxide semiconductor (CMOS) conversion data output buses, selectable using the LVDS/CMOS pin. Between one and eight lines of data output can be employed in CMOS mode, allowing the user to optimize bus width and throughput. The 7.00 mm × 7.00 mm, 64-ball, ball grid array (BGA) of the AD4855 includes all critical power supply and reference bypass ca- pacitors, minimizing full solution footprint and component count and reducing sensitivity to application printed circuit board (PCB) layout. The device operates over an extended industrial temperature range of −40°C to +125°C. Note that throughout this data sheet, multifunction pins such as LVDS/CMOS are referred to either by the entire pin name or by a single function of the pin. For example, LVDS when only that function is relevant. COMPANION PRODUCTS ►Voltage references: LTC6655-4.096 or ADR4540 ►Power solutions: LT1761, LT8330, and/or LT3042
unipolar SoftSpan ranges, and all specifications TMIN to TMAX, unless otherwise noted. Typical values are at TA = 25°C. Table 1. Specifications
Table 1. Specifications (Continued)
11 MHz
1 Positive analog-input pin voltage. 2 Negative analog-input pin voltage. 3 REFBUF pin voltage scaled by (1/1.024), nominally 4 V. 4 REFBUF pin voltage, nominally 4.096 V. 5 Common-mode voltage of the positive analog-input pin and the negative analog-input pin. Tolerance section for further details. Refer to the Absolute Maximum Ratings section for pin voltage and current limits related to device reliability. 7 Positive analog-input pin resistance. 8 Negative analog-input pin resistance. 9 Positive analog-input pin capacitance. 10 Negative analog-input pin capacitance. 11 A plot of the input-referred transition noise vs. the differential input level with SHDR on and off is shown in Figure 18. 12 LSB vs. SoftSpan shown in Table 12. nominal value or the temperature drift terms associated with the internal band-gap. 14 When REFIO is overdriven, the internal band-gap reference must be disabled using the Device Control Register. amplitude, and the THD, which is referred to the fundamental input signal amplitude. 16 A plot of dynamic range vs. oversampling ratio (OSR) is shown in Figure 34. 17 Sine wave at frequency on injection channel (fINJ) = 100 kHz and second sine wave at frequency on receiver channels (fRCV) = 1 kHz. 18 Temperature coefficient is calculated by dividing the maximum change in the output voltage by the specified temperature range (TMAX − TMIN). 19 When REFBUF is overdriven, the internal band-gap reference and reference buffer must be disabled using the Device Control Register. 20 IREFBUF varies proportionally with the sample rate and the number of active channels. 21 Enable or disable the LVDS termination resistance and half-bias mode using the Device Control Register. 22 A plot of the CMOS operating mode currents vs. sample rate is shown in Figure 33. 23 Refer to the Absolute Maximum Ratings section and the Junction Temperature section for the junction temperature limits related to device reliability.
Table 2. Universal Timing 1 The acquisition phase is the time available for the ADCs to acquire a new input with the DAS running at a throughput rate of 250 kSPS. Figure 2. Universal Timing
Table 3. SPI Register Configuration Bus Read/Write Timing Figure 3. SPI Register Configuration Bus Write Timing
Table 4. CMOS Conversion Data Output Timing Figure 6. CMOS Conversion Data Bus Timing
Table 5. LVDS Conversion Data Output Timing Figure 7. LVDS Conversion Data Bus Timing
Table 6. Absolute Maximum Ratings
1 The absolute maximum ratings of VIO depend on the selected state of the
2 Adding an external resistor in series with each of the INx+ and INx– pins
Tolerance section for further information.
3 The maximum junction temperature for continuous operation with nonderated
ing conditions for extended periods may affect product reliability. function of the junction operating temperature. 95°C for a compensating time period of 3.2 hours. Table 7. Thermal Resistance sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 8. AD4855, 64-Ball BGA damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 8. Pin Configuration Table 9. Universal Pin Function Descriptions configuration of each channel. GND P Power Supply Ground. Solder all GND pins to a solid ground plane. conversion initiates a global device reset, equivalent to a POR event. Logic levels are determined by the VIO supply. specified device performance levels. The CNV high and low threshold voltages are 0.8 V and 0.4 V, respectively. the GND pins with a 0.1 μF ceramic capacitor. power-on-reset and goes low once power-on-reset completes. Logic levels are determined by the VIO supply. recommended use cases and precautions. section for recommended uses cases and precautions.
Table 9. Universal Pin Function Descriptions (Continued) recommended uses cases and precautions. affect the behavior of the SPI register configuration bus. Logic levels are determined by the VIO supply. is internally bypassed to the IOGND pin with a 1 μF ceramic capacitor. Logic levels are determined by the VDD supply. E6 IOGND P Digital Input and Output Power Supply Ground. Solder the IOGND pin to the same ground plane as the GND pins. with a 1 μF ceramic capacitor. with a 1 μF ceramic capacitor. are determined by the VIO supply. bypassed to the GND pins with a 0.1 μF ceramic capacitor. CSCK pin is allowed to idle either high or low. Logic levels are determined by the VIO supply. data during read transactions. Logic levels are determined by the VIO supply. disabled and high-Z when the CS pin is high. Logic levels are determined by the VIO supply. 1 AI is analog input, AO is analog output, P is power, DI is digital input, and DO is digital output. 2 The maximum operating and absolute maximum ratings of the VIO supply, and associated digital inputs and outputs, are defined by the HIVIO/LOVIO pin state.
Table 10. CMOS Conversion Data Bus Pin Function Descriptions levels are determined by the VIO supply. allowed to idle either high or low. Logic levels are determined by the VIO supply. pin is high-Z. Logic levels are determined by the VIO supply. 1 AI is analog input, AO is analog output, P is power, DI is digital input, and DO is digital output. Table 11. LVDS Conversion Data Bus Pin Function Descriptions through the Device Control Register. disabled through the Device Control Register, these pins are high-Z. 100 Ω resistor at the receiver (FPGA). 1 AI is analog input, AO is analog output, P is power, DI is digital input, and DO is digital output.
analog.com Rev. 0 | 29 of 68 Integral Nonlinearity (INL) Error INL is the deviation of each individual code from a line drawn through the two endpoints of the ADC transfer function. The two endpoints of the transfer function are ½ LSB before the first code transition and 1½ LSB beyond the last code transition. The devia- tion is measured from the middle of each code to the true straight line. Differential Nonlinearity (DNL) Error In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. DNL is often specified in terms of resolution for which no missing codes are guaranteed. Zero-Scale Error For both bipolar and unipolar SoftSpan ranges, zero-scale error is the difference between the ideal zero-scale input voltage of 0 V and the actual input voltage which produces the zero-scale output code of 0 LSB. Full-Scale Error For bipolar SoftSpan ranges, full-scale error is the worst-case devi- ation of the first and last code transitions from ideal. It includes the effect of zero-scale error and any contributions from the reference buffer. For unipolar SoftSpan ranges, full-scale error is the worst-case deviation of the last code transition from ideal. It includes the effect of zero-scale error and any contributions from the reference buffer. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the following formula: ENOB = (SINADdB − 1.76)/6.02 ENOB is expressed in bits. Dynamic Range Dynamic range is the ratio of the RMS amplitude of a full-scale sine wave to the total RMS noise and is expressed in decibels (dB). It is measured with a −60 dBFS input signal to include all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the RMS amplitude of a full-scale sine wave to the RMS sum of all other spectral components below the Nyquist frequency, excluding the first five harmonics and DC. The value for SNR is expressed in decibels (dB). Signal-to-Noise-and-Distortion (SINAD) Ratio SINAD is the ratio of the RMS amplitude of a full-scale sine wave to the RMS sum of all other spectral components below the Nyquist frequency, including harmonics but excluding DC. The value for SINAD is expressed in decibels (dB). Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first five harmonic compo- nents to the RMS amplitude of the fundamental input signal and is expressed in decibels (dB). Spurious-Free Dynamic Range (SFDR) SFDR is the difference in decibels (dB) between the RMS amplitude of a full-scale input signal and the peak spurious signal. Channel-to-Channel Crosstalk Channel-to-channel crosstalk is measured by applying a sine wave at frequency (fINJ) on one interferer injection channel and a second sine wave at a different frequency (fRCV) on all receiver channels. Crosstalk is the ratio of the RMS sum of the spectral tones at fINJ and up to fifth-order intermodulation products on the receiver and injector channels. Channel-to-channel crosstalk is expressed in decibels (dB). All channels convert at fS = 250 kSPS with the internal reference and reference buffer enabled during the meas- urement. Aperture Delay Aperture delay is a measure of acquisition performance. It is the time between the rising edge of the CNV input and when the input signals are held for a conversion. Transient Response Transient response is the time required for the ADC to acquire a full-scale input step to 50 ppm settling accuracy. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the RMS amplitude of a sine wave of frequen- cy (f) applied to the analog input common-mode voltage to the RMS amplitude of the ADC output data at frequency (f). The value for CMRR is expressed in decibels (dB). Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the RMS amplitude of a sine wave of frequency (f) applied to the power supply voltage to the RMS amplitude of the ADC output data at frequency (f). The value for PSRR is expressed in decibels (dB).
Table 12. SoftSpan Range Properties Table 13. Per Channel SoftSpan Registers input-referred conversion noise on a sample-by-sample basis. noise level for all samples. control bit in the SEAMLESS_HDR register.
every conversion, just prior to the falling edge of the BUSY line. first sample of oversampling mode. window, just prior to the falling edge of the BUSY line. Figure 51. Oversampling Mode with 4× Oversampling Ratio (OS_RATIO = 0x1)
the corresponding CHx_OFFSET register, shown in Table 14. curs at negative and positive full scale for bipolar SoftSpan ranges. on the magnitude and the polarity of the digital offset employed. Table 14. Per Channel Offset Correction Registers with the default of 1.00000 corresponding to CHx_GAIN = 0x8000. tive full scale depending on the magnitude of digital gain employed. Table 15. Per Channel Gain Correction Registers so forth) as shown in Figure 51.
- The maximum phase correction allowed is one less than the
Table 16. Per Channel Phase Correction Registers Figure 52. Oversampling Mode with 4× Oversampling Ratio (OS_RATIO = 0x1), Channel 7 Averages Phase-Shifted by One Sample (CH7_PHASE = 0x0001)
the CH_OR_STATUS register or CH_UR_STATUS register is set. and CHx_UR registers, shown in Table 17 and Table 18. Table 17. Per Channel Overrange Limit Registers Table 18. Per Channel Underrange Limit Registers
true bipolar, and fully differential). process and is, therefore, reacquired for each new conversion. than 100 V/μs at the sampling moment. Figure 53. Equivalent Circuit for Differential Analog Inputs, Single Channel drive the passive 4 pF analog input capacitance (CPIN) directly. maintain the full DC accuracy of the AD4855. arbitrarily slow time constants for anti-aliasing or other purposes. ed to driving the high impedance analog inputs directly. less than the coupling that can be present in a poor PCB design. grounding serves as a shield between channels. up to 10 mA does not affect conversion results on other channels. supply may corrupt the conversion results on other channels.
associated with the PD pin going high is not affected by the reset. time produces invalid results. Figure 63. Reset Timing for the AD4855
16-bit, and 24-bit. The default packet size is 24-bit. and status packet data formats shown in Figure 70 are available. the eight channel packets plus the ninth status packet. Figure 70. Channel and Status Packet Data Formats in Nonversampling Mode (OS_EN = 0), Test Pattern Output Disabled (TEST_PAT = 0)
and status packet data formats shown in Figure 71 are available. all data in the eight channel packets and the ninth status packet. Figure 71. Channel and Status Packet Data Formats in Oversampling Mode (OS_EN = 1), Test Pattern Output Disabled (TEST_PAT = 0)
Table 19. Per Channel Test Pattern Registers Figure 72. Channel and Status Packet Data Formats with Test Pattern Output Enabled (TEST_PAT = 1)
independent of the CMOS or LVDS conversion data output buses. Configuration D Register register. address word specifies the address of the register to be accessed. be provided in a single SPI frame. the CSDIO line on the CSCK line rising edge for register writes. following each data byte (see the SPI Bus CRC Checking section). AD4855 and the digital host. Figure 73. 3-Wire SPI Register Configuration Bus Frame
functions as the serial data output. Figure 74. 4‐ Wire SPI Register Configuration Bus Frame
analog.com Rev. 0 | 49 of 68 Streaming Instruction Mode When the INST_MODE bit (Bit 7) in the SPI Configuration B Register is set to 0, streaming mode is enabled. In streaming mode, only one instruction phase (see the Instruction Phase section) is accepted per SPI frame and is followed by multiple data phases (see the Data Phase section), one per register being accessed. The register address being read from or written to is automatically incremented (ADDR_DIR bit high, Bit 5 of the SPI Configuration A Register) or decremented (ADDR_DIR bit low, Bit 5 of the SPI Configuration A Register) after each data phase. Streaming mode enables efficient access to large, contiguous register addresses of the AD4855 memory map and is enabled by default. If the ascending address option is selected, the address automati- cally increments the number of times defined by the LOOP_SIZE bits (Bits[7:0] in the Loop Configuration A Register). If the address reaches 0xB9, it then continues from Address 0x00 on the subse- quent byte access. If the descending address option is selected, the address automati- cally decrements the number of times defined by LOOP_SIZE bits (Bits[7:0] in the Loop Configuration A Register). If the address reaches 0x00, it then continues from Address 0xB9 on the subse- quent byte access. By default, the LOOP_SIZE bits (Bits[7:0] in the Loop Configuration A Register) reset to 0 at every rising edge of the CS pin; therefore, a user-set value only persists for one SPI frame. If persistent looping is required, set KEEP_LOOP_SIZE bit (Bit 2 in the Loop Configuration B Register) to 1. There is only one instruction phase per frame in streaming mode; therefore, all SPI transactions in a given SPI frame are either all reads or all writes. Nonstreaming Instruction Mode When the INST_MODE bit (Bit 7 in the SPI Configuration B Regis- ter register) is set to 1, nonstreaming instruction mode is selected. In nonstreaming instruction mode, one or more SPI transactions can be provided in a single SPI frame. Each transaction includes an instruction phase to specify whether a read or write is being performed, and which address is being accessed. Nonstreaming instruction mode allows the digital host to quickly read from and write to registers with nonadjacent register addresses in a single SPI frame, as opposed to streaming mode, which allows exclusively reading from or writing to registers with adjacent addresses in an SPI frame. SPI Bus CRC Checking The AD4855 register bus data includes optional error checking based on an 8-bit CRC. When the CRC is enabled, an 8-bit checksum code is appended to the data phase of the read or write transaction for each register. The value of the checksum is calculated from the data read or written, allowing the AD4855 and the digital host to detect if data corruption has occurred. If the checksum does not match the corresponding register data, the register read or write is considered invalid. Use the following CRC polynomial to calculate the checksums: x 8 + x 2 + x + 1 (6) The initial value for the CRC calculation is 0xA5 in all transactions.
reset. The access mode specifies whether bits are read-only (R), read or write (R/W), or read or write one to clear (R/W1C). Table 20. Register Summary
Table 20. Register Summary (Continued)
Figure 75. Address: 0x00, Reset: 0x00, Name: SPI_CONFIG_A Table 21. Bit Descriptions for SPI_CONFIG_A to 1 using a single register write initiates a software reset of the AD4855. the ADDR_DIR and CSDO_EN bits in the SPI_CONFIG_A register. configuration bus (see the Streaming Instruction Mode section). the 4-Wire SPI Operation section). output on CSDIO. CSDO is not used and remains high-Z. SPI_CONFIG_D register is set to 1). to 1 using a single register write initiates a software reset of the AD4855. the ADDR_DIR and CSDO_EN bits in the SPI_CONFIG_A register.
Figure 91. Address: 0x20, Reset: 0x40, Name: DEVICE_STATUS Table 37. Bit Descriptions for DEVICE_STATUS CRC register has not been programmed with the proper CRC code. Underrange Status Register register. Channel Sleep Register register.
Table 43. Bit Descriptions for OVERSAMPLE (Continued) 0000: Average 2 conversions results. 0001: Average 4 conversions results. 0010: Average 8 conversions results. 0011: Average 16 conversions results. 0100: Average 32 conversions results. 0101: Average 64 conversions results. 0110: Average 128 conversions results. 0111: Average 256 conversions results. 1000: Average 512 conversions results. 1001: Average 1024 conversions results. 1010: Average 2048 conversions results. 1011: Average 4096 conversions results. 1100: Average 8192 conversions results. 1101: Average 16,384 conversions results. 1110: Average 32,768 conversions results. 1111: Average 65,536 conversions results. Figure 98. Address: 0x28, Reset: 0xFF, Name: SEAMLESS_HDR Table 44. Bit Descriptions for SEAMLESS_HDR
registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A.
- DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
- ALL DIMENSIONS ARE IN MILLIMETERS
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
0.40 REF Ø 64x
0.32 REF
0.70 REF
- PRIMARY DATUM -Z- IS SEATING PLANE
6 PACKAGE ROW AND COLUMN LABELING MAY VARY
Figure 107. 64-Ball BGA Package 2 The EVAL-AD4857FMCZ evaluation board can be used to evaluate the AD4855.