AD4693 AD | Alldatasheet
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8-Channel, Easy Drive Multiplexed SAR ADC with Averaging Filters Per Channel Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT
FEATURES
►Easy Drive features enable compact system designs ►Precharge buffers reduce analog input and reference circuit drive requirements ►On-chip reference buffer (WLCSP only) ►Small footprint, big performance ►Sample rate: 500kSPS (AD4693) and 1MSPS (AD4694) ►INL: ±0.85 LSB maximum ►Guaranteed 16-bit, no missing codes ►First conversion accurate ►SINAD: 93dB typical, fIN = 1kHz ►14.6mW at fS = 1MSPS and 7.3mW at fS = 500kSPS ►24-lead 4mm × 4mm LFCSP or 36-ball 2.96mm × 2.96mm WLCSP ►Enhanced digital functionality ►Averaging filters per channel ►Customizable channel sequencer ►Interleaved channel sampling ►Autonomous and burst sampling modes ►4-wire SPI compatible with 1.2V and 1.8V logic ►Wide operating temperature range: −40°C to +125°C
APPLICATIONS
►Optical power monitoring ►Medical instrumentation ►Electronic test and measurement ►Automated test equipment ►Battery-powered equipment GENERAL DESCRIPTION The AD4693/AD4694 are compact, high accuracy, 16-channel, 16- bit successive approximation register (SAR) analog-to-digital con- verters (ADCs) optimized for high-density multichannel precision data acquisition solutions. The AD4693/AD4694 combine precision performance with Easy Drive features and flexible digital processing to ensure compatibility with space-constrained analog front-end (AFE) designs and low-power digital hosts. The AD4693/AD4694 Easy Drive features broaden the selection of compatible amplifiers and voltage references. The precharge buf- fers enable smaller and lower power AFE designs by significantly reducing input voltage and current transients that typically force AFEs to include high-bandwidth ADC driver amplifiers per channel. The WLCSP model also includes an integrated reference buffer which provides a true, buffered reference input. The AD4693/AD4694 digital features and serial interface are opti- mized for use with low-power or power-cycled microcontrollers. The AD4693/AD4694 include averaging filters per channel and a customizable channel sequencer, which combined enable on-chip noise filtering with channel-independent averaging ratios. An inte- grated burst sampling timer enables autonomous and burst sam- pling schemes to perform conversions with minimal digital resour- ces. Device configuration and ADC data readback are supported via a robust, 4-wire serial peripheral interface (SPI) with optional cyclic redundancy check (CRC). The AD4693/AD4694 are available in a 4mm × 4mm, 24-lead lead frame chip scale package (LFCSP) and a 2.96mm × 2.96mm, 36-ball wafer level chip scale package (WLCSP) with operation specified from −40°C to +125°C.
analog.com Rev. 0 | 2 of 77 Masking Channels to Avoid Lockout Evaluating the AD4693/AD4694
REVISION HISTORY
2/2026—Revision 0: Initial Version
Figure 1. AD4693/AD4694 Functional Block Diagram
values at TA = −40°C to +125°C and typical values at TA = +25°C, unless otherwise specified. Table 1. Specifications
Table 1. Specifications (Continued)
1 The reference buffer turn-on time specification is the time needed for the reference buffer to drive the REF voltage from 0V to VREF to 0.01% accuracy. See Figure 41. 2 Offset error, gain error, and full-scale error drift utilizes the box method across the full operating temperature range of −40°C to +125°C. 3 %FS is the percentage of the ADC full scale (see the Transfer Function section for a definition of full scale). 4 See the Internal LDO Regulator section for more information.
configuration. Minimum and maximum values at TA = −40°C to +125°C and typical values at TA = +25°C, unless otherwise specified. Table 2. ADC Timing Specifications tCYC − 515ns, and therefore increases with slower sampling rates. 2 See the nominal oscillator frequency settings in Table 41. Table 3. SPI Timing (All Modes Except Manual Mode) Table 4. SPI Timing (Manual Mode)
Table 6. Absolute Maximum Ratings 1 INn refers to the analog inputs, Pin IN0 through Pin IN7. ing conditions for extended periods may affect product reliability. with JESD51-12. The worst case junction temperature is reported. Table 7. Thermal Resistance
1 Simulated values are based on the JEDEC 2S2P thermal test board with
2 Simulated values are measured to the package top surface with a cold plate
attached directly to the package top surface. sitive devices in an ESD-protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 8. AD4693/AD4694 24-Lead LFCSP Table 9. AD4693/AD4694 36-Lead WLCSP devices and circuit boards can discharge without detection. taken to avoid performance degradation or loss of functionality.
Figure 4. AD4693/AD4694 LFCSP Pin Configuration Table 10. AD4693/AD4694 LFCSP Pin Function Descriptions 1 IN1 AI Analog Input Channel 1. 2 IN2 AI Analog Input Channel 2. 3 IN3 AI Analog Input Channel 3. Multiplexer Configuration Options section). COM is nominally tied to signal ground. 5 IN4 AI Analog Input Channel 4. 6 IN5 AI Analog Input Channel 5. 7 IN6 AI Analog Input Channel 6. 8 IN7 AI Analog Input Channel 7. 9 AGND P Analog Supply Ground. AVDD, LDO_IN, and VDD are referenced to AGND. powering VDD with an external 1.8V supply, tie LDO_IN to AGND. See the Internal LDO Regulator section for more information. 13 RESET DI Hardware Reset Input (Active Low). Drive RESET low to perform a hardware reset of the device (see the Device Reset section). nominally supplied by the host interface logic supply (1.2V or 1.8V). Decouple VIO to IOGND with a local 100nF capacitor. 15 IOGND P Logic Input and Output Ground. VIO is referenced to IOGND. status and hardware interrupt signals (see the General Purpose Pin Functions section). 17 SDO DO Serial Data Output. Data are shifted out of the SDO output on the falling edge of SCK. 18 SCK DI Serial Data Clock Input. SCK is used to clock out data on SDO and clock in data on SDI during SPI transactions. 19 SDI DI Serial Data Input. Data are shifted into the SDI input on the rising edge of SCK. Modes of Operation section).
Table 10. AD4693/AD4694 LFCSP Pin Function Descriptions (Continued) 21 CS DI Chip Select Input (Active Low). The CS input frames all SPI transactions (see the Digital Interface section). Multiplexer Configuration Options section). REF must be decoupled with a minimum 1μF capacitor for optimal operation. 24 IN0 AI Analog Input Channel 0. pad be soldered to the system ground plane. 1 AI is analog input, P is power, DI is digital input, DO is digital output, and NC is no internal connection. Figure 5. AD4693/AD4694 WLCSP Pin Configuration Table 11. AD4693/AD4694 WLCSP Pin Function Descriptions A1 SDI DI Serial Data Input. Data are shifted into the SDI input on the rising edge of SCK. A2 CS DI Chip Select Input (Active Low). The CS input frames all SPI transactions (see the Digital Interface section). A3 REFIN AI Internal Reference Buffer Input. The internal reference buffer provides a high impedance input for the ADC VREF voltage. A4, A5, A6NC AI No Connect. Leave these pins open or connected to AGND. B1 SDO DO Serial Data Output. Data are shifted out of the SDO output on the falling edge of SCK. in the Modes of Operation section). 5.1V. REF must be decoupled with a minimum 1μF capacitor for optimal operation. B4 NC AI No Connect. Leave this pin open or connected to AGND.
Table 11. AD4693/AD4694 WLCSP Pin Function Descriptions (Continued) B5 IN0 AI Analog Input Channel 0. B6 IN1 AI Analog Input Channel 1. device status and hardware interrupt signals (see the General Purpose Pin Functions section). C2 SCK DI Serial Data Clock Input. SCK is used to clock out data on SDO and clock in data on SDI during SPI transactions. Multiplexer Configuration Options section). the Multiplexer Configuration Options section). COM is nominally tied to signal ground. C5 IN2 AI Analog Input Channel 2. C6 IN3 AI Analog Input Channel 3. device status and hardware interrupt signals (see the General Purpose Pin Functions section). device status and hardware interrupt signals (see the General Purpose Pin Functions section). D4 AGND P Analog Supply Ground. AVDD, LDO_IN, and VDD are referenced to AGND. D5 IN5 AI Analog Input Channel 5. D6 IN4 AI Analog Input Channel 4. nominally supplied by the host interface logic supply (1.2V or 1.8V). Decouple VIO to IOGND with a local 100nF capacitor. device status and hardware interrupt signals (see the General Purpose Pin Functions section). E3 IOGND P Logic Input and Output Ground. VIO is referenced to IOGND. E4, E5, E6NC AI No Connect. Leave these pins open or connected to AGND. F2 LDO_IN P Internal LDO Regulator Input. Nominally tied to AVDD when using the internal LDO regulator to supply the 1.8V VDD rail. F4 NC AI No Connect. Leave this pin open or connected to AGND. F5 IN7 AI Analog Input Channel 7. F6 IN6 AI Analog Input Channel 6. 1 AI is analog input, P is power, DI is digital input, DO is digital output, and NC is no internal connection.
analog.com Rev. 0 | 20 of 77 Integral Nonlinearity Error (INL) INL is the deviation of each individual code from a line drawn through the two endpoints of the ADC transfer function. The two endpoints of the transfer function are ½ LSB before the first code transition and 1½ LSB beyond the last code transition. The devia- tion is measured from the middle of each code to the true straight line. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. DNL is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The offset error is the deviation of the measured transition between −FSR and −FSR + 1 from the ideal transition. The ideal transition between −FSR and −FSR + 1 occurs at an analog input level ½ LSB above 0V (see the Transfer Function section). Offset error drift is the typical change in offset error vs. temperature, expressed in μV/°C. Offset error match is the largest difference in offset error between any two input channels for a given device. Gain Error Gain error is the deviation of the slope of the measured transfer function and the ideal transfer function. The ideal slope is VREF/216. Gain error drift is the typical change in gain error vs. temperature, expressed in ppm/°C. Gain error match is the largest difference in gain error between any two input channels for a given device. Full-Scale Error The full-scale error is the deviation of the measured transition between +FSR – 1 and +FSR from the ideal transition, measured in LSBs. The ideal transition between +FSR − 1 and +FSR occurs for an analog input level 1½ LSB below the nominal full scale (see the Transfer Function section). Full-scale error is combination of the offset and gain errors for each device. Full-scale error drift is the typical change in full-scale error vs. temperature, expressed in ppm/°C. Dynamic Range Dynamic range is the ratio of the RMS value of the full scale to the total RMS noise measured with the inputs shorted together. The value for dynamic range is expressed in dB and is measured with a signal at −60dBFS to include all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the RMS value of the actual input signal to the RMS sum of all other spectral components below the Nyquist frequency, excluding harmonics and DC. The value for SNR is expressed in dB. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of harmonics to the fundamental and is defined as THD dB = 20 log V 2 2 + V 3 2 + V 4 2 + V 5 2 + V 6 2 V 1 (1) where: V1 is the RMS amplitude of the fundamental. V2, V3, V4, V5, and V6 are the RMS amplitudes of the second through the sixth harmonic. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the RMS voltage of a full-scale sine wave to the RMS sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding DC. The value of SINAD is expressed in decibels. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input and is related to SINAD by the following formula: ENOB = (SINAD − 1.76)/6.02 ENOB is expressed in bits. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the RMS ampli- tude of the input signal and the peak spurious signal. Channel-to-Channel Crosstalk Channel-to-channel crosstalk is a measure of the level of crosstalk from a signal on an inactive channel to an active channel. Channel- to-channel crosstalk is measured by applying a full-scale interferer sine wave on one or more channels and a DC mid-scale signal on the active channel. The channel-to-channel crosstalk is the ratio of the amplitude of the interferer sine wave and the amplitude of the spectrum of the active channel at the same frequency. Channel-to-Channel Memory Channel-to-channel memory is a measure of the level of crosstalk that occurs when switching between channels in a channel se- quence. It is measured by applying a full-scale interferer sine wave to one analog input channel and a DC voltage on another analog input channel, and repeatedly alternating sampling between the two channels on each conversion. The channel-to-channel memory is the ratio of the amplitude of the interferer sine wave and the amplitude of the spectrum of the DC-driven channel at the same frequency. Aperture Delay Aperture delay is the measure of the acquisition performance. Aperture delay is the time between the rising edge of the CNV
analog.com Rev. 0 | 21 of 77 input (or other convert-start trigger based on the selected operating mode) and when the input signal is held for a conversion.
constrained precision measurement applications (see Figure 1). LFCSP or in a 36-lead 2.96 mm × 2.96 mm WLCSP. sponding 16-bit digital output. tion. The precharge phase ends 515ns after the start of conversion. the precharge buffers and precharge phase. start initiates another conversion phase. longer sample periods and is equal to tCYC − 515ns. Figure 47. ADC Phase Timing Diagram
Table 13. Averaging Filter Right-Shift Operations vs. ACC_COUNT data transfer to the digital host. Table 14. Averaging Filter Data Registers (AVG_INx) Table 15. Averaging Filter Data Plus Status Registers (AVG_STS_INx) Table 16. Accumulator Data Registers (ACC_INx) Table 17. Accumulator Data Plus Status Registers (ACC_STS_INx)
500mV across a −40°C to 125°C temperature range. Table 18. General Purpose Pin Configuration reducing the number of digital isolation channels. Table 18. The logic output thresholds for the GP0 pin to the GP3 pin are specified in Table 1 as VOL and VOH. applications by reducing the number of digital isolation channels. are specified in Table 1 as VIL and VIH.
ADC sampling control and timing. AD4694 operating modes. CNV clock mode is selected by default. Table 19. Operating Mode Feature Summary Table 20. Operating Mode Configuration Bits 1 A state reset is required after changing the state of ADC_MODE or STOP_STATE. 2 OSC_EN must be set to 0 before updating ADC_MODE.
transaction errors from inadvertently enabling or disabling CRC.
- The checksum calculator applies the CRC-8 polynomial to the
AD4694 to detect transmission errors from the host and vice versa. missions and resulting unexpected device configuration settings. Table 22. CRC Calculator Seed and Data Values
using the AD4693/AD4694 advanced sequencer mode. while the HP channels are sampled multiple times per sequence. Figure 87. Sequence of HP and LP Channels in Two-Priority Channel NLP is the number of LP channels. NHP is the number of HP channels. Table 23. Two-Priority Example with Sampling Rates and Output Data Rates
0 IN0 fS/4 4 fS/16
1 IN1 fS/4 4 fS/16
2 IN2 fS/4 4 fS/16
3 IN3 fS/8 2 fS/16
4 IN0 fS/4 4 fS/16
5 IN1 fS/4 4 fS/16
6 IN2 fS/4 4 fS/16
7 IN4 fS/8 2 fS/16
Figure 88. Two-Priority Example Timing Diagram
analog.com Rev. 0 | 57 of 77 LAYOUT GUIDELINES The following are suggested layout techniques for achieving optimal performance of the AD4693/AD4694 populated on a PCB. An example PCB layout is provided in the user guide for the AD4694 evaluation board (EVAL-AD4692-ARDZ). Analog traces (that is, traces connected to the analog inputs and reference input) must be physically separated from the digital traces (that is, traces to the CNV input, SPI, and general-purpose pins) to limit cross coupling from fast switching digital signals into the analog input signals. Add ground fill between analog and digital traces on the same PCB layer. Do not cross digital traces over the analog traces or the AD4693/AD4694 devices without a ground plane PCB layer in between. The analog and digital pins on the AD4693/AD4694 are arranged to facilitate separation of analog and digital traces. The AD4693/AD4694 analog inputs (IN0 to IN7) have a dynamic in- put impedance due to the multiplexer and ADC core input switches, which toggle between conversions. An external capacitor is recom- mended to reduce nonlinear voltage steps at the analog inputs. Place these external capacitors as close to the analog inputs as possible to minimize parasitic impedance paths between the two, which can degrade performance. The AD4693/AD4694 voltage reference input, REF, also has a dynamic input impedance. The effective impedance between the reference drive circuitry output and the REF input must be very low, and a decoupling capacitor must be placed as close to the REF pin as possible. If the internal reference buffer is not used, connect the external reference circuitry to the REF pin with wide traces to minimize the trace impedance. The power supplies of the AD4693/AD4694 must be decoupled with low effective series resistance (ESR) ceramic capacitors placed close to the supply pins and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines (see the Power Supplies section). If LDO_IN is powered from the same supply as AVDD, short the pins with a wide common trace, and a single 100nF capacitor can be used to decouple both pins. The AN-617 Application Note, Wafer Level Chip Scale Package, has information on PCB layout and assembly for the WLCSP. EVALUATING THE AD4693/AD4694 PERFORMANCE The AD4693/AD4694 evaluation tool offerings include a fully as- sembled and tested evaluation board (EVAL-AD4692-ARDZ), in- cluding the 16-channel equivalent device (AD4692), evaluation software for controlling the board from a PC and support documen- tation for the hardware and software. The EVAL-AD4692-ARDZ board allows for prototyping the analog front-end circuitry and reference circuitry with the various digital features offered by the AD4693/AD4694. It also features a standard Arduino Uno digital header, enabling interfacing to the EVAL-SDP- CK1Z board or third party controller boards for prototyping interface firmware and application software.
AD4693/AD4694 configuration registers. Table 24. AD4693/AD4694 Configuration Register Summary
Table 25. Bit Descriptions for SPI_CONFIG_A a software reset fo the device. All registers reset to their default power-up state except the SPI_CONFIG_A register. software reset fo the device. All registers reset to their default power-up state except the SPI_CONFIG_A register. Table 26. Bit Descriptions for SPI_CONFIG_B
Table 27. Bit Descriptions for DEVICE_TYPE [3:0] DEVICE_TYPEDevice Type Indicator Field. This field identifies the Analog Devices, Inc., product category that the device belongs to. The value 0x7 corresponds to precision ADCs. Table 28. Bit Descriptions for PRODUCT_ID_LSB Table 29. Bit Descriptions for PRODUCT_ID_MSB
Table 30. Bit Descriptions for SCRATCH_PAD have no impact on device configuration or behavior. Table 31. Bit Descriptions for VENDOR_ID_LSB Table 32. Bit Descriptions for VENDOR_ID_MSB Table 33. Bit Descriptions for STREAM_MODE
Table 34. Bit Descriptions for SPI_CONFIG_C Table 35. Bit Descriptions for SPI_STATUS only cleared by writing it to 1. is a sticky bit and is only cleared by writing it to 1.
Table 35. Bit Descriptions for SPI_STATUS (Continued) read-only bits. INVALID_WRITE_ERROR is a sticky bit and is only cleared by writing it to 1. register. MB_PARTIAL_ERROR is a sticky bit and is only cleared by writing it to 1. register address. INVALID_ADDR_ERROR is a sticky bit and is only cleared by writing it to 1. Table 36. Bit Descriptions for DEVICE_STATUS event. This bit is not sticky, and is cleared once the COM overvoltage protection clamp deactivates. automatically cleared when read. ERROR is the logical OR of all bits in the SPI_STATUS register. 0: no interface error detected. 1: one or more interface errors detected. INX_CLAMP_FLAG bits are deasserted (that is, when all clamps are deactivated). 0: Inactive clamps. None of the IN0 to IN7 clamps were activated. 1: Active clamp(s). One or more of the IN0 to IN7 clamps were or are activated.
Table 37. Bit Descriptions for CLAMP_STATUS the corresponding overvoltage protection clamp deactivates. Table 38. Bit Descriptions for DEVICE_SETUP default. Disable the internal LDO regulator when driving VDD with an external 1.8V supply. 0: Internal LDO regulator disabled. 1: Internal LDO regulator enabled.
Table 39. Bit Descriptions for REF_CTRL option. Changing this bit on the LFCSP option has no effect. 0: Disables internal reference buffer. Table 40. Bit Descriptions for SEQ_CTRL and a maximum of 128 slots per sequence.
Table 41. Bit Descriptions for OSC_FREQ_REG rate for burst and autonomous modes.
Table 42. Bit Descriptions for STD_SEQ_CONFIG sequencer is enabled (see the Standard Sequencer Mode section). sequencer is enabled (see the Standard Sequencer Mode section). sequencer is enabled (see the Standard Sequencer Mode section). sequencer is enabled (see the Standard Sequencer Mode section). sequencer is enabled (see the Standard Sequencer Mode section). sequencer is enabled (see the Standard Sequencer Mode section). sequencer is enabled (see the Standard Sequencer Mode section). sequencer is enabled (see the Standard Sequencer Mode section).
Table 43. Bit Descriptions for CONFIG_INn independently to each INn channel. 0x0: Single-ended mode. Converts INn with respect to REFGND. 0x1: Pseudo differential mode. Converts INn with respect to COM. Table 44. Bit Descriptions for AS_SLOTn
Table 45. Bit Descriptions for OSC_EN_REG 0: Internal oscillator disabled. 1: Internal oscillator enabled. Table 46. Bit Descriptions for STATE_RESET_REG ensure proper device operation. Table 47. Bit Descriptions for ADC_SETUP 0: EOS triggers the stop state. 1: DRDY triggers the stop state. [1:0] ADC_MODE ADC mode select.
Table 47. Bit Descriptions for ADC_SETUP (Continued) Table 48. Bit Descriptions for ACC_MASK ACC_MASK_IN0 controls the masking of the IN0 accumulator, and so on. Table 49. Bit Descriptions for ACC_DEPTH_INn 16 samples from its corresponding channel. The depth can be set between 1 and 64 samples for each accumulator.
Table 50. Bit Descriptions for GP0_GP1_MODE 0x6: Accumulator data ready signal. 0x7: Accumulator overflow error signal. 0x8: Accumulator saturation error signal. 0x6: Accumulator data ready signal. 0x7: Accumulator overflow error signal. 0x8: Accumulator saturation error signal. Table 51. Bit Descriptions for GP2_GP3_MODE
Table 51. Bit Descriptions for GP2_GP3_MODE (Continued) 0x6: Accumulator data ready signal. 0x7: Accumulator overflow error signal. 0x8: Accumulator saturation error signal. 0x6: Accumulator data ready signal. 0x7: Accumulator overflow error signal. 0x8: Accumulator saturation error signal. Table 52. Bit Descriptions for GPIO_READ configured as a logic input with the GP3_MODE setting. configured as a logic input with the GP2_MODE setting. configured as a logic input with the GP1_MODE setting. configured as a logic input with the GP0_MODE setting.
Table 53. Bit Descriptions for ACC_STS_FULL number of samples in the accumulator is equal to the user-programmed accumulator depth (ACC_DEPTH + 1). Table 54. Bit Descriptions for ACC_STS_OVR channel's accumulator experienced an overrun event since the most recent state reset. Table 55. Bit Descriptions for ACC_STS_SAT read back 1 when a saturation error occurred since the most recent state reset.
Table 56. Bit Descriptions for ACC_STATUS_INn Each channel has a corresponding 16-bit averaged data register, ranging from AVG_IN0 (at Address 0x0201) to AVG_IN7 (at Address 0x020F). Table 57. Bit Descriptions for AVG_INn
AVG_STS_IN7 (at Address 0x0237). Table 58. Bit Descriptions for AVG_STS_INn Table 59. Bit Descriptions for ACC_INn
Table 60. Bit Descriptions for ACC_STS_INn