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Pseudo Differential Input, 1 MSPS/500 kSPS, Dual, Simultaneous Sampling, 16-Bit, SAR ADCs Data Sheet AD4682/AD4683 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Dual simultaneous sampling Pseudo differential analog inputs Throughput conversion rate
1 MSPS for the AD4682
SNR (typical) 87.5 dB, VREF = 3.3 V external 93.4 dB with RES = 1 and OSR = ×8 On-chip oversampling function Alert function Resolution boost function INL error (maximum): 2.5 LSBs
2.5 V internal reference
High speed serial interface −40°C to +125°C operation 3 mm × 3 mm, 16-lead LFCSP
APPLICATIONS
Motor control position feedback Motor control current sense Sonar Power quality Data acquisition systems Erbium doped fiber amplifier (EDFA) applications Inphase (I) and quadrature (Q) demodulation GENERAL DESCRIPTION The AD4682 and the AD4683 are a 16-bit, pin-compatible family of dual, simultaneous sampling, high speed, low power, successive approximation register (SAR), analog-to-digital converters (ADCs) that operate from a 3.0 V to 3.6 V power supply and feature throughput rates up to 1 MSPS for the AD4682 and 500 kSPS for the AD4683. The analog input type is pseudo differential and is sampled and converted on the falling edge of CS. Integrated on-chip oversampling blocks improve dynamic range and reduce noise at lower bandwidths. A buffered internal 2.5 V reference is included. Alternatively, an external reference up to 3.3 V can be used. The conversion process and data acquisition use standard control inputs that allow simple interfacing to microprocessors or digital signal processors (DSPs). The devices are compatible with 1.8 V, 2.5 V, and 3.3 V interfaces, using a separate logic supply. COMPANION PARTS ADC Drivers: ADA4896-2, ADA4940-2, ADA4807-2, LTC6227 Voltage References: ADR4533 (3.3 V), ADR4525 (2.5 V) Low Dropout Regulators: ADP166, ADP7104, ADP7182 Additional companion products on the AD4682 and AD4683 product pages Table 1. Related Devices in the Family
Rev. 0 | Page 2 of 30 TABLE OF CONTENTS
REVISION HISTORY
10/2020—Revision 0: Initial Version
Rev. 0 | Page 3 of 30 SPECIFICATIONS AD4682, fSAMPLE = 500 kSPS for the AD4683, TA = −40°C to +125°C, and no oversampling enabled, unless otherwise noted. FS is full scale. Multifunction pin names may be referenced by their relevant function only. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits THROUGHPUT CONVERSION RATE AD4682 1 MSPS AD4683 500 kSPS DC ACCURACY No Missing Codes 16 Bits Differential Nonlinearity (DNL) Error −1.0 ±0.5 +1.0 LSB Integral Nonlinearity (INL) Error −2.5 ±1 +2.5 LSB Gain Error −40°C to +125°C −0.06 ±0.02 +0.06 % FS Gain Error Temperature Drift −3 ±1 +3 ppm/°C Gain Error Match 0.025 +0.07 % FS Offset Error −0.5 ±0.05 +0.5 mV Offset Temperature Drift −5 ±1 +5 µV/°C Offset Error Match −40°C to +125°C 0.05 +0.5 mV AC ACCURACY Input frequency (fIN) = 1 kHz Dynamic Range VREF = 3.3 V external 88 dB 86 dB Oversampled Dynamic Range Oversampling ratio (OSR) = ×4 91.8 dB Signal-to-Noise Ratio (SNR) VREF = 3.3 V external 85 87.5 dB 84 86 dB OS_MODE = 1, OSR = ×8, RES = 1 93.4 dB fIN = 100 kHz 85.3 dB Spurious-Free Dynamic Range (SFDR) 101 dB Total Harmonic Distortion (THD) −100 dB fIN = 100 kHz −97 dB Signal-to-Noise-and-Distortion (SINAD) VREF = 3.3 V external 84.5 87 dB 83.5 85.5 dB Channel to Channel Isolation −110 dB ANALOG INPUT Voltage Range (AINx+) to (AINx−) −VREF/2 +VREF/2 V Absolute Input Voltage Range AINx+ −0.1 VREF + 0.1 V Common-Mode Input Range AINx− VREF/2 ± 0.075 V Common-Mode Rejection Ratio (CMRR) fIN = 500 kHz −70 dB DC Leakage Current 0.1 1 µA Input Capacitance When in track mode 18 pF When in hold mode 5 pF SAMPLING DYNAMICS Input Bandwidth At −0.1 dB 6 MHz At −3 dB 25 MHz Aperture Delay 2 ns Aperture Delay Match 26 100 ps Aperture Jitter 20 ps
Rev. 0 | Page 4 of 30 Parameter Test Conditions/Comments Min Typ Max Unit REFERENCE INPUT AND OUTPUT VREF Input Voltage Range External reference 2.49 3.4 V Current External reference AD4682 1 MSPS 0.26 0.29 mA AD4683 500 kSPS 0.23 0.26 mA VREF Output Voltage −40°C to +125°C 2.495 2.5 2.505 V VREF Temperature Coefficient 5 10 ppm/°C VREF Noise 7 µV rms DIGITAL INPUTS (SCLK, SDI, AND CS) Logic Levels Input Voltage Low (VIL) 0.2 × VLOGIC V High (VIH) 0.8 × VLOGIC V Input Current Low (IIL) −1 +1 µA High (IIH) −1 +1 µA DIGITAL OUTPUTS (SDOA AND SDOB/ALERT) Output Coding Twos complement Bits Output Voltage Low (VOL) Sink current (ISINK) = 300 µA 0.4 V High (VOH) Source current (ISOURCE) = −300 µA VLOGIC − 0.3 V Floating State Leakage Current ±1 µA Output Capacitance 10 pF POWER SUPPLIES VCC 3.0 3.3 3.6 V External reference = 3.3 V 3.2 3.3 3.6 V VLOGIC 1.65 3.6 V VCC Current (IVCC) Normal Mode (Operational) AD4682, 1 MSPS 7.28 8.4 mA AD4683, 500 kSPS 4.76 5.6 mA Normal Mode (Static) 2.3 2.8 mA Shutdown Mode 101 200 µA VLOGIC Current (IVLOGIC) SDOA and SDOB at 0x1FFF Normal Mode (Operational) AD4682, 1 MSPS 884 950 µA AD4683, 500 kSPS 438 470 µA Normal Mode (Static) 10 200 nA Shutdown Mode 10 200 nA Power Dissipation Total Power (PTOTAL) (Operational) 83 107 mW VCC Power (PVCC) Normal Mode (Operational) AD4682, 1 MSPS 26.2 30.3 mW AD4683, 500 kSPS 17.2 20.2 mW Normal Mode (Static) 8 11 mW Shutdown Mode 365 720 µW VLOGIC Power (PVLOGIC) SDOA and SDOB at 0x1FFF Normal Mode (Operational) AD4682, 1 MSPS 3.2 3.5 mW AD4683, 500 kSPS 1.6 1.7 mW Normal Mode (Static) 36 720 nW Shutdown Mode 36 720 nW
Rev. 0 | Page 5 of 30 TIMING SPECIFICATIONS Figure 37, Figure 38, and Figure 39 for the timing diagrams. Multifunction pin names may be referenced by their relevant function only. Table 3. Parameter Min Typ Max Unit Description tCYC Time between conversions 1 µs AD4682 2 µs AD4683 tSCLKED 190 ns CS falling edge to first SCLK falling edge tSCLK 25 ns SCLK period tSCLKH 10 ns SCLK high time tSCLKL 10 ns SCLK low time tCSH 10 ns CS pulse width tQUIET Interface quiet time prior to conversion 500 ns AD4682 1500 ns AD4683 tSDOEN CS low to SDOA and SDOB/ALERT enabled 6 ns VLOGIC ≥ 2.25 V 8 ns 1.65 V ≤ VLOGIC < 2.3 V tSDOH 3 ns SCLK rising edge to SDOA and SDOB/ALERT hold time tSDOS SCLK rising edge to SDOA and SDOB/ALERT setup time 6 ns VLOGIC ≥ 2.25 V 8 ns 1.65 V ≤ VLOGIC < 2.3 V tSDOT 8 ns CS rising edge to SDOA and SDOB/ALERT high impedance tSDIS 1 ns SDI setup time prior to SCLK falling edge tSDIH 1 ns SDI hold time after SCLK falling edge tSCLKCS 0 ns SCLK rising edge to CS rising edge tCONVERT 190 ns Conversion time tACQUIRE ns Acquire time 810 ns AD4682 1810 ns AD4683 tRESET Valid time to start conversion after software reset 250 ns Valid time to start conversion after soft reset 800 ns Valid time to start conversion after hard reset tPOWERUP Supply active to conversion 5 ms First conversion allowed 11 ms Settled to within 1% with internal reference 5 ms Settled to within 1% with external reference tREGWRITE 5 ms Supply active to register read write access allowed tSTARTUP Exiting shutdown mode to conversion 11 ms Settled to within 1% with internal reference 10 µs Settled to within 1% with external reference tALERTS 220 ns Time from CS to ALERT indication tALERTC 12 ns Time from CS to ALERT clear
operational section of this specification is not implied. extended periods may affect product reliability. PCB thermal design is required. the junction to case thermal resistance. Table 5. Thermal Resistance
1 Test Condition 1: thermal impedance simulated values are based on
JEDEC 2S2P thermal test board four thermal vias. See JEDEC JESDS-51. ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 6. AD4682 and AD4683, 16-Lead LFCSP
- EXPOSED PAD. FOR PROPER OPERATION OF THE DEVICE,
CONNECT THE EXPOSED PAD TO GROUND. Figure 6. Pin Configuration Table 7. Pin Function Descriptions 1, 10 GND Ground Reference Points. The GND pins are the ground reference points for all circuitry on the device. 2 VLOGIC Logic Interface Supply Voltage, 1.65 V to 3.6 V. Decouple VLOGIC to GND with a 1 µF capacitor. capacitor. The voltage at REGCAP is 1.9 V typical. 4 VCC Power Supply Input Voltage, 3.0 V to 3.6 V. Decouple VCC to GND using a 1 µF capacitor. connected to VREF/2, and the AINB+ voltage range is from 0 V to VREF. connected to VREF/2, and the AINA+ voltage range is from 0 V to VREF. the device is configured accordingly. Alternatively, an external reference of 2.5 V to 3.3 V can be input to REFIO. options. Apply a 1 µF capacitor from REFIO to GND. and the AD4683 and framing the serial data transfer. or data from any of the on-chip registers. SDOB functions as a serial data output pin to access the ADC B conversion results. ALERT operates as an alert pin going low to indicate that a conversion result exceeded a configured threshold. 15 SDI Serial Data Input. SDI provides the data written to the on-chip control registers. 16 SCLK Serial Clock Input. SCLK is for data transfers to and from the ADC. EPAD Exposed Pad. For proper operation of the device, connect the exposed pad to ground.
Rev. 0 | Page 13 of 30 TERMINOLOGY Differential Nonlinearity (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. DNL is often specified in terms of resolution for which no missing codes are guaranteed. Integral Nonlinearity (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Gain Error The first transition (from 100 … 000 to 100 … 001) occurs at a level ½ LSB above nominal negative full scale. The last transition (from 011 … 110 to 011 … 111) occurs for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Gain Error Temperature Drift Gain error temperature drift is the gain error change due to a temperature change of 1°C. Gain Error Match Gain error matching is the difference in negative full-scale error between the input channels and the difference in positive full-scale error between the input channels. Offset Error Offset error is the difference between the ideal midscale voltage,
0 V, and the actual voltage producing the midscale output code,
0 LSB. Offset Temperature Drift Offset temperature drift is the zero error change due to a temperature change of 1°C. Offset Error Match Offset error match is the difference in zero error between the input channels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in dB, between the rms amplitude of the input signal and the peak spurious signal. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Signal-to-Noise-and-Distortion (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in dB. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of AINx+ and AINx− of frequency, f. The value for CMRR is expressed in dB. CMRR = 10log(PADC_IN/PADC_OUT) where: PADC_IN is the common-mode power at the frequency, f, applied to the AINx+ and AINx− inputs. PADC_OUT is the power at the frequency, f, in the ADC output. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the falling edge of the CS input and when the input signal is held for a conversion. Aperture Delay Match Aperture delay match is the difference of the aperture delay between ADC A and ADC B. Aperture Jitter Aperture jitter is the variation in aperture delay.
The AD4682 and the AD4683 can use a typical 2.5 V to 3.3 V VREF. AD4683 are shown in Figure 34. Figure 34. ADC Ideal Transfer Function (FSR = Full-Scale Range) Table 8. LSB Size
the devices and must be connected to the PCB ground. optimal performance is achieved. coupling of the AD4682 and the AD4683. on AINA+ and AINB+, and a VREF/2 voltage on AINA− and AINB−. however, and must be ignored. Table 9. Signal Chain Components
Figure 35. Typical Application Circuit
registers for controlling the operational mode of the device. oversampling function on chip, rolling average oversampling. the CONFIGURATION1 register. output data rate to stay the same. the Resolution Boost section for further details. from the FIFO, added together, and the result is divided by n. enabled, the performance of the ADC can exceed the 16-bit level. conversion result size for the AD4682 and the AD4683 is 18 bits. In this mode, 18 SCLKs are required to propagate the data. Table 10. AD4682 Rolling Average Oversampling Performance Overview
and the bus is taken out of three-state. on-board oscillator and is independent of the SCLK signal. sections to ensure proper operation. output pins. The next conversion also initiates at this point. shifts out of the device under the control of the SCLK input. SDOA and SDOB/ALERT pins to a high impedance state. data access must be completed within a single frame. Table 11. Number of SCLK Cycles, n, Required for Reading 1CONSULT TABLE 11 FOR VALUES FOR n, THE NUMBER OF SCLK PULSES REQUIRED. Figure 40. Reading Conversion Results
Rev. 0 | Page 24 of 30 CRC The AD4682 and the AD4683 have CRC checksum modes that can improve interface robustness by detecting errors in data transmissions. The CRC feature is independently selectable for SPI reads and SPI writes. For example, the CRC function for SPI writes can be enabled to prevent unexpected changes to the device configuration but disabled on SPI reads, therefore maintaining a higher throughput rate. The CRC feature is controlled by the programming of the CRC_W bit and CRC_R bits in the CONFIGURATION1 register. CRC Read If enabled, a CRC is appended to the conversion result or register reads and consists of an 8-bit word. The CRC is calculated in the conversion result for ADC A and ADC B and is output on SDOA. A CRC is also calculated and appended to register read outputs. The CRC read function can be used in 2-wire SPI mode, 1-wire SPI mode, and resolution boost mode. CRC Write To enable the CRC write function, set the CRC_W bit in the CONFIGURATION1 register to 1. To set the CRC_W bit to 1 to enable the CRC feature, ensure the request frame has a valid CRC appended to the frame. After the CRC feature is enabled, all register write requests are ignored unless the requests are accompanied by a valid CRC command, requiring a valid CRC to both enable and disable the CRC write feature. CRC Polynomial For CRC checksum calculations, the following polynomial is always used: x8+ x2 + x + 1. The following is an example of how to generate the checksum on a conversion read. The 16-bit data conversion result of the two channels is combined to produce 32-bit data. The 8 MSBs of the 32-bit data are inverted and then left shifted by eight bits to create a number ending in eight logic zeros. The polynomial is aligned such that its MSB is adjacent to the leftmost Logic 1 of the data. An exclusive OR (XOR) function is applied to the data to produce a new, shorter number. The polynomial is again aligned such that its MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process repeats until the original data is reduced to a value less than the polynomial, which is the 8-bit checksum. For example, this polynomial is 100000111. Let the original data of two channels be 0xAAAA and 0x5555, that is, 1010 1010 1010 1010 and 0101 0101 0101 0101. The data of the two channels is then appended, including eight zeros on the right. The data then becomes 1010 1010 1010 1010 0101 0101 0101 0101 0000 0000. Table 12 shows the CRC calculation of 16-bit two-channel data. In the final XOR operation, the reduced data is less than the polynomial. Therefore, the remainder is the CRC for the assumed data.
Table 12. Example CRC Calculation for 16-Bit Two-Channel Data Figure 46. CRC Operation
The AD4682 and the AD4683 have user programmable on-chip registers for configuring the device. (R/W) or read only (R). Any read request to a write only register is ignored, and any write request to a read only register is ignored. listed in Table 13, is considered an NOP, and the data transmitted in the next SPI frame are the conversion results. Table 13. Register Summary register data is available to be read during the next read operation. Table 14. Addressing Register Format Table 15. Bit Descriptions for Addressing Registers from the designated register, if the register is a valid address. D14 to D12 REGADDR When WR = 1, the contents of REGADDR determine the register for selection as outlined in Table 13. output on the SDOA pin during the next interface access. interface access results in the conversion results being read back. equal to 1 and the REGADDR data bits contain a valid address.
Enable Alert Indicator Function. Table 16. Bit Descriptions for CONFIGURATION1 section for further details. mode. Rolling average oversampling mode supports oversampling ratios of ×2, ×4, and ×8. 3 ALERT_EN Enable Alert Indicator Function. This alert function is enabled when the SDO bit = 1. Otherwise, the ALERT_EN bit is ignored. the resolution is set to default resolution. 0: selects internal reference. 1: selects external reference.
Table 17. Bit Descriptions for CONFIGURATION2 section for further details. 0: 2-wire. Conversion data are output on both the SDOA and SDOB/ALERT pins. 1: 1-wire. Conversion data are output on the SDOA pin only. 0x3C performs a soft reset that resets some blocks. Register contents remain unchanged. 0xFF performs a hard reset that resets all possible blocks in the AD4682 or the AD4683. Register contents are set to defaults. All other values are ignored. Table 18. Bit Descriptions for ALERT section for further details. sticky and remains set until the register is read.
sticky and remains set until the register is read. sticky and remains set until the register is read. sticky and remains set until the register is read. sticky and remains set until the register is read. Table 19. Bit Descriptions for ALERT_LOW_THRESHOLD section for further details. Table 20. Bit Descriptions for ALERT_HIGH_THRESHOLD section for further details. converter result is below ALERT_HIGH_THRESHOLD.
0.05 MAX
0.02 NOM
0.15 REF
0.55 REF
Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP] 2 Use the EVAL-AD7383FMCZ to evaluate the AD4682 and the AD4683. registered trademar ks a re the pro perty of their respecti ve own ers.