DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 52
Technical content
24-Bit, 2 MSPS/500 kSPS, Dual Channel SAR ADCs Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►High performance ►Throughput: 2 MSPS (AD4630-24) or 500 kSPS (AD4632-24) per channel maximum ►INL: ±0.9 ppm maximum from −40°C to +125°C ►SNR: 105.7 dB typical ►THD: −127 dB typical ►NSD: −166 dBFS/Hz typical ►Low power ►15 mW per channel at 2 MSPS ►5 mW per channel at 500 kSPS ►1.5 mW per channel at 10 kSPS ►Easy Drive features reduce system complexity ►Low 0.6 μA input current for dc inputs at 2 MSPS ►Wide input common-mode range: −(1/128) × VREF to +(129/128) × VREF ►Flexible external reference voltage range: 4.096 V to 5 V ►Accurate integrated reference buffer with 2 μF bypass capacitor ►Programmable block averaging filter with up to 216 decimation ►Extended sample resolution to 30 bits ►Overrange and synchronization bits ►Flexi-SPI digital interface ►1, 2, or 4 SDO lanes per channel allows slower SCK ►Echo clock mode simplifies use of digital isolator ►Compatible with 1.2 V to 1.8 V logic ►7 mm × 7 mm 64-Ball CSP_BGA package with internal supply and reference capacitors to help reduce system footprint
APPLICATIONS
►Automatic test equipment ►Digital control loops ►Medical instrumentation ►Seismology ►Semiconductor manufacturing ►Scientific instrumentation FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram ble decimation ratio can increase dynamic range up to 153 dB. simplifying signal conditioning requirements and system calibration. component count, and lessening sensitivity to board layout.
Data Sheet AD4630-24/AD4632-24 TABLE OF CONTENTS analog.com Rev. A | 2 of 52 Sample Conversion Timing and Data
REVISION HISTORY
7/2022—Rev. 0 to Rev. A
Data Sheet AD4630-24/AD4632-24 TABLE OF CONTENTS analog.com Rev. A | 3 of 52 Changes to Host Clock Mode Section, Figure 54 Title, Dual Data Rate Section, 1-Lane Output Data Changes to 4-Lane Output Data Clocking Mode Section, Interleaved Lane Output Data Clocking Mode Changes to Host Clock Mode Timing Section Title, 1-Lane, Host Clock Mode, SDR Section, and 1- 11/2021—Revision 0: Initial Version
for the AD4630-24/AD4632-24, and all specifications TMIN to TMAX, unless otherwise noted. Typical values are at TA = 25°C. Table 1. Specifications
4.096 V 104 dB
4.096 V 130 dB
4.096 V −130 dB
and 500 kSPS for the AD4632-24. 2 See the low frequency noise plot in Figure 24. 1/f noise is canceled internally by auto-zeroing. Noise spectral density is substantially uniform from dc to fS/2. 3 When VIO < 1.4V, Bit IO2X must be set to 1. See the Output Driver Register section. timing voltage levels. For VIO < 1.4 V, Bit IO2X must be set to 1. Table 2. Digital Timing Interface
guaranteed by characterization and design. and 500 kSPS for the AD4632-24. Figure 2. Voltage Levels for Timing Table 3. Register Read/Write Timing
Table 4. SPI Compatible Mode Timing Figure 6. SPI Clocking Mode 1-Lane SDR Timing Table 5. Echo Clock Mode Timing, SDR, 1-Lane
Table 8. Absolute Maximum Ratings ing conditions for extended periods may affect product reliability. Table 9. Thermal Resistance sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 10. AD4630-24/AD4632-24, 64-Ball CSP_BGA damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 11. Pin Configuration Table 11. Pin Function Descriptions (referred to GND). To disable the reference buffer, tie REFIN to GND and drive REF with 4.096 V to 5 V. A7 RST DI Reset Input (Active Low). Asynchronous device reset. of the output driver register must be set to 1. B1 IN0+ AI Channel 0 Positive Analog Input. IOGND P VIO Ground. Connect to the same ground plane as GND. C1 IN0− AI Channel 0 Negative Analog Input. C7 SDO3 DO Channel 0 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. C8 SDO1 DO Channel 0 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. μF bypass capacitor inside the package. When using the internal reference buffer, do not connect REF. D7 SDO2 DO Channel 0 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. D8 SDO0 DO Channel 0 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK.
F1 IN1+ AI Channel 1 Positive Analog Input. F7 SDO6 DO Channel 1 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. F8 SDO4 DO Channel 1 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. G1 IN1− AI Channel 1 Negative Analog Input. G7 SDO7 DO Channel 1 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. G8 SDO5 DO Channel 1 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. H5 CS DI Chip Select Input (Active Low). H6 SDI DI Serial Data Input. 1 AI is analog input, P is power, DI is digital input, and DO is digital output.
Data Sheet AD4630-24/AD4632-24 TERMINOLOGY analog.com Rev. A | 20 of 52 Integral Nonlinearity (INL) Error INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 40). Differential Nonlinearity (DNL) Error In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. DNL is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error (ZE) Zero error is the difference between the ideal midscale voltage, 0 V, and the actual voltage producing the midscale output code, 0 LSB. Gain Error (GE) LSB above nominal negative full scale. The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of a full-scale input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. ENOB is related to SINAD as follows: ENOB = (SINAD dB − 1.76)/ 6.02. ENOB is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic compo- nents to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range (DR) Dynamic range is the rms voltage of a full-scale sine wave to the total rms voltage of the noise measured. The value for dynamic range is expressed in decibels. Dynamic range is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms voltage of a full-scale sine wave to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion (SINAD) Ratio SINAD is the ratio of the rms voltage of a full-scale sine wave to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 4.5 V p-p sine wave applied to the input common-mode voltage of frequency, f. C MRR d B = 10 × log P AD C _ I N / P AD C _ OU T where: PADC_IN is the common-mode power at the frequency, f, applied to the inputs. PADC_OUT is the power at the frequency, f, in the ADC output. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency, f. PSRR dB = 10 × log P V DD _ I N / P AD C _ OU T where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output.
constant is more than 12.5 ns (R × C > 12.5e-9). features available for each input channel. ing) when either or both inputs exceed the specified analog limits. representing the input voltage difference. …, 16. The filter is reset after processing each block of 2N samples. section for the data format when the filter is enabled. Figure 42. Frequency Response Examples for the Block Averaging Filter
1 Offset Registers section in the AD4630-24/AD4632-24 register
where 0x0000 ≤ CHx_USER_GAIN ≤ 0xFFFF. AD4630-24/AD4632-24 register map for more details.
Figure 44. Typical Application Circuit Diagrams
1.4 V, Bit IO2X in the output driver register must be set to 1
clocked out on up to four SDO lanes per channel (see Figure 49). describes the operation of the AD4630-24/AD4632-24 SPI. Figure 49. Multilane SPI registers of the AD4630-24/AD4632-24. nal determines the sampling rate of the AD4630-24/AD4632-24. The maximum frequency of the CNV clock is 2 MSPS. ►SDO0 through SDO7 (outputs). Data lanes to the host controller.
- The number of data lanes configured for each channel can be
behavior for each clocking mode. Table 13. BUSY/SCKOUT Pin Behavior vs. Clocking Mode signal. BUSY goes low when the conversion completes.
- Perform a readback from dummy Register Address 0x3FFF to
enter the register configuration mode.
- Readback from or write to the desired user register addresses.
- Exit the register configuration mode by writing 0x01 to Register
register updates to take effect.
- The quiet zone immediately before the rising edge of CNV is la-
SCK on the SPI and ease the timing requirements for the interface. overwritten with Sample N + 1. Figure 51. Example Timing for Data Transfer Zones
ADC channels. The channels cannot be configured independently. which the host controller uses its own clock to latch the output data. pulse for the last sample in the block. Figure 52. Typical Sample Cycle for SPI Clocking Mode
in the Data Clocking Requirements and Timing section. Requirements and Timing section. for SPI clocking mode, echo clock mode, and host clock mode. transfer can occur in either Zone 1 or Zone 2 (see Figure 51). ADC channels, reducing I/O requirements for the digital interface. Clocking Requirements and Timing section. Table 14. Supported Data Output Modes
1 SDO0 SDO4 SPI SDR only 24 or 32
2 SDO0, SDO1 SDO4, SDO5 SPI SDR only 24 or 32
4 SDO0, SDO1, SDO2,
Data Sheet AD4630-24/AD4632-24 LAYOUT GUIDELINES analog.com Rev. A | 39 of 52 The following layout guidelines are recommended to achieve maxi- mum performance out of the AD4630-24/AD4632-24: ►The AD4630-24/AD4632-24 contains internal 1 μF bypass ca- pacitors for VDD_5V and VDD_1.8V, while VIO contains an inter- nal 0.2 μF capacitor. Therefore, no external bypass capacitors are required, saving board space and reducing BOM count and layout sensitivity. ►Have all the analog signals flow in from the left side of the AD4630-24/AD4632-24 and all the digital signals to flow in and out from the right side of AD4630-24/AD4632-24 because this helps isolate analog signals from digital signals. ►Use a solid ground plane under the AD4630-24/AD4632-24 and connect all the analog ground (GND) pins and digital ground (IOGND) pins to the shared ground plane to avoid the formation of ground loops. ►Traces routed to either the REFIN pin or REF pins must be iso- lated/shielded from other signals. Avoid routing signals beneath the reference trace (REFIN or REF). The REF pins are connect- ed to an internal 2 µF capacitor, eliminating the need to place a decoupling capacitor on the output of the external reference buffer. If a noise reduction filter is placed between the output of the reference (or buffer) and the chosen reference input, the filter must be placed as close as possible to the AD4630-24/ AD4632-24.
write bits can be overwritten. Table 16. Register Summary
Interface configuration settings. Table 17. Bit Descriptions for INTERFACE_CONFIG_A 0: address accessed is decremented by one for each data byte when streaming. reset to their default values. Additional interface configuration settings. Table 18. Bit Descriptions for INTERFACE_CONFIG_B 0: streaming mode is enabled. The address decrements as successive data bytes are received. 1: single instruction mode is enabled.
Table 19. Bit Descriptions for DEVICE_CONFIG uniquely identify a given product. Table 20. Bit Descriptions for CHIP_TYPE Table 21. Bit Descriptions for PRODUCT_ID_L High byte of the product ID.
Table 22. Bit Descriptions for PRODUCT_ID_H Identifies product variations and device revisions. Table 23. Bit Descriptions for CHIP_GRADE This register can be used to test writes and reads. Table 24. Bit Descriptions for SCRATCH_PAD Table 25. Bit Descriptions for SPI_REVISION
Table 26. Bit Descriptions for VENDOR_L Table 27. Bit Descriptions for VENDOR_H Defines the length of the loop when streaming data. Table 28. Bit Descriptions for STREAM_MODE auto clears upon the end of that instruction.
Additional interface configuration settings. Table 29. Bit Descriptions for INTERFACE_CONFIG_C Status bits are set to 1 to indicate an active condition. The status bits can be cleared by writing a 1 to the corresponding bit location. Table 30. Bit Descriptions for INTERFACE_STATUS_A Table 31. Bit Descriptions for EXIT_CFG_MD
Table 32. Bit Descriptions for AVG 0x11 through 0x1F = invalid. Table 33. Bit Descriptions for OFFSET_CH0_LB Gain Registers section for a description of the gain parameter. Table 34. Bit Descriptions for OFFSET_CH0_MB Gain Registers section for a description of the gain parameter.
Table 35. Bit Descriptions for OFFSET_CH0_HB Gain Registers section for a description of the gain parameter. Table 36. Bit Descriptions for OFFSET_CH1_LB Gain Registers section for a description of the gain parameter value. Table 37. Bit Descriptions for OFFSET_CH1_MB Gain Registers section for a description of the gain parameter value. Table 38. Bit Descriptions for OFFSET_CH1_HB Gain Registers section for a description of the gain parameter value.
Table 39. Bit Descriptions for GAIN_CH0_LB Table 40. Bit Descriptions for GAIN_CH0_HB Table 41. Bit Descriptions for GAIN_CH1_LB Table 42. Bit Descriptions for GAIN_CH1_HB
Table 43. Bit Descriptions for MODES 10 = four lanes per channel. 11 = Channel 0 and Channel 1 interleaved on SDO0. 1 = DDR (only valid for echo clock and host clock modes). 000 = 24-bit differential data. 001 = 16-bit differential data + 8-bit common mode data. 010 = 24-bit differential data + 8-bit common mode data. 011 = 30-bit averaged differential data + OR bit + SYNC bit. 100 = 32-bit test data pattern (see the Test Pattern Registers section). Table 44. Bit Descriptions for OSCILLATOR AD4630-24/AD4632-24 based on the data-word size, number of active SDO lanes, and data rate mode (SDR or DDR). 00 = no divide (divide by 1).
Table 45. Bit Descriptions for IO 1 = double output driver strength. 0 = normal output driver strength. Table 46. Bit Descriptions for TEST_PAT_BYTE0 Table 47. Bit Descriptions for TEST_PAT_BYTE1 Table 48. Bit Descriptions for TEST_PATBYTE2
Table 49. Bit Descriptions for TEST_PAT_BYTE3 Table 50. Bit Descriptions for DIG_DIAG Table 51. Bit Descriptions for DIG_ERR
registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 60. 64-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 2 The EVAL-AD4630-24-KTZ and EVAL-AD4630-24FMCZ can be used to evaluate the AD4632-24.