ADN4600 AD | Alldatasheet
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4.25 Gbps, 8 × 8,
Asynchronous Crossp oint Switch ADN4600 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
FEATURES
Full 8 × 8 crossbar connectivity Fully buffered signal path supports multicast and broadcast operation Optimized for dc to 4.25 Gbps data Programmable receive equalization Compensates for up to 30 in. of FR4 @ 4.25 Gbps Programmable transmit pre-emphasis/de-emphasis Compensates for up to 30 in. of FR4 @ 4.25 Gbps Flexible 1.8 V to 3.3 V core supply Per lane positive/negative (P/N) pair inversion for routing ease Low power: 125 mW/channel at 4.25 Gbps DC- or ac-coupled differential CML inputs Programmable CML output levels 50 Ω on-chip termination −40°C to +85°C temperature range operation Supports 8b10b, scrambled or uncoded nonreturn-to-zero (NRZ) data I 2C control interface Package: 64-lead LFCSP
APPLICATIONS
1×, 2×, 4× FibreChannel XAUI Gigabit Ethernet over backplane 10GBase-CX4 InfiniBand® 50 Ω cables FUNCTIONAL BLOCK DIAGRAM RECEIVE EQUALIZATION CROSSPOINT ARRAY TRANSMIT PRE-EMPHASIS CONTROL LOGIC ADN4600 IP[7:0] IN[7:0] ADDR[1:0] SCL SDA RESETB OP[7:0] ON[7:0] 07061-001 EQ PE Figure 1. GENERAL DESCRIPTION The ADN4600 is an asynchronous, nonblocking crosspoint switch with eight differential PECL-/CML-compatible inputs with programmable equalization and eight differential CML outputs with programmable output levels and pre-emphasis or de-emphasis. The operation of this device is optimized for NRZ data at rates up to 4.25 Gbps. The receive inputs provide programmable equalization with nine settings to compensate for up to 30 in. of FR4 and programmable pre-emphasis with seven settings to compensate for up to 30 in. of FR4 at 4.25 Gbps. The ADN4600 nonblocking switch core implements an 8 × 8 crossbar and supports independent channel switching through the I 2C control interface. Every channel implements an asynchronous path supporting NRZ data rates from dc to 4.25 Gbps. Each channel is fully independent of other channels. The ADN4600 has low latency and very low channel-to-channel skew. The main application for the ADN4600 is to support switching on the backplane, line card, or cable interface sides of serial links. The ADN4600 is packaged in a 9 mm × 9 mm, 64-lead LFCSP package and operates from −40°C to +85°C.
Rev. 0 | Page 2 of 2 TABLE OF CONTENTS
REVISION HISTORY
6/08—Revision 0: Initial Version
Rev. 0 | Page 3 of 3 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VCC = 1.8 V , VEE = 0 V , VTTI = VTTO = VCC, RL = 50 Ω, differential output swing = 800 mV p-p differential, 4.25 Gbps, PRBS 27 − 1, TA = 25°C, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Data Rate per Channel In NRZ format 4.25 Gbps Deterministic Jitter Data rate < 4.25 Gbps; BER = 1e − 12 30 ps p-p Random Jitter VCC = 1.8 V 1.5 ps rms Residual Deterministic Jitter with Receive Equalization Data rate < 3.25 Gbps; 0 in. to 30 in. FR4 0.16 UI Data rate < 4.25 Gbps; 0 in. to 30 in. FR4 0.20 UI Residual Deterministic Jitter with Transmit Pre-Emphasis Data rate < 3.25 Gbps; 0 in. to 30 in. FR4 0.13 UI Data rate < 4.25 Gbps; 0 in. to 30 in. FR4 0.18 UI Output Rise/Fall Time 20% to 80% 75 ps Channel-to-Channel Skew 50 ps Propagation Delay 1 ns OUTPUT PRE-EMPHASIS Equalization Method One-tap programmable pre-emphasis Maximum Boost 800 mV p-p output swing 6 dB 200 mV p-p output swing 12 dB Pre-Emphasis Tap Range Minimum 2 mA Maximum 12 mA INPUT EQUALIZATION Minimum Boost EQBY = 1 1.5 dB Maximum Boost Maximum boost occurs @ 2.125 GHz 22 dB Number of Equalization Steps 8 Steps Gain Step Size 2.5 dB INPUT CHARACTERISTICS Input Voltage Swing Differential, VICM1 = VCC − 0.6 V; VCC = 3.3 V 300 2000 mV p-p Input Voltage Range Single-ended absolute voltage level, VL minimum VEE + 0.4 V p-p Single-ended absolute voltage level, VH maximum VCC + 0.5 V p-p Input Resistance Single-ended 45 50 55 Ω Input Return Loss Measured at 2.5 GHz 5 dB OUTPUT CHARACTERISTICS Output Voltage Swing @ dc, differential, PE = 0, default, VCC = 1.8 V 635 740 870 mV p-p @ dc, differential, PE = 0, default, VCC = 3.3 V 800 mV p-p @ dc, differential, PE = 0, min output level2, VCC = 1.8 V 100 mV p-p @ dc, differential, PE = 0, min output level2, VCC = 3.3 V 100 mV p-p @ dc, differential, PE = 0, max output level2, VCC = 1.8 V 1300 mV p-p @ dc, differential, PE = 0, max output level2, VCC = 3.3 V 1800 mV p-p Output Voltage Range Single-ended absolute voltage level, TxHeadroom = 0; VL min V CC − 1.1 V Single-ended absolute voltage level, TxHeadroom = 0; VH max V CC + 0.6 V Single-ended absolute voltage level, TxHeadroom = 1; V L min V CC − 1.2 V Single-ended absolute voltage level, TxHeadroom = 1; VH max V CC + 0.6 V Output Current Minimum output current per channel 2 mA Maximum output current per channel, VCC = 1.8 V 21 Output Resistance Single ended 45 50 55 Ω Output Return Loss Measured at 2.5 GHz 5 dB
Rev. 0 | Page 4 of 4 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range VCC V EE = 0 V 1.7 1.8 3.6 V DVCC V EE = 0 V, DVCC ≤ (VCC + 1.3 V) 3.0 3.3 3.6 V VTTI (V EE + 0.4 V + 0.5 × VID) < VTTI < (VCC + 0.5 V) VEE + 0.4 1.8 3.6 V VTTO (V CC − 1.1 V + 0.5 × VOD) < VTTO < (VCC + 0.5 V) VCC − 1.1 1.8 3.6 V Supply Current3 ITTO All outputs enabled 63 69 mA ICC All outputs enabled 460 565 mA IEE All outputs enabled 586 mA ITTO Single channel enabled 16 18 mA ICC Single channel enabled 173 214 mA IEE Single channel enabled 205 mA LOGIC CHARACTERISTICS Input High (VIH) DVCC = 3.3 V 2.5 V Input Low (VIL) 1.0 V Output High (VOH) 2.5 V Output Low (VOL) 1.0 V THERMAL CHARACTERISTICS Operating Temperature Range −40 +85 °C θJA 22 °C/W 1 VICM is the input common-mode voltage. 2 Programmable via I2C. 3 Assumes dc-coupled outputs. For ac-coupled outputs, ITTO currents will double.
Table 2. I2C Timing Parameters Figure 2. I2C Timing Diagram
Rev. 0 | Page 6 of 6 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Rating VCC to VEE 3.7 V VTTI V CC + 0.6 V VTTO V CC + 0.6 V Internal Power Dissipation 4.26 W Differential Input Voltage 2.0 V Logic Input Voltage VEE − 0.3 V < VIN < VCC + 0.6 V Storage Temperature Range −65°C to +125°C Lead Temperature 300°C ESD CAUTION
- PAD ON BOTTOM OF PACKAGE MUST BE CONNECTED TO VEE.
Figure 3. Pin Configuration Table 4. Pin Function Descriptions
1 RESETB Control Reset Input (Active Low)
47 SDA Control I2C Control Interface Data Input/Output
48 SCL Control I2C Control Interface Clock Input
49 ADDR0 Control I2C Control Interface Address LSB
50 ADDR1 Control I2C Control Interface Address MSB
Table 5. Common Input Voltage Levels Table 6. Receive Equalizer Boost vs. Setting Table 7. Equalization Control Registers
is passed into the second rank by strobing the XPT update register. Table 8. Switch Core Control and Status Registers Table 9. Switch Core Temporary Registers
equal to or greater than 2.5 V . FR4 trace compensated for by each setting. of interest. The supported output levels are shown in Table 12. other settings are not supported. TX[7:0] Output Level Control[1:0] registers (per channel). low selects pre-emphasis control from the optimized map. Figure 29. Simplified Output Structure Table 10. Transmit Pre-Emphasis Boost and Overshoot vs. Setting Table 11. Transmitters Control Registers Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Def.
Table 12. Output Level Programming
Rev. 0 | Page 18 of 18 VOD (mV) V D Peak (mV) PE (dB) I TOT (mA) Tx[7:0] Output Level Contro l 0 Tx[7:0] Output Level Control 1 400 700 4.86 28 0x33 0xC4 400 800 6.02 32 0x44 0xC4 400 900 7.04 36 0x55 0xC4 400 1000 7.96 40 0x66 0xC4 450 450 0.00 18 0x00 0xC5 450 550 1.74 22 0x11 0xC5 450 650 3.19 26 0x22 0xC5 450 750 4.44 30 0x33 0xC5 450 850 5.52 34 0x44 0xC5 450 950 6.49 38 0x55 0xC5 450 1050 7.36 42 0x66 0xC5 500 500 0.00 20 0x00 0xD5 500 600 1.58 24 0x11 0xD5 500 700 2.92 28 0x22 0xD5 500 800 4.08 32 0x33 0xD5 500 900 5.11 36 0x44 0xD5 500 1000 6.02 40 0x55 0xD5 500 1100 6.85 44 0x66 0xD5 550 550 0.00 22 0x00 0xD6 550 650 1.45 26 0x11 0xD6 550 750 2.69 30 0x22 0xD6 550 850 3.78 34 0x33 0xD6 550 950 4.75 38 0x44 0xD6 550 1050 5.62 42 0x55 0xD6 550 1150 6.41 46 0x66 0xD6 600 600 0.00 24 0x00 0xE6 600 700 1.34 28 0x11 0xE6 600 800 2.50 32 0x22 0xE6 600 900 3.52 36 0x33 0xE6 600 1000 4.44 40 0x44 0xE6 600 1100 5.26 44 0x55 0xE6 600 1200 6.02 48 0x66 0xE6 650 650 0.00 26 0x01 0xE6 650 750 1.24 30 0x12 0xE6 650 850 2.33 34 0x23 0xE6 650 950 3.30 38 0x34 0xE6 650 1050 4.17 42 0x45 0xE6 650 1150 4.96 46 0x56 0xE6 700 700 0.00 28 0x02 0xE6 700 800 1.16 32 0x13 0xE6 700 900 2.18 36 0x24 0xE6 700 1000 3.10 40 0x35 0xE6 700 1100 3.93 44 0x46 0xE6 750 750 0.00 30 0x03 0xE6 750 850 1.09 34 0x14 0xE6 750 950 2.05 38 0x25 0xE6 750 1050 2.92 42 0x36 0xE6 800 800 0.00 32 0x04 0xE6 800 900 1.02 36 0x15 0xE6 800 1000 1.94 40 0x26 0xE6 850 850 0.00 34 0x05 0xE6 850 950 0.97 38 0x16 0xE6 900 900 0.00 36 0x06 0xE6
to transistor saturation and poor transmitter performance. Figure 30. Simplified Output Voltage Levels Diagram Table 13. Signal Levels and Common-Mode Shift for DC- and AC-Coupled Outputs
1 TxHeadroom = 1 is not an option at VTTO and VCC = 1.8 V. Table 14. Symbol Definitions for Output Levels vs. Setting
Each transmitter is equipped with disable and squelch controls. approximately 1 μs associated with re-enabling the transmitter. squelch in less than 100 ns. all 0s for this functionality. Table 15. Transmitters Squelch Control Registers
SCL input clock pin and the SDA bidirectional data pin. while the SCL line is high to indicate the end of a transfer. repeated start, or stop condition. specified. A diagram of the procedure is shown in Figure 31.
- Send a start condition (that is, while holding the SCL line
high, pull the SDA line low).
- Send the ADN4600 part address (seven bits), whose upper
bits are controlled by the ADDR1 and ADDR0 input pins. This transfer should be MSB first.
- Send the write indicator bit (0).
- Wait for the ADN4600 to acknowledge the request.
- Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
- Wait for the ADN4600 to acknowledge the request.
- Send the data (eight bits) to be written to the register
- Wait for the ADN4600 to acknowledge the request.
- Send a stop condition (that is, while holding the SCL line
high, pull the SDA line high) and release control of the bus.
- Send a repeated start condition (that is, while holding the
Step 2 in this procedure to perform another write.
- Send a repeated start condition (that is, while holding the
- Send a repeated start condition (that is, while holding the
same address set in Step 5 of the write procedure. Address 0x6D of an ADN4600 part with a slave address of 0x4B. end phase case shown corresponds with Step 9. condition is being sent, as is the case in Step 1 and Step 9. Figure 31. I2C Write Diagram
specified. A diagram of the procedure is shown in Figure 32.
- Send a start condition (that is, while holding the SCL line
high, pull the SDA line low).
- Send the ADN4600 part address (seven bits), whose upper
bits are controlled by the ADDR1 and ADDR0 input pins. This transfer should be MSB first.
- Send the write indicator bit (0).
- Wait for the ADN4600 to acknowledge the request.
- Send the register address (eight bits) from which data is to
2C Interface Data Transfers: Data Write section).
- Wait for the ADN4600 to acknowledge the request.
- Send a repeated start condition (that is, while holding the
SCL line high, pull the SDA line low).
- Send the ADN4600 part address (seven bits), whose upper
bits are controlled by the ADDR1 and ADDR0 input pins. This transfer should be MSB first.
- Send the read indicator bit (1).
- Wait for the ADN4600 to acknowledge the request.
- The ADN4600 then serially transfers the data (eight bits) held
in the register indicated by the address set in Step 5.
- Send a stop condition (that is, while holding the SCL line
high, pull the SDA line high) and release control of the bus.
- Send a repeated start condition (that is, while holding the
Transfers: Data Write section) to perform a write.
- Send a repeated start condition (that is, while holding the
- Send a repeated start condition (that is, while holding the
Address 0x6D of an ADN4600 part with a slave address of 0x4B. end phase case shown corresponds with Step 13. condition is being sent, as is the case in Step 1, Step 7, and Step 13.
- Sr = A REPEATED START WHERE THE SDA LINE IS BROUGHT HIGH BEFORE SCL IS RAISED.
Figure 32. I2C Read Diagram
Rev. 0 | Page 24 of 24 PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance. Power Supply Connections and Ground Planes Use of one low impedance ground plane is recommended. The VEE pins should be soldered directly to the ground plane to reduce series inductance. If the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance. The exposed pad should be connected to the VEE plane using plugged vias so that solder does not leak through the vias during reflow. Use of a 10 μF electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. It is recommended that 0.1 μF and 1 nF ceramic chip capacitors be placed in parallel at each supply pin for high frequency power supply decoupling. When using 0.1 μF and 1 nF ceramic chip capacitors, they should be placed between the IC power supply pins (VCC, VTTI, VTTO) and VEE, as close as possible to the supply pins. By using adjacent power supply and GND planes, excellent high frequency decoupling can be attained by using close spacing between the planes. This capacitance is given by C PLANE = 0.88εr A/d (pF) where: εr is the dielectric constant of the PCB material. A is the area of the overlap of power and GND planes (cm2). d is the separation between planes (mm). For FR4, εr = 4.4 and 0.25 mm spacing, C ~15 pF/cm2. Transmission Lines Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections. It is also necessary for the high speed pairs of differential input traces, as well as the high speed pairs of differential output traces, to be matched in length to avoid skew between the differential traces. Soldering Guidelines for Chip Scale Package The lands on the LFCSP are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central exposed pad. The pad on the printed circuit board should be at least as large as this exposed pad. The user must connect the exposed pad to VEE using plugged vias so that solder does not leak through the vias during reflow. This ensures a solid connection from the exposed pad to VEE.
Table 16. Basic Mode I2C Register Definitions
Table 17. Advanced Mode I2C Register Definitions
Rev. 0 | Page 27 of 27 Addr (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0xD1 TX2 Output Level Control 1 TX2 CTL SRC TX2_OLEV1[6:0] 0x40 0xD2 TX2 Output Level Control 0 TX2_OLEV0[6:0] 0x40 0xD3 TX2 Squelch Control SQUELCHb[3:0] DISABLEb[3:0] 0xFF 0xD9 TX3 Output Level Control 1 TX3 CTL SRC TX3_OLEV1[6:0] 0x40 0xDA TX3 Output Level Control 0 TX3_OLEV0[6:0] 0x40 0xDB TX3 Squelch Control SQUELCHb[3:0] DISABLEb[3:0] 0xFF 0xE1 TX7 Output Level Control 1 TX7 CTL SRC TX7_OLEV1[6:0] 0x40 0xE2 TX7 Output Level Control 0 TX7_OLEV0[6:0] 0x40 0xE3 TX7 Squelch Control SQUELCHb[3:0] DISABLEb[3:0] 0xFF 0xE9 TX6 Output Level Control 1 TX6 CTL SRC TX6_OLEV1[6:0] 0x40 0xEA TX6 Output Level Control 0 TX6_OLEV0[6:0] 0x40 0xEB TX6 Squelch Control SQUELCHb[3:0] DISABLEb[3:0] 0xFF 0xF1 TX5 Output Level Control 1 TX5 CTL SRC TX5_OLEV1[6:0] 0x40 0xF2 TX5 Output Level Control 0 TX5_OLEV0[6:0] 0x40 0xF3 TX5 Squelch Control SQUELCHb[3:0] DISABLEb[3:0] 0xFF 0xF9 TX4 Output Level Control 1 TX4 CTL SRC TX4_OLEV1[6:0] 0x40 0xFA TX4 Output Level Control 0 TX4_OLEV0[6:0] 0x40 0xFB TX4 Squelch Control SQUELCHb[3:0] DISABLEb[3:0] 0xFF
0.05 MAX
0.02 NOM
0.60 MAX
Figure 33. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] registered trademarks are the prop erty of their respective owners.