AD4311-1

AD4311-1 AD | Alldatasheet

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Technical content

Low Cost, Dual, High Current Output Line Driver with Shutdown ADA4311-1 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.

FEATURES

−3 dB bandwidth: 310 MHz, G = +5, RLOAD = 50 Ω Slew rate: 1050 V/μs, RLOAD = 50 Ω Wide output swing

20.6 V p-p differential, RLOAD of 100 Ω from 12 V supply

−98 dBc typical at 1 MHz, VOUT = 2 V p-p, G = +5, RLOAD = 100 Ω −72 dBc typical at 10 MHz, VOUT = 2 V p-p, G = +5, RLOAD = 100 Ω Power management and shutdown Control inputs CMOS level compatible Shutdown quiescent current: 1 mA/amplifier Selectable quiescent current: 1 mA to 11.8 mA/amplifier

APPLICATIONS

Home networking line drivers Twisted pair line drivers Power line communications (PLC) Video line drivers ARB line drivers I/Q channel amplifiers PIN CONFIGURATION NC = NO CONNECT +VS 1 NC 2 OUT A 3 –IN A 4 +IN A 5 OUT B10 –IN B9 +IN B8 PD17 PD06 ADA4311-1 06940-001 Figure 1. Thermally Enhanced, 10-Lead MINI_SO_EP Figure 2. Typical PLC Driver Application while driving low impedance loads. go to a high impedance state. MSOP with an exposed paddle for improved thermal conduction. temperature range of −40°C to +85°C.

Rev. 0 | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

8/07—Revision 0: Initial Version

Rev. 0 | Page 3 of 16 SPECIFICATIONS VS = 12 V , RF = 499 Ω (@ TA = 25°C, G = +5, RL = 100 Ω to VS/2), unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth VOUT = 0.1 V p-p, PD1 = 0, PD0 = 0, RLOAD = 50 Ω 310 MHz VOUT = 0.1 V p-p, PD1 = 0, PD0 = 1, RLOAD = 50 Ω 220 MHz VOUT = 0.1 V p-p, PD1 = 1, PD0 = 0, RLOAD = 50 Ω 140 MHz Full Power Bandwidth VOUT = 10.2 V p-p, PD1 = 0, PD0 = 0, RLOAD = 50 Ω 12.9 MHz Slew Rate VOUT = 2 V p-p, PD1 = 0, PD0 = 0 1050 V/μs VOUT = 2 V p-p, PD1 = 0, PD0 = 1 1050 V/μs VOUT = 2 V p-p, PD1 = 1, PD0 = 0 1000 V/μs NOISE/DISTORTION PERFORMANCE Differential Distortion (Worst Harmonic) fC = 1 MHz, VOUT = 2 V p-p PD1 = 0, PD0 = 0 −98 dBc PD1 = 0, PD0 = 1 −95 dBc PD1 = 1, PD0 = 0 −86 dBc fC = 10 MHz, VOUT = 2 V p-p PD1 = 0, PD0 = 0 −72 dBc PD1 = 0, PD0 = 1 −63 dBc PD1 = 1, PD0 = 0 −52 dBc fC = 20 MHz, VOUT = 2 V p-p PD1 = 0, PD0 = 0 −56 dBc PD1 = 0, PD0 = 1 −49 dBc PD1 = 1, PD0 = 0 −43 dBc Input Voltage Noise f = 100 kHz 2.4 nV/√Hz Input Current Noise f = 100 kHz 17 pA/√Hz DC PERFORMANCE Input Offset Voltage −3 +1 +3 mV Input Bias Current Noninverting Input −9 −2 +3 μA Inverting Input −4 +4.5 +16 μA Open-Loop Transimpedance RLOAD = 50 Ω 4 14 MΩ R LOAD = 100 Ω 15 35 MΩ Common-Mode Rejection 57 62 dB INPUT CHARACTERISTICS Input Resistance +IN, f < 100 kHz 500 kΩ OUTPUT CHARACTERISTICS Single-Ended, +Swing RLOAD = 50 Ω 11 11.1 VP Single-Ended, −Swing RLOAD = 50 Ω 0.9 1 VP Single-Ended, +Swing RLOAD = 100 Ω 11 11.1 VP Single-Ended, −Swing RLOAD = 100 Ω 0.8 0.9 VP Differential Swing RLOAD = 100 Ω 20.2 20.6 V p-p POWER SUPPLY Single Supply 12 V Supply Current PD1 = 0, PD0 = 0 10.5 11.8 13 mA/amp PD1 = 0, PD0 = 1 7 7.9 9 mA/amp PD1 = 1, PD0 = 0 4.3 5.2 6.3 mA/amp PD1 = 1, PD0 = 1 0.9 1.3 mA/amp

Rev. 0 | Page 4 of 16 Parameter Test Conditions/Comments Min Typ Max Unit POWER-DOWN PINS PD1, PD0 Threshold Referenced to GND 1.5 V High Level Input Voltage, VIH 2 5 V Low Level Input Voltage, VIL 0 0.8 V PD1, PD0 = 0 Pin Bias Current PD1 or PD0 = 0 V −1.5 −0.2 +1.5 μA PD1, PD0 = 1 Pin Bias Current PD1 or PD0 = 3 V 40 63 80 μA Enable/Disable Time 130/116 ns Power Supply Rejection Ratio −63 −70 dB

Figure 4. Pin Configuration Table 4. Pin Function Description 1 +VS Positive Power Supply Input. 4 −IN A Amplifier A Inverting Input. 5 +IN A Amplifier A Noninverting Input. 6 PD0 Power Dissipation Control. 7 PD1 Power Dissipation Control. 8 +IN B Amplifier B Noninverting Input. 9 −IN B Amplifier B Inverting Input. 10 OUT B Amplifier B Output. 11 (Exposed Paddle) GND Ground (Electrical Connection Required).

Figure 21. Simplified Block Diagram

Rev. 0 | Page 11 of 16

APPLICATION INFORMATION

FEEDBACK RESISTOR SELECTION The feedback resistor has a direct impact on the closed-loop bandwidth and stability of the current feedback op amp. Reducing the resistance below the recommended value can make the amplifier response peak and even become unstable. Increasing the size of the feedback resistor beyond the recom- mended value reduces the closed-loop bandwidth. Table 5 provides a convenient reference for quickly determining the feedback and gain resistor values, and the corresponding bandwidth, for common gain configurations. The recommended feedback resistor value for the ADA4311-1 is 499 Ω. Table 5. Recommended Values and Frequency Performance1 are compatible with standard 3 V and 5 V CMOS logic. Table 6. Power Modes renders the part inoperable. adequate heat transfer away from the die and into the board.

2 V p-p, with the gain of the ADA4311-1 configured to realize

Figure 22. TxDAC Output Directly via Center-Tap Transformer

Rev. 0 | Page 12 of 16 BOARD LAYOUT As is the case with all high speed applications, careful attention to printed circuit board (PCB) layout details prevents associated board parasitics from becoming problematic. Proper RF design technique is mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance return path. Removing the ground plane on all layers from the area near the input and output pins reduces stray capacitance, particularly in the area of the inverting inputs. Signal lines connecting the feedback and gain resistors should be as short as possible to minimize the inductance and stray capacitance associated with these traces. Termination resistors and loads should be located as close as possible to their respective inputs and outputs. Input and output traces should be kept as far apart as possible to minimize coupling (crosstalk) though the board. Wherever there are complementary signals, a symmetrical layout should be provided to the extent possible to maximize balanced performance. When running differential signals over a long distance, the traces on the PCB should be close. Doing this reduces the radiated energy and makes the circuit less susceptible to RF interference. Adherence to stripline design techniques for long signal traces (greater than about 1 inch) is recommended. For more information on high speed board layout, see A Practical Guide to High-Speed Printed-Circuit-Board Layout. POWER SUPPLY BYPASSING The ADA4311-1 operates on supplies from 6 V to 12 V . The ADA4311-1 circuit should be powered with a well-regulated power supply. Careful attention must be paid to decoupling the power supply. High quality capacitors with low equivalent series resistance (ESR), such as multilayer ceramic capacitors (MLCCs), should be used to minimize supply voltage ripple and power dissipation. In addition, 0.1 μF MLCC decoupling capacitors should be located no more than ⅛-inch away from each of the power supply pins. A large, usually tantalum, 10 μF capacitor is required to provide good decoupling for lower frequency signals and to supply current for fast, large signal changes at the ADA4311-1 outputs. Bypassing capacitors should be laid out in such a manner as to keep return currents away from the inputs of the amplifiers, which minimizes any voltage drops that can develop due to ground currents flowing through the ground plane. A large ground plane also provides a low impedance path for the return currents.

EXCEPT FOR EXPOSED PAD DIMENSIONS.

1.10 MAX

Figure 23. 10-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP]

Rev. 0 | Page 14 of 16 NOTES

Rev. 0 | Page 15 of 16 NOTES

Rev. 0 | Page 16 of 16 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06940-0-8/07(0)