AD4129-4 (Rev.A)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 110
Technical content
32 μA, Ultra-Low Power, 16-Bit Sigma-Delta ADC with Integrated PGA and FIFO Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►Ultra-low current consumption (typical) ►32 µA: continuous conversion mode (gain = 128) ►5 µA: duty cycling mode (ratio = 1/16) ►0.5 µA: standby mode ►0.1 µA: power-down mode ►Built-in features for system level power savings ►Current saving duty cycle ratio: 1/4 or 1/16 ►Smart sequencer and per channel configuration minimizes host processor load ►Deep embedded FIFO minimizes host processor load (depth of 256 samples) ►Autonomous FIFO interrupt functionality, threshold detection ►Single supply as low as 1.71 V increasing battery length ►RMS noise: 25 nV rms at 1.17 SPS (gain = 128) = 48 nV/√Hz ►Up to 16 noise free bits (gain = 1) ►Output data rate: 1.17 SPS to 2.4 kSPS ►Operates from 1.71 V to 3.6 V single supply or ±1.8 V split supplies ►Band gap reference with 15 ppm/°C maximum drift ►PGA with rail-to-rail analog input ►Adaptable sensor interfacing functionality ►Matched programmable excitation currents for RTDs ►On-chip bias voltage generator for thermocouples ►Low-side power switch for bridge transducers ►Sensor open-wire detection ►Internal temperature sensor and oscillator ►Self and system calibration ►Flexible filter options ►Simultaneous 50 Hz/60 Hz rejection (on selected filter options) ►General-purpose outputs ►Diagnostic functionality ►Crosspoint multiplexed inputs ►4 differential/8 pseudodifferential inputs ►5 MHz SPI (3-wire or 4-wire) ►Available in 35-ball, 2.7 mm × 3.56 mm WLCSP and 32-lead, 5 mm × 5 mm LFCSP ►Temperature range: −40°C to +105°C (WLCSP), −40°C to +125°C (LFCSP) ►AD4129-4 LFCSP pin compatible with AD7124-4 LFCSP
APPLICATIONS
►Smart transmitters ►Wireless battery and harvester powered sensor nodes ►Portable instrumentation ►Temperature measurement: thermocouple, RTD, thermistors ►Pressure measurement: bridge transducers ►Healthcare and wearables FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram
analog.com Rev. A | 2 of 110 Internal Reference and Temperature Sensor... 30
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REVISION HISTORY
1/2025—Rev. 0 to Rev. A Changes to Last SCLK Rising for SW Reset Serial Peripheral Interface (SPI) Transaction to First SCLK Falling for Next SPI Transaction Parameter and CS Rising Edge for SW Reset SPI Transaction to CS 4/2024—Revision 0: Initial Version
analog.com Rev. A | 4 of 110 The AD4129-4 is an ultra-low power, high precision, and measure- ment solution for low bandwidth battery-operated applications. The fully integrated analog front end (AFE) includes a multiplexer for up to 8 single-ended or 4 differential inputs, programmable gain amplifier (PGA), 16-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC), on-chip reference and oscillator, selectable filter options, smart sequencer, sensor biasing and excitation options, diagnos- tics, and newly added features to improve the battery-operated lifetime (more than 5 years on a coin cell), that is, a first in, first out (FIFO) buffer and duty cycling. The AD4129-4 allows users to measure low-frequency signals with a current consumption of 28.5 μA (gain = 1) and 32.5 μA (gain = 128) while continuously converting, and even lower average currents when using one of the duty cycling options. The AD4129-4 can be configured to have 4 differential inputs or 8 single-ended or pseudodifferential inputs, which connect to a crosspoint multiplexer, where any input pair can become a measurement channel input to the PGA and ADC. The AD4129-4 is designed to allow the user to operate from a single analog supply voltage from 1.71 V to 3.6 V. In battery applications, operation as low as 1.71 V can extend the system lifetime as the AFE can continue its operation, even as the battery voltage dissipates. The digital supply can be separate and range from 1.65 V to 3.6 V. Together with the reduced current consumption, the integration of an on-chip FIFO buffer can be used in tandem with the smart sequencer, to enable the AD4129-4 to become an autonomous measurement system, which allows the microcontroller to sleep for extended periods. Intelligent interrupt functionality gives the user a greater confidence in both error detection and safety. The user can enable an interrupt signal to trigger when the samples in the FIFO reach a predefined value or when a user-programmable threshold is exceeded. The following key analog functions are offered on the AD4129-4 to allow simple and effective connection to transducers used for measuring temperature, load, and pressure: ►PGA. Due to the programmable gain (from 1 to 128) and the high input impedance with low input current, the PGA allows direct interfacing to transducers with low output amplitudes such as resistive bridges, thermocouples, and resistance temperature detectors (RTDs). ►The capacitive PGA allows full common-mode input range, giv- ing designers greater margin for widely varying input common modes. A wider common-mode input range improves the overall resolution and is highly effective in ratio metric measurements. ►Low drift precision current sources. The IEXC0 and IEXC1 cur- rent sources can be used to excite 2‑ , 3‑ , and 4‑ wire RTDs. Excitation current output options include 100 nA, 10 μA, 20 μA, 50 μA, 100 μA, 150 μA, and 200 μA. ►The low-side power switch (PDSW) can be used to power down bridge sensors between conversions. The PDSW can be con- trolled within the sequencer on a per channel basis, allowing optimum timing and energy savings in the overall system. The PDSW can also allow higher powered analog sensors to be used in a low power system. ►Voltage bias for thermocouples (the VBIAS source sets the common-mode voltage of a channel to AVDD/2). ►The smart sequencer allows the conversion of each enabled preconfigured channel in a predetermined order, allowing a mix of transducer, system checks, and diagnostic measurements to be interleaved. The sequencer eliminates the need for repetitive serial interface communication with the device. Sixteen channels can be configured in the sequence, each of them selecting from eight predefined ADC setups that allow selection of gain, filter type, output data rate, buffering, timing, and reference source. High levels of integrated front-end functionality, coupled with small package options, allow smaller end solutions. For example, the AD4129-4 integrates a low thermal drift band gap reference in addition to accepting an external differential reference, which can be internally buffered. In safety critical applications, the AD4129-4 includes diagnostic functionality such as open-wire detection through burnout currents, internal temperature sensor, reference detection, and analog input overvoltage and undervoltage detection. Added diagnostics are included on the digital interface such as cyclic redundancy check (CRC) and serial interface checks for a robust communication link. COMPANION PRODUCTS ►Low Noise, Low Dropout Regulators: ADP150ACBZ‑ 3.3 and ADP150ACBZ‑ 1.8 ►Regulated Charge-Pump Inverters: LTC1983ES6‑ 3 and ADP7182AUJZ‑ 1.8 ►Voltage Reference: ADR391 or ADR3625 ►Low Power Microcontrollers: MAX32670 (precision), MAX32655 (BLE), MAX32663A (ECG)
Table 1. ADC and AFE Specifications
16 Bits FS4 > 8, sinc3 filter
1 See the Terminology section. 2 These specifications are not production tested but are supported by characterization data at the initial product release. Cycling Mode and Duty Cycling Mode Timing sections. 4 FS is the decimal equivalent of the FS, Bits[10:0] in the filter registers. characterization data at the initial product release. calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 7 PGA_BYP_n = 1. The PGA_BYP_n bit can be found in each CONFIG_n register. See the Programmable Gain Amplifier section for more details.
8 Recalibration at any temperature removes these errors. 9 Gain error applies to both positive and negative full scale. A factory calibration is performed at gain = 1 and TA = 25°C (PGA_BYP_n = 0). 10 This gain error is factory calibrated at ambient temperature and at a gain of 1 (PGA_BYP_n = 0). 11 CAL_RANGE_X2 = 1 for VREF > 2 V. The CAL_RANGE_X2 bit can be found in the MISC register. See the Internal Gain Calibration section for more details. Table 2. Analog Input Specifications 1 See the Terminology section. 3 These specifications are not production tested but are supported by characterization data at the initial product release. 4 PGA_BYP_n = 0, when VREF > (AVDD − AVSS – 200 mV), the input differential range cannot exceed (AVDD − AVSS – 200 mV)/gain. 5 PGA_BYP_n = 1. The PGA_BYP_n bit can be found in each CONFIG_n register. See the Programmable Gain Amplifier section for more details. Table 3. Reference Specifications
Table 3. Reference Specifications (Continued) 1 See the Terminology section. 3 These specifications are not production tested but are supported by characterization data at the initial product release. 4 The REF_BUFP_n and REF_BUFM_n bits can be found in each CONFIG_n register. See the Reference Buffers section for more details. Table 4. Sensor Biasing Specifications
32 TA = −40°C to +125°C (LFCSP only)
78 TA = −40°C to +125°C (LFCSP only)
Table 4. Sensor Biasing Specifications (Continued) 1 See the Terminology section. 2 These specifications are not production tested but are supported by characterization data at the initial product release. 3 Matching between IOUT0 and IOUT1, VOUT = 0 V. Table 5. Diagnostics Specifications 1 See the Terminology section. 2 These specifications are not production tested but are supported by characterization data at the initial product release. Table 6. Rejection Specifications
79 TA = −40°C to +125°C (LFCSP only)
90 TA = −40°C to +125°C (LFCSP only)
96 TA = −40°C to +125°C (LFCSP only)
85 TA = −40°C to +125°C (LFCSP only)
Table 6. Rejection Specifications (Continued) 1 See the Terminology section. 2 PGA_BYP_n = 1. The PGA_BYP_n bit can be found in each CONFIG_n register. See the Programmable Gain Amplifier section for more details. 3 These specifications are not production tested but are supported by characterization data at the initial product release. 4 FS is the decimal equivalent of the FS, Bits[10:0] in the filter registers.
Table 7. Logic Input and Output Specifications 1 See the Pin Configuration and Function Descriptions section. 2 These specifications are not production tested but are supported by characterization data at the initial product release. 3 The bipolar bit can be found in the ADC_CONTROL register. See the Data Output Coding section for more details. 4 See also the Out of Standby Mode Timing section for further details. 5 General-purpose output pins used as digital pins require AVSS = DGND and AVDD = IOVDD. See the General-Purpose Output section. Table 8. Power Specifications
Table 8. Power Specifications (Continued) 1 The digital inputs are equal to IOVDD or DGND with excitation currents disabled. 2 PGA_BYP_n = 1. The PGA_BYP_n bit can be found in each CONFIG_n register. See the Programmable Gain Amplifier section for more details. Cycling Mode and Duty Cycling Mode Timing sections. 4 These specifications are not production tested but are supported by characterization data at the initial product release.
Table 9. Timing Specifications 1 These specifications are not production tested but are supported by characterization data at the initial product release. 2 The device operates with SPI Mode 3: SCLK idles high, the falling edge of SCLK is the drive edge for DOUT, and the rising edge of SCLK is the sample edge for DIN. 3 CSB_EN = 0b0 (default) in the ADC_CONTROL register (3-wire mode). Change this bit to 1 to enable 4-wire mode. 4 See the 3-Wire Mode Timing Diagrams section.
6 This bit can be found in the ADC_CONTROL register and it is only active if CSB_EN = 0b0 in the same register. 7 Applies only when SYNC is high, or MM_CRC_ERR_EN = 0b1 and only for ADC_CONTROL and error register writes. 8 For the data ready signal related timing specifications, the INT pin is considered (INT_PIN_SEL = 0b00 in the IO_CONTROL register). See the Data Ready Signal section. 9 See the 4-Wire Mode Timing Diagrams section. rising edge. In 3-wire mode, CS pin can still be used to enable (CS pin low) and disable (CS pin high) the DOUT pin. 12 See the System Synchronization section. 13 Internal oscillator is kept alive. See the internal clock wake-up time specification in Table 7 and the Out of Standby Mode Timing section for further details. Table 10. FIFO Timing Specifications 1 These specifications are not production tested but are supported by characterization data at the initial product release. 2 See the FIFO Timing Diagrams and FIFO sections. 3 For the FIFO ready signal related timing specifications, the DOUT pin is considered. 4 For the FIFO interrupt signal related timing specifications, the INT pin is considered (INT_PIN_SEL = 0b00 in the IO_CONTROL register). 5 This specification applies to the FIFO watermark interrupt. 6 CS falling edge (4-wire mode) or SCLK falling edge (3-wire mode and CS tied low). 7 CS rising edge (4-wire mode) or SCLK rising edge (3-wire mode and CS tied low). 8 See the Clearing the FIFO section. Figure 2. Write Cycle Timing Diagram, 3-Wire Mode (CSB_EN Bit Set to 0), CS Pin Tied Low
TA = 25°C, unless otherwise noted. Table 11. Absolute Maximum Ratings
1 See the Pin Configuration and Function Descriptions section for a list of the
digital input and digital output pins. ing conditions for extended periods may affect product reliability. nation, and they all apply for any given configuration. Table 12. Thermal Resistance
1 The values in Table 12 were calculated based on the standard JEDEC 2S2P
thermal test board with 6 × 11 thermal vias. See the JEDEC JESD51 series. ature in the system environment. standards in the JESD51 series is recommended. must be monitored using the internal temperature sensor. sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. are for characterization only. Table 13. AD4129-4, 35-Ball WLCSP Table 14. AD4129-4, 32-Lead LFCSP damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 14. WLCSP Pin Configuration Table 15. WLCSP Pin Function Descriptions A1 AVDD S Analog Supply Voltage, Relative to AVSS. See the Power Supplies section. selection bits (RS, Bits[5:0]) of the COMMS register identifying the appropriate register. See the Digital Interface section. information transmitting to or from the ADC in smaller batches of data. See the Digital Interface section. connect any additional load to the REGCAPA pin. See the Internal LDOs section. used to clear the FIFO. See the Clearing the FIFO section. read access. See the Digital Interface section. Interrupt section). If not in use, tie the CLK pin to DGND. B5 IOVDD S Serial Interface Supply Voltage, 1.65 V to 3.6 V. See the Power Supplies section. between AVDD and AVSAVSSS must be between 1.71 V and 3.6 V. See the Power Supplies section. C2 PSW AI Low-Side Power Switch to AVSS. See the Power-Down Switch section.
Table 15. WLCSP Pin Function Descriptions (Continued) C5 DGND S Digital/Common Ground Reference Point. See the Power Supplies section. capacitor is required on the REFOUT pin when the internal reference is active. See the ADC Reference section. connect any additional load to the REGCAPD pin. See the Internal LDOs section. AI/O Analog Input 7 (AIN7) (Default)/Output of Internal Excitation Current Source/Bias Voltage/Negative Reference Input. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. Negative Reference Input (REFIN2(−)). The REFIN2(−) pin can be anywhere between AVSS and AVDD – 0.5 V. AVDD. When AVSS is tied to DGND and IOVDD is tied to AVDD, the P0 pin can operate like a digital output. Signal section and FIFO Interrupt section). E5 AIN0/IOUT/VBIAS AI/O Analog Input 0 (AIN0) (Default)/Output of Internal Excitation Current Source/Bias Voltage. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. AI/O Analog Input 6 (AIN6) (Default)/Output of Internal Excitation Current Source/Bias Voltage/Positive Reference Input. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. Positive Reference Input (REFIN2(+)). An external reference can be applied between REFIN2(+) and REFIN2(−). is 2.5 V, but the device functions with a reference from 0.5 V to AVDD. F5 AIN1/IOUT/VBIAS AI/O Analog Input 1 (AIN1) (Default)/Output of Internal Excitation Current Source/Bias Voltage. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. G1 AIN5/IOUT/VBIAS AI/O Analog Input 5 (AIN5) (Default)/Output of Internal Excitation Current Source/Bias Voltage. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. G2 AIN4/IOUT/VBIAS AI/O Analog Input 4 (AIN4) (Default)/Output of Internal Excitation Current Source/Bias Voltage. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. G4 AIN3/IOUT/VBIAS/P2AI/O Analog Input 3 (AIN3) (Default)/Output of Internal Excitation Current Source/Bias Voltage/General Purpose Output 2. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. AVDD. When AVSS is tied to DGND and IOVDD is tied to AVDD, the P2 pin can operate like a digital output. G5 AIN2/IOUT/VBIAS/P1AI/O Analog Input 2 (AIN2) (Default)/Output of Internal Excitation Current Source/Bias Voltage/General Purpose Output 1. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output.
Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. AVDD. When AVSS is tied to DGND and IOVDD is tied to AVDD, the P1 pin can operate like a digital output. 1 AO is analog output, S is supply, AI is analog input, AI/O is analog input or output, DI is digital input, DO is digital output, and DI/O is digital input or output.
- NC = NOT CONNECT. THESE PINS MUST BE MECHANICALLY SOLDERED TO THE PCB.
- CONNECT EXPOSED PAD TO AV SS.
Figure 15. LFCSP Pin Configuration Table 16. LFCSP Pin Function Descriptions connect any additional load to the REGCAPD pin. See the Internal LDOs section. 2 IOVDD S Serial Interface Supply Voltage, 1.65 V to 3.6 V. See the Power Supplies section. 3 DGND S Digital/Common Ground Reference Point. See the Power Supplies section. 4 AIN0/IOUT/VBIAS AI/O Analog Input 0 (AIN0) (Default)/Output of Internal Excitation Current Source/Bias Voltage. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. 5 AIN1/IOUT/VBIAS AI/O Analog Input 1 (AIN1) (Default)/Output of Internal Excitation Current Source/Bias Voltage. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. AVDD. When AVSS is connected to DGND and IOVDD is connected to AVDD, the P0 pin can operate as a digital output. Signal section and FIFO Interrupt section). 8 AIN2/IOUT/VBIAS/P1AI/O Analog Input 2 (AIN2) (Default)/Output of Internal Excitation Current Source/Bias Voltage/General Purpose Output 1. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. AVDD. When AVSS is connected to DGND and IOVDD is connected to AVDD, the P1 pin can operate as a digital output. 9 AIN3/IOUT/VBIAS/P2AI/O Analog Input 3 (AIN3) (Default)/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 2.
Table 16. LFCSP Pin Function Descriptions (Continued) available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. AVDD. When AVSS is connected to DGND and IOVDD is connected to AVDD, the P2 pin can operate as a digital output. 16 AIN4/IOUT/VBIAS AI/O Analog Input 4 (AIN4) (Default)/Output of Internal Excitation Current Source/Bias Voltage. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. 17 AIN5/IOUT/VBIAS AI/O Analog Input 5 (AIN5) (Default)/Output of Internal Excitation Current Source/Bias Voltage. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin.
20 AIN6/IOUT/ VBIAS/
AI/O Analog Input 6 (AIN6) (Default)/Output of Internal Excitation Current Source/Bias Voltage/Positive Reference Input. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. Positive Reference Input (REFIN2(+)). An external reference can be applied between REFIN2(+) and REFIN2(−). is 2.5 V, but the device functions with a reference from 0.5 V to AVDD.
21 AIN7/IOUT/ VBIAS/
AI/O Analog Input 7 (AIN7) (Default)/Output of Internal Excitation Current Source/Bias Voltage/Negative Reference Input. available at the IOUT pin. Either IOUT1 or IOUT0 can be switched to this output. Bias Voltage (VBIAS). A bias voltage midway between the analog power supply rails can be generated at the VBIAS pin. Negative Reference Input (REFIN2(−)). The REFIN2(−) pin can be anywhere between AVSS and AVDD – 0.5 V. capacitor is required on the REFOUT pin when the internal reference is active. See the ADC Reference section. between AVDD and AVSS must be between 1.71 V and 3.6 V. See the Power Supplies section. connect any additional load to the REGCAPA pin. See the Internal LDOs section. 25 PSW AI Low-Side Power Switch to AVSS. See the Power-Down Switch section. 26 AVDD S Analog Supply Voltage, Relative to AVSS. See the Power Supplies section. used to clear the FIFO. See the Clearing the FIFO section. with read access. See the Digital Interface section. selection bits (RS, Bits[5:0]) of the COMMS register identifying the appropriate register. See the Digital Interface section. information transmitting to or from the ADC in smaller batches of data. See the Digital Interface section.
Interrupt section). If not in use, tie the CLK pin to DGND. 1 AO is analog output, S is supply, AI is analog input, AI/O is analog input or output, DI is digital input, DO is digital output, and DI/O is digital input or output.
Figure 28. Noise Histogram Plot (Sinc3 Filter, ODR = 50 SPS, Gain = 1, Figure 29. RMS Noise vs. Analog Input Voltage (Sinc3 Filter, ODR = 50 SPS, Figure 30. RMS Noise vs. Analog Input Voltage (Sinc3 Filter, ODR = 50 SPS, Figure 31. Noise Histogram Plot (Sinc4 Filter, ODR = 240 SPS, Gain = 1, Figure 32. RMS Noise vs. Analog Input Voltage (Sinc3 Filter, ODR = 50 SPS, Figure 33. NSD vs. Output Data Rate for Various Gains (Sinc3 Filter, External
2.5 V Reference)
analog.com Rev. A | 34 of 110 ANALOG INPUT AINP AINP refers to the positive analog input. AINM AINM refers to the negative analog input. Input Span The input span specification defines the minimum and maximum input voltages from zero to full scale that the analog input can accept and still calibrate gain accurately. ADC Integral Nonlinearity (INL) Error INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (not to be confused with bipolar zero), a point 0.5 LSB below the first code transition (000 ... 000 to 000 ... 001), and full scale, a point 0.5 LSB above the last code of the full-scale range. Offset Error Offset error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Offset Calibration Range In the system calibration modes, the AD4129-4 calibrates offset with respect to the analog input. The offset calibration range specifi- cation defines the range of voltages that the AD4129-4 can accept and still calibrate offset accurately. Gain Error Full-Scale Range (FSR) The full-scale range is the input range the AD4129-4 can accept based on the choice of reference voltage and gain value. For a differential input signal, FSR = 2 × VREF/gain. Full-Scale Calibration Range The full-scale calibration range is the range of voltages that the AD4129-4 can accept in the system calibration mode and still calibrate full scale correctly. Output Data Rate (ODR) The output data rate is the rate at which ADC conversions are available on a single settled channel when the ADC is continuously converting. Same Conversion Output Data Rate (1CNV_ODR) The same conversion output data rate is the rate at which ADC conversions are available using multiple channels with the same filter settings and taking one sample per channel. REFERENCE Line Regulation Line regulation refers to the change in output voltage in response to a given change in supply voltage and is expressed in μV/V. Load Regulation Load regulation refers to the change in output voltage in response to a given change in load current and is expressed in μV/mA. Voltage Reference (VREF) Temperature Coefficient (TC) VREF TC is a measure of the change in the reference output voltage with a change in the ambient temperature of the device, normalized by the output voltage at 25°C. VREF TC is specified using the box method, which defines TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C, as follows: V RE F TC = V RE F _ M A X − V REF _ MI N V R EF _ NOM × TE MP _ R A NG E × 10 6 pp m / ° C where: VREF_MAX is the maximum reference voltage output measured over the full temperature range. VREF_MIN is the minimum reference voltage output measured over the full temperature range. VREF_NOM is the nominal reference voltage output at ambient tem- perature (25°C). TEMP_RANGE is the difference between the maximum and mini- mum operating temperature of the reference. Voltage Reference (VREF) Noise Spectral Density (NSD) VREF NSD is a measurement of the internally generated thermal noise characterized as a spectral density nV/√Hz. TEMPERATURE SENSOR Accuracy The temperature sensor accuracy is the deviation of the internal measured temperature vs. the real ambient temperature normalized to a 25°C measurement. Temperature sensor accuracy is measured in °C.
analog.com Rev. A | 35 of 110 Sensitivity The temperature sensor sensitivity is the output voltage change due to a change in ambient temperature and is expressed in µV/K or LSB/K.
AD4129-4 for various output data rates, gain settings, and filters. the resolution without a code flicker.
2.5 V REFERENCE
Table 17. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P) Table 18. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
Table 19. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P) Table 20. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits Table 21. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P) Table 22. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
Table 23. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P) Table 24. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits Table 25. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P) Table 26. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
1.25 V REFERENCE
Table 27. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
Table 27. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P) (Continued) Table 28. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits Table 29. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P)
Table 30. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits Table 31. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P) Table 32. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits Table 33. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P) Table 34. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits
Table 34. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits (Continued) Table 35. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate, Expressed in µVRMS (µVP-P) Table 36. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Expressed in Bits square root of the input bandwidth. Table 37. Input Referred Noise Spectral Density, Expressed in nV/√Hz
Figure 70. Detailed Block Diagram gathers measurements according to the predefined configuration. wake when a problem occurs, or the FIFO is ready to be read. filter. The ADC core inherently rejects frequencies at 38.4 kHz. tectures, especially for high resolution, low frequency applications. Refer to MT-022 and MT-023 for a deep dive in Σ-Δ ADC theory. Table 38. AD4129-4 Filter Options Sinc4 0x01 to 0xA 2400 to 240 ADC frequency (fADC) = fMCLK / 32 / FS. Sinc3 + REJ60 0x01 to 0x7FF 2400 to 1.17 FS = 0d48 can be set to simultaneously reject 50 Hz and 60 Hz at 50 SPS ODR. Sinc3 + Post Filters N/A2 16.21, 19.355, 24, 26.087Low latency with good 50 Hz and 60 Hz rejection. 1 Assuming accurate fMCLK = 76.8 kHz.
CLK pin can also be selected as the MCLK source for the device. when the internal divide by two option is selected. AD4129-4 ADC clock connection scheme. Table 39. MCLK Source Options reference connection scheme. used with the internal reference or an externally applied reference. accommodate 2-wire, 3-wire, and 4-wire RTDs.
Figure 71. Analog Input Multiplexer Circuit inputs, or a combination of both. bit to 1 in the MISC register. using the excitation currents. load capacitance. See Table 4 for more details. is in standby mode (see the Power-Down Modes section). the PGA bits in the respective CONFIG_n register.
Currents section for further details. The analog input range is ±VREF/gain. See Table 40. Table 40. Absolute Input Range Examples Table 40. Absolute Input Range Examples (Continued) Table 41. IO_CONTROL Register
ADC setups to be preconfigured and selected for each channel. the Smart Channel Sequencer section for full details. See the Diagnostics section for full details. to 256 conversion results. See the FIFO section for full details. single supply for both AVDD and IOVDD as low as 1.71 V. and IOVDD LDOs, respectively.
- A POR resets the state of the user configuration registers. If
not trigger a reset of the device. cleared when the user reads the status register. Figure 72. POR Timing Diagram the negative input. SETUP_m = 0 is selected. selected with FS, Bits[10:0] = 0x30.
modes. In Table 42, only the power-down mode options are listed. Table 42. Power-Down Mode Options blocks are powered down, with no register information retained. To go to power-down mode, the device must be in standby mode. ed transitions to power-down mode. The modulator and digital filter are held in reset in idle mode. All user registers retain their content as previously configured. consumption with respect to continuous conversion mode. register to select a different mode of operation. DIAGNOSTICS = 1, the internal oscillator is kept enabled. STBY_REFHOL_EN bit and the STBY_INTREF_EN bit to 1. of Standby Mode Timing section for further details.
AVSS, following the specifications in Table 2. the ADC Calibration section. (zero scale) and 0xFFFF (full scale). where AINP < AINM are clamped at 0x0000 (zero scale). interprets threshold values in the FIFO settings. output code equations for any analog input voltage. Table 45. ADC Data Output Coding Options
1 N = 16, VIN is the differential input voltage, and Gain is the gain setting (1 to
bipolar bit in the ADC_CONTROL register. Table 46. Ideal Output Codes for a Given Input Differential Signal for reading the data register becomes: DATA[15:0], STATUS[7:0]. TROL register to 1 (see Table 47). Table 47. ADC_CONTROL Register Table 48. Status Register Table 49. CHANNEL_m Register (m = 0 to 15)
1 The CHANNEL_0 default value is 0x800100. The default value of all other channels is 0x000100. channel in increasing order up to the largest enabled channel. configuration, filter, gain, and offset settings. GAIN_0 register. Figure 77 shows the grouping of these registers. Table 50. CONFIG_n Register (n = 0 to 7) Table 51. FILTER_n Register (n = 0 to 7) Table 52. OFFSET_n Register (n = 0 to 7) Table 53. GAIN_n Register (n = 0 to 7)
Figure 77. ADC Setup Register Grouping sensor output to reach a settled value before conversion starts. Calibration section for more details. See Table 52 and Table 53. Table 54. ADC Conversion Mode Options complete, the ADC starts again with the lowest enabled channel. single sequence mode, SPI writes are ignored. the device out of idle mode and initiate a new single sequence. In idle mode, the modulator and digital filter are held in reset.
again with an ADC conversion on the lowest enabled channel. available. See the Duty Cycling Mode Timing section. be kept active when in standby during duty cycling. Figure 81. Example of Duty Cycling Mode vs. Continuous Conversion Mode Table 55. Ready Interrupt Pin Options1 assign the selected FIFO interrupt to a pin as per Table 72. 2 Pin behaves as a shared DOUT and data ready signal functionality. found in Table 9 and Figure 9. read mode is enabled, an ADC result can be read only once. is ignored if the CLK pin is enabled as interrupt. IO_CONTROL register is ignored if P0 is enabled as an interrupt. automatically kept enabled in standby mode.
modulator and places the AD4129-4 into a consistent, known state. reset state, and the device starts to gather input samples again. SYNC pin low at power-up and while configuring the AD4129-4. mode. See the ADC Conversion Modes section for more details. (see Table 41). See the Clearing the FIFO section for more details. 0x8000 and the nominal value of the GAIN_n registers is 0x5555. the AD4129-4 to update the OFFSET_n and GAIN_n registers. Table 56. ADC Calibration Mode Options calibration reduces the gain error to the order of the noise. tional point of view, treat a calibration like another ADC conversion.
ADC CONFIGURATION AND OPERATIONS analog.com Rev. A | 57 of 110 given channel if the reference source or the gain for that channel is changed (using the PGA_n bitfields of the CONFIG_n registers). The following equations show the calculations that are used to scale data based on offset and gain calibration coefficients. In unipolar mode (bipolar bit = 0b0 in the ADC_CONTROL register): D AT A = 0.75 × V I N V R EF × 2 N ‐1 − O FF S ET _ n − 0x8000 × G AI N _ n 0x4000 × 2 In bipolar mode (bipolar bit = 0b1 in the ADC_CONTROL register): D A T A = 0 .75 × V I N V RE F × 2 N ‐1 − OF F SE T _ n − 0x8000 × G A I N _ n 0 x 4000 + 0x8000 where: DATA is the code written in the data register after postprocessing. VIN is the differential voltage at the input of the converted channel (AINP − AINM). N is the number of bits of the ADC (16). OFFSET_n is the hexadecimal code written in the relative OFF- SET_n register of the converted channel. GAIN_n is the hexadecimal code written in the relative GAIN_n register of the converted channel. The AD4129-4 provides the user with access to the on-chip calibra- tion registers, allowing the microprocessor to read the calibration coefficients of the device or to write its own calibration coefficients. A read or write of the OFFSET_n and GAIN_n registers can be performed at any time except during an internal or system calibra- tion. The values in the calibration registers are 16 bits wide. The input span and offset of the device can also be manipulated using these registers. See the System Calibration Span and Offset Limits section for more details. The AD4129-4 can run background checks during calibration. To enable this functionality, set the ADC_ERR_EN bit in the ER- ROR_EN register to 1. If an error occurs, the ADC_ERR bit in the error register is set. See the ADC Errors section for more details. If the user is concerned about verifying that a valid reference is in place every time a calibration is performed, check the status of the REF_DETECT_ERR bit at the end of the calibration cycle. Internal Gain Calibration To perform an internal gain calibration, a full-scale input voltage generated internally, is automatically connected to the PGA inputs. A gain calibration is recommended each time the gain of a channel is changed to minimize the full-scale error caused by the new gain setting. When performing internal calibrations, the internal gain calibration must be performed before the internal offset calibration. Therefore, write the value 0x8000 to the OFFSET_n register of the selected channel before performing the internal gain calibration, which ensures that the OFFSET_n register is at its default value. If the reference voltage is higher than 2 V, set the CAL_RANGE_X2 bit in the MISC register to 1 to improve the outcome of the internal gain calibration. The AD4129-4 is factory calibrated at ambient temperature and with a gain of 1 with PGA_BYP_n = 0, and the resulting gain coefficients are loaded to the GAIN_n registers of the device as default value. The device does not support further inter- nal gain calibrations at a gain of 1 (PGA_BYP_n = 0). An internal gain calibration requires a time equal to four first conversions of the selected configuration on that channel to be completed. Internal Offset Calibration During an internal offset calibration, the selected positive analog input pin is disconnected, and it is connected internally to the selected negative analog input pin. For this reason, it is necessary to ensure that the voltage on the selected negative analog input pin does not exceed the allowed limits and is free from excessive noise and interference. When performing internal calibrations, the internal gain calibration must be performed before the internal offset calibration. An internal offset calibration requires a time equal to the first conversion of the selected configuration on that channel to be completed. System Offset Calibration A system offset calibration expects the system zero-scale voltages to be applied to the ADC pins before enabling the calibration mode. As a result, offset errors external to the ADC are removed. When performing system calibrations, system offset calibration must be performed before the system gain calibration. Internal calibrations must be performed before completing system calibrations. A sys- tem offset calibration requires a time equal to the first conversion of the selected configuration on that channel to be completed. System Gain Calibration A system gain calibration expects the system full-scale voltages to be applied to the ADC pins before enabling the calibration mode. As a result, gain errors external to the ADC are removed. When performing system calibrations, system offset calibration must be performed before the system gain calibration. Internal calibrations must be performed before completing system calibrations. A sys- tem gain calibration requires a time equal to the first conversion of the selected configuration on that channel to be completed. System Calibration Span and Offset Limits System calibration can be used to compensate for offset or gain errors in the external circuit and to manipulate the input span and offset of the device. Whenever system calibration is performed, the amount of input offset and span adjustments that can be accommodated is limited. The input span is the difference between the input voltage that corresponds to full code and the input voltage that corresponds
register select between the filter types as shown in Table 58. and 60 Hz (±1 Hz) rejection. ieve good rejection at the respective notch frequency (fNOTCH_STD). fMCLK is the main clock frequency (76.8 kHz). fNOTCH_STD is the first notch from sinc3 or sinc4 standalone filters. channels using the same filter. not influence the ODR when the post filters are selected. Table 57. Post Filters: Output Data Rate and Rejection band of ±0.5 Hz around 50 Hz and 60 Hz. Table 58. FILTER_MODE_n Bits and Filter Types
0000 Sinc4 0x01 to 0xA
rejection. FS > 0d10 is forced to FS = 0d10.
0001 Sinc4 + Sinc1 0x01 to 0xA
0011 Sinc3 + REJ60 0x01 to 0x7FF
0100 Sinc3 + Sinc1 0x01 to 0x7FF
FS from 0x01 to 0xCC only (minimum ODR = 1.17).
0110 Sinc3 + Post Filter 2 Not applicable 24
Figure 89. Effect of an Asynchronous Step Change in the Analog Input on the ADC Output Table 60. Number of Intermediate Conversions Needed to Settle a Step
50 HZ AND 60 HZ REJECTION
ieve good rejection at the respective notch frequency (fNOTCH_STD). 50 Hz and/or 60 Hz rejection. See the Rejection Specifications section. achieve a notch at 50 Hz. ODR in this case is 50 SPS. rejection. ODR in this case is 10 SPS. See Table 61 and Figure 90. Table 61. Sinc3 Filter Rejection Performance band of ±1 Hz around 50 Hz and/or 60 Hz. where fNOTCH_STD is the first notch from sinc3 filter. Figure 90. Simultaneous 50 Hz and 60 Hz Rejection for Sinc3 with frequency response of the sinc3 filter with this configuration. Figure 91. Sinc3 and Sinc3 + REJ60 Filter Response (50 SPS ODR)
Post filters offer good simultaneous rejection at 50 Hz and 60 Hz. See Table 57 and the Rejection Specifications section. fNOTCH_STD is the first notch from the sinc3 or sinc4 filter. Avg is the averaging factor (average = 8). sinc4 + sinc1 and sinc3 + sinc1 filters. See Figure 92 and Table 62. Figure 92. Sinc3 + Sinc1 and Sinc4 + Sinc1 Filter Response (FS = 6) Table 62. Averaging Filters Rejection Performance band of ±0.5 Hz around 50 Hz and/or 60 Hz. that are converted only once. due to FS value to output the first result. processing time due to FS value to output the first result. to subsequent conversions, compared to standalone filters. tCNV = 1/fADC, and the processing time is already accounted for. t1st_CNV is the first conversion time on a new channel. new channel due to the SETTLE_n bits selection, as per Table 63. conversion time as shown in Table 64. post filters where it is a constant, as per Table 65. Table 63. Programmable tSETTLE Values
Table 64. Conversion and First Conversion Time (MCLK Cycles) 1 FS is the decimal equivalent of the FS, Bits[10:0] binary value. Table 65. DPP Time (MCLK Cycles) 1 FS is the decimal equivalent of the FS, Bits[10:0] binary value. of the new channel tSETTLE and the previous channel DPP time. the previous channel, as shown in Figure 95. the next channel (REPEAT_n set to 0 in the FILTER_n register). same configuration in the sequence. not change with the 1CNV_ODR or sample rate per channel values. Table 66. First Conversion Time and Conversion Time on a Settled Channel, by Filter Types1 equivalent of the FS, Bits[10:0] in the filter register. DPP Time is the digital postprocessing time expressed in MCLK cycles.
Figure 96. Example of Autonomous Duty Cycling Mode
settings to calculate the standby time. tACTIVE is the effective active time during duty cycling. n is the number of channels enabled. new channel due to the SETTLE_n bits selection, as per Table 63. conversion time as shown in Table 64. See Figure 96. with the first tSETTLE of the active sequence, as shown in Figure 96. autonomous duty cycling mode is enabled. n is the number of channels enabled. conversion time as shown in Table 64. tWU_DUTY is the duty cycling wake-up time (see Table 9). standby mode wake-up time corresponds to tWU_STBY in Table 9. Figure 97. Out of Standby Mode Diagram
analog.com Rev. A | 68 of 110 The ΔV threshold value can be found in Table 5. The external reference voltage can also be monitored for overvolt- age/undervoltage enabling the REF_OV_UV_ERR_EN bit in the ERROR_EN register. An overvoltage is flagged when the voltage on REFINx(+) exceeds AVDD while an undervoltage is flagged when the voltage on REFINx(−) goes below AVSS. The error flag REF_OV_UV_ERR in the error register is set to 1 in any of the two conditions. When this function is enabled, the corresponding flags can be set in the error register. These bits are R/W1C. POWER SUPPLY MONITORS Along with converting external voltages, the ADC can monitor the voltage on the AVDD pin and the IOVDD pin. When the inputs of AVDD to AVSS or IOVDD to DGND are selected, the voltage (AVDD to AVSS or IOVDD to DGND) is internally attenuated by 6, and the resulting voltage is applied to the Σ-Δ modulator. This is useful to monitor variations in the power supply voltage. MAIN CLOCK COUNTER A stable MCLK to the ADC is important as the output data rate, filter first conversion time, and the filter notch frequencies are dependent on the main clock. The AD4129-4 allows the user to monitor the main clock. When the MCLK_CNT_EN bit in the ERROR_EN register is set, the MCLK_COUNT register increments by 1 every 131 main clock cycles. The user can monitor this register over a fixed period. The main clock frequency can be determined from the result in the MCLK_COUNT register. The MCLK_COUNT register wraps around after it reaches its maximum value. SPI DIAGNOSTICS SPI Clock Counter The SPI SCLK counter counts the number of SCLK pulses used in each read and write operation. CS must frame every read and write operation when this function is used. All read and write operations are multiples of eight SCLK pulses. If the SCLK counter counts the SCLK pulses and the result is not a multiple of eight, an error is flagged. The SPI_SCLK_CNT_ERR bit in the error register is set to 1. If a write operation is being performed and the SCLK contains an insufficient number of SCLK pulses, the value is not written to the addressed register and the write operation is aborted. The SCLK counter is enabled by setting the SPI_SCLK_ CNT_ERR_EN bit in the ERROR_EN register. SPI Read/Write Errors Along with the SCLK counter, the AD4129-4 can also check the read and write operations to ensure that valid registers are being addressed. When the SPI_READ_ERR_EN bit in the ERROR_EN register is set to 1, attempts to read registers at addresses not listed in Table 73 cause the SPI_READ_ERR bit to be set to 1 and the readback data for that register is all 0s. When the SPI_WRITE_ERR_EN bit in the ERROR_EN register is set to 1, attempts to write to read-only registers and to registers at addresses not listed in Table 73 cause the SPI_WRITE_ERR bit to be set to 1, and the write transaction is aborted. This function, along with the SCLK counter and the CRC protection, makes the serial interface more robust. Invalid registers are not written to or read from. An incorrect number of SCLK pulses can cause the serial interface to go asynchronous and incorrect registers to be accessed. The AD4129-4 protects against these issues via the diagnostics. SPI Ignore Error At certain times, the on-chip registers are not accessible. During power-up, when the on-chip registers are set to their default values, they cannot be accessed via SPI. The user must wait tRESET_DELAY until this operation is complete before writing to registers. When offset or gain calibrations are being performed, registers cannot be accessed. When in single sequence mode, during conversion and before the last conversion finishes, registers cannot be accessed. The SPI_IGNORE_ERR bit in the error register indicates when the on-chip registers cannot be written to. This diagnostic is ena- bled by default. The function can be disabled using the SPI_IG- NORE_ERR_EN bit in the ERROR_EN register. Any write operations performed when SPI_IGNORE_ERR is set to 1 in the error register are ignored. This bit is R/W1C. CRC PROTECTION The AD4129-4 features optional CRC to provide error detection on interface transactions, memory map content, and read-only memory (ROM) content. CRC Calculation The AD4129-4 uses the CRC-8 standard with the following polyno- mial: x8 + x2 + x + 1 To generate the checksum, the data is left shifted by eight bits to create a number ending in eight Logic 0s. The polynomial is aligned so that its MSB is adjacent to the leftmost Logic 1 of the data. An XOR (exclusive OR) function is applied to the data to produce a new, shorter number. The polynomial is again aligned so that its MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process is repeated until the original data is reduced to a value less than the polynomial. This is the 8-bit checksum.
Figure 103. FIFO Structure the FIFO_MODE bits in the FIFO_CONTROL register to 0b00. Write FIFO_MODE = 0b00 to exit any of the other FIFO modes.
- Clearing the FIFO is recommended after reading the FIFO in
See the FIFO Watermark Interrupt section. Table 68. In this mode, data can be read back at any time unless FIFO_STATUS register is set to 1 (see Table 71). Table 67. Example of FIFO Buffer Filling Up with Conversion Results in Watermark Mode with Watermark = 0 (256 Samples) and Data Not Read Back When Full
255 Empty Empty … Empty (FIFO_HEADER (256),
254 Empty Empty … (FIFO_HEADER (255),
1 Empty (FIFO_HEADER (2),
Table 68. Example of FIFO Buffer Filling Up with Conversion Results in Streaming Mode with Watermark = 0 (256 Samples) and Data Not Read Back When Full Table 69. FIFO_CONTROL Register (LFCSP) pin once the appropriate number of SCLKs is provided. samples read reaches the specified amount in the FIFO command. readback diagram looks like Figure 105. time the next two ADC conversions in the sequence take.
60 Hz Rejection section for more details on how to calculate the
ADC conversion time for a given channel in the sequence. details, see Figure 12 and Table 10. FIFO read command length is equal to 16 SCLK cycles. disabled, or 24 SCLK cycles if the FIFO_HEADER is enabled. can be data loss from the converted sequence.
Table 70. FIFO Header Format Table 71. FIFO_STATUS Register conversion result in the FIFO with the format shown in Table 70. the data with FIFO_HEADER disabled. be interpreted as the trigger to stop reading back the FIFO. sticky. Therefore, it is relevant for every sample. the FIFO operations when the FIFO is enabled. the FIFO is written with at least one ADC conversion. detected to be less than the value in the watermark field. emptied by reading all the content or clearing the FIFO. the FIFO, or by clearing the FIFO. request is successfully granted or the FIFO is emptied. to one conversion cycle if the user is still reading the FIFO data. read or by clearing the FIFO. STATUS register and follows the same behavior.
section on how to select the pin to direct the interrupt signal to. of conversions in the FIFO assume the updated threshold values. THRES_HIGH_FLAG bits to return to 0. when the FIFO is written with at least one ADC conversion. as the error flags clear in the FIFO_STATUS register. Table 72. FIFO Interrupt Pin Options assign the ready signal to a pin as per Table 55.
analog.com Rev. A | 76 of 110 2 N/A means not applicable. CLEARING THE FIFO When the FIFO is enabled, any write to the FIFO_CONTROL register clears the FIFO. It is also possible to use the SYNC pin to initiate a FIFO clear by setting the SYNCB_CLEAR bit to 1 in the IO_CONTROL register (see Table 41). Clearing the FIFO using the SYNC pin guarantees that the sequencer restarts from the first channel. See Figure 11, Figure 13, and Table 10.
the ADP150, which has a 3.3 V output and low quiescent current. minimum value is limited by the minimum AVDD = 1.71 V. Good decoupling is important when using high resolution ADCs. tantalum capacitor in parallel with a 0.1 µF capacitor to DGND. decouple the REFINx(+) and REFINx(−) pins to AVSS. regulates the AVDD supply and one that regulates the IOVDD supply. output signal, and a synchronization signal. Figure 108. Example of MAX32670 μC SPI Connection to AD4129-4 weak pull-down resistor is placed on the DIN line.
analog.com Rev. A | 78 of 110 When not in use, the analog pins (AINx, REFINx(±), REFOUT, PSW) can be left electrically floating, but must be soldered to the PCB for mechanical stability. POWER-UP AND INITIALIZATION Power up the AD4129-4 by following the recommended power sup- ply sequencing as follows: DGND, AVSS (if different from DGND), IOVDD, AVDD, REFINx(+) and REFINx(−), AINx, Digital Inputs. See also the Digital Pins section. Upon power-up, wait for the tRESET_DELAY timing before attempting an SPI transaction (see the Power-On Reset section). The device has a power-on reset function. However, any glitches during pow- er-up can cause corruption of the registers. Therefore, a reset in the initialization routine is advisable. Write 64 consecutive ones to the device to perform a software reset (see the Device Reset section). If the digital host attempts to perform an SPI transaction before the device is ready, the transaction is invalid and the SPI_IGNORE_ERR bit in the ERROR register is set. The SPI_IG- NORE_ERR is an R/W1C type of bit. After the device initializes, the digital interface can be accessed to configure the device, including selecting the reference scheme according to the application. Regardless of the voltage reference scheme used, it is recommended to let the voltage reference settle after configuring the device to ensure it achieves its specifications. The recommended configuration flow is as follows: 1. Select Interface mode: write to ADC_CONTROL register (select 3-wire or 4-wire mode, clock source, enable CRC, data + sta- tus, and so on). 2. Setup configuration: Eight possible ADC setup options. Write to the CONFIG_n and FILTER_n registers (select configuration, filter order, output data rate, and so on). 3. Channel configuration: write to the CHANNEL_m registers (select positive and negative input and setup for each ADC channel, enable open wire detection in GPIO configuration, and so on). 4. Setup ADC mode: write to the ADC_CONTROL register (select ADC operating mode, clock source, enable CRC, data + status, and so on) to start conversions. LAYOUT AND GROUNDING The analog inputs and reference inputs are differential and, there- fore, most of the voltages in the analog modulator are common- mode voltages. The high common-mode rejection of the device removes common-mode noise on these inputs. The analog and digital supplies to the AD4129-4 are independent and separately pinned out to minimize coupling between the analog and digital sec- tions of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the main clock frequency. The digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. As a result, the AD4129-4 is more immune to noise interference than a conventional high resolution converter. However, given that the resolution of the AD4129-4 is high and the noise levels from the converter are so low, care must be taken regarding grounding and layout. The PCB that houses the ADC must be designed so that the analog and digital sections are separated and confined to certain areas of the board. A minimum etch technique is generally best for ground planes because it results in the best shielding. In any layout, the user must keep in mind the flow of currents in the system, ensuring that the paths for all return currents are as close as possible to the paths the currents took to reach their destinations. Place the decoupling capacitors as close to the package as possi- ble (ideally directly against the device). Avoid running digital lines under the device because this couples noise onto the die and allows the analog ground plane to run under the AD4129-4 to prevent noise coupling. The power supply lines to the AD4129-4 must use as wide a trace as possible to provide low impedance paths and reduce glitches on the power supply line. Shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side. If using the AD4129-4 with split supply operation, a separate plane must be used for AVSS. ASSEMBLY GUIDELINES For the WLCSP, heat is transferred through the solder balls to the PCB. Thermal impedance is dependent on PCB construction. More copper layers and ground through remove heat more effectively. The PCB level reliability of the device is directly linked to the PCB type and design used. Using a PCB material that matches the coefficient of thermal expansion (CTE) of the silicon (for example, ceramic) provides the optimal mechanical performance. For organic material PCBs (for example, FR4) where the CTE is different from that of the silicon, the use of underfill can increase the mechanical performance. For organic PCB thickness >0.8 mm, consider using underfill. Give particular attention to the underfill material selection to match the material properties with the application use conditions. Consider using low alpha material in the system assembly to reduce the soft error rate (SER). The AN-617 Application Note provides information on PCB layout and assembly for the WLCSP.
analog.com Rev. A | 79 of 110 The AN-772 Application Note provides information on PCB layout and assembly for the LFCSP.
Table 73. User Configuration Register Names and Descriptions1 1 Blank cells are not applicable. 3 See the Identification Register section for details. 4 CHANNEL_0 default value is 0x800100. All other channels default value is 0x000100. the GAIN_n registers of the device as default value. Table 74. User Configuration Register Summary1
Table 74. User Configuration Register Summary1 (Continued)
1 Blank cells are not applicable. 3 See the Identification Register section for details. 4 CHANNEL_0 default value is 0x800100. All other channels default value is 0x000100. the GAIN_n registers of the device as default value. All communications to the device must start with a write operation to the communications register. Table 75. Bit Descriptions for COMMS Register written to the WEN bit, the next seven bits are loaded to the communications register. operation is a read from the designated register. communication. See Table 74 for a list of all registers and relative addresses.
ADC and interface status information register. Table 76. Bit Descriptions for Status Register 7 RDYB Active Low ADC Data Ready Indicator. The RDYB bit is used to indicate availability of ADC data. Because the RDYB bit is treated as an interrupt event, when it is set to 0, the data ready pin goes low. Conversely, the data ready pin automatically clears (goes high) when the RDYB bit is set to 1. register does not affect this bit. is written, that write is aborted. There is no mixing of data values, but one ADC conversion is missed. automatically cleared once there are no errors in the error register. when the user reads the status register. being converted. These values are a direct map from the CHANNEL_m register currently active. CHANNEL_0 results in CH_ACTIVE = 0b0000 while CHANNEL_15 results in CH_ACTIVE = 0b1111.
Controls the operation mode of the ADC. Table 77. Bit Descriptions for ADC_CONTROL Register conversion is performed on a bipolar input span. 0 Straight Binary (Unipolar) Coding. Input range: 0 V to VREF/gain. used in conjunction with the INT_REF_EN bit in this same register. edge to the DOUT pin disable time when the CSB_EN bit is set to 0 in the ADC_CONTROL register. continuous read mode, it is not required to write to the COMMS register before reading ADC data. continuous read mode, issue a software reset command (64 1s) or write a read data command (0x42). No CRC is required if CRC is enabled. This feature is disabled if the FIFO is enabled. 0 Continuous Read Mode Disabled. 1 Continuous Read Mode Enabled.
Table 77. Bit Descriptions for ADC_CONTROL Register (Continued) be held high to tristate the DOUT (WLCSP) or DOUT/RDY (LFCSP) pin. (WLCSP) or DOUT/RDY (LFCSP) pin is tristated. REFOUT pin depends on the setting of INT_REF_VAL bit in this same register. 0 Internal Reference Disabled (Default). 1 Internal Reference Enabled. to be effective, the MODE bitfield in this register must be set to duty cycling mode (0b1001). 0 1/4 Duty Cycle. The device is active 1/4 of the time and in standby for 3/4 of the time. 1 1/16 Duty Cycle. The device is active 1/16 of the time and in standby for 15/16 of the time. 0000 Continuous Conversion Mode. accidental/unwanted transitions to power-down mode. 0100 Idle Mode. The digital filter and the modulator are held in reset. There is no change to anything else. 0101 Internal Offset Calibration (Zero Scale). The device returns to idle mode once calibration is completed. 0110Internal Gain Calibration (Full Scale). The device returns to idle mode once calibration is completed. 0111System Offset Calibration (Zero Scale). The device returns to idle mode once calibration is completed. 1000 System Gain Calibration (Full Scale). The device returns to idle mode once calibration is completed.
Table 79. Bit Descriptions for IO_CONTROL Register 0 Disabled. Clearing of FIFO contents via SYNC is disabled. 1 Enabled. Clearing of FIFO contents via SYNC is enabled. Unused (LFCSP) for the FIFO Interrupt signal. the CLK_SEL bit setting in the ADC_CONTROL register. GPO_CTRL_P0 bit of the IO_CONTROL register. (WLCSP) or DOUT/RDY pin (LFCSP). This option is unused for the FIFO interrupt signal. bit in the MISC register) and takes highest priority and overrides its other functions. 0 GPO Has Specific Input Function. 0 GPO Has Specific Input Function. Register) and takes highest priority and overrides its other functions. 0 GPO Has Specific Input Function.
Select output VBIAS on the analog input pins. Table 80. Bit Descriptions for VBIAS_CONTROL Register 0 VBIAS Disabled on This Pin. 1 VBIAS Enabled on This Pin. 0 VBIAS Disabled on This Pin. 1 VBIAS Enabled on This Pin. 0 VBIAS Disabled on This Pin. 1 VBIAS Enabled on This Pin. 0 VBIAS Disabled on This Pin. 1 VBIAS Enabled on This Pin. 0 VBIAS Disabled on This Pin. 1 VBIAS Enabled on This Pin. 0 VBIAS Disabled on This Pin. 1 VBIAS Enabled on This Pin.
Table 80. Bit Descriptions for VBIAS_CONTROL Register (Continued) 0 VBIAS Disabled on This Pin. 1 VBIAS Enabled on This Pin. 0 VBIAS Disabled on This Pin. 1 VBIAS Enabled on This Pin.
Table 82. Bit Descriptions for ERROR Register (Continued) 1 AINP OV/UV Error Detected. 1 AINM OV/UV Error Detected. error flag in the ERROR_EN register. 1 REFIN OV/UV Error Detected. modulator is in saturation. Enable this error flag in the ERROR_EN register. flag in the ERROR_EN register. frame are not multiples of eight. Enable this error flag in the ERROR_EN register. 1 SCLK Count Error Detected. address. Enable this error flag in the ERROR_EN register. address. Enable this error flag in the ERROR_EN register. is detected. Enable this error flag in the ERROR_EN register.
1 Memory Map CRC Error Detected. 0 ROM_CRC_ERR ROM CRC Error Flag. A CRC calculation is performed on the ROM contents upon power-up. Each bit in this register enables a flag in the error register. Table 83. Bit Descriptions for ERROR_EN Register the AINP overvoltage error seen in the error register. 0 AINP OV/UV Error Disabled.
Table 83. Bit Descriptions for ERROR_EN Register (Continued) the AINM overvoltage/undervoltage error seen in the error register. 0 AINM OV/UV Error Disabled. 0 REFIN OV/UV Error Disabled. 1 REFIN OV/UV Error Enabled. reference error seen in the error register. ADC_ERR seen in the error register. memory map while offset or gain calibration is performed. 0 SPI Ignore Error Disabled. to 1 in ADC_CONTROL. The error is reported via SPI_READ_ERR in the error register. The SPI_READ_ERR bit is flagged if the user attempts to read an invalid address. in ADC_CONTROL. The error is reported via SPI_WRITE_ERR in the error register.
0 SPI CRC Check is Disabled. CONT_READ bit changes to 0 in ADC_CONTROL. 0 ROM CRC/ECC Check Disabled. 1 ROM CRC/ECC Check Enabled. Returns the MCLK count value when functionality is enabled. Table 84. Bit Descriptions for MCLK_COUNT Register giving it an update rate of 586.26 Hz. The 8‑ bit counter wraps around on reaching its maximum value. Enable the MCLK counter functionality using the MCLK_CNT_EN bit in the ERROR_EN register.
each channel. An ADC setup is made up of configuration, filter, offset, and gain registers. Table 85. Bit Descriptions for CHANNEL_m Registers 23 ENABLE_m Enable Bit for Channel m. This bit enables the relative channel to take part in the sequence. channel that corresponds to the data being read. to these bits on all active channels, or up to eight channels can be configured differently.
Table 85. Bit Descriptions for CHANNEL_m Registers (Continued) STBY_PDSW_EN bit in the MISC register is set to 0. 0 Power-Down Switch Off. The power-down switch is always disabled for this channel. 1 Power-Down Switch On. This allows the PSW pin to sink current. connected to the positive input for this channel. 10100(AVDD − AVSS)/6+. Use in conjunction with (AVDD − AVSS)/6− to monitor supply AVDD − AVSS. 10101(AVDD − AVSS)/6−. Use in conjunction with (AVDD − AVSS)/6+ to monitor supply AVDD − AVSS. 10110(IOVDD − DGND)/6+. Use in conjunction with (IOVDD − DGND)/6− to monitor IOVDD − DGND. 10111(IOVDD − DGND)/6−. Use in conjunction with (IOVDD − DGND)/6+ to monitor IOVDD − DGND. 11000(ALDO − AVSS)/6+. Use in conjunction with (ALDO − AVSS)/6− to monitor the analog LDO. 11001(ALDO − AVSS)/6−. Use in conjunction with (ALDO − AVSS)/6+ to monitor the analog LDO. 11010(DLDO − DGND)/6+. Use in conjunction with (DLDO − DGND)/6− to monitor the digital LDO. 11011(DLDO − DGND)/6−. Use in conjunction with (DLDO − DGND)/6+ to monitor the digital LDO.
11100V_MV_P. Use in conjunction with V_MV_M to apply a tens of mVP-P signal to the ADC. connected to the negative input for this channel. 10100(AVDD − AVSS)/6+. Use in conjunction with (AVDD − AVSS)/6− to monitor supply AVDD − AVSS. 10101(AVDD − AVSS)/6−. Use in conjunction with (AVDD − AVSS)/6+ to monitor supply AVDD − AVSS. 10110(IOVDD − DGND)/6+. Use in conjunction with (IOVDD − DGND)/6− to monitor IOVDD − DGND. 10111(IOVDD − DGND)/6−. Use in conjunction with (IOVDD − DGND)/6+ to monitor IOVDD − DGND. 11000(ALDO − AVSS)/6+. Use in conjunction with (ALDO − AVSS)/6− to monitor the analog LDO. 11001(ALDO − AVSS)/6−. Use in conjunction with (ALDO − AVSS)/6+ to monitor the analog LDO. 11010(DLDO − DGND)/6+. Use in conjunction with (DLDO − DGND)/6− to monitor the digital LDO. 11011(DLDO − DGND)/6−. Use in conjunction with (DLDO − DGND)/6+ to monitor the digital LDO. 11100V_MV_P. Use in conjunction with V_MV_M to apply a tens of mVP-P signal to the ADC. 11101V_MV_M. Use in conjunction with V_MV_P to apply a tens of mVP-P signal to the ADC. 0000 I_OUT1 is available on AIN0. 0001 I_OUT1 is available on AIN1. 0100 I_OUT1 is available on AIN2.
0101 I_OUT1 is available on AIN3. 1010 I_OUT1 is available on AIN4. 1011I_OUT1 is available on AIN5. 1110I_OUT1 is available on AIN6. 1111I_OUT1 is available on AIN7. 0000 I_OUT0 is available on AIN0. 0001 I_OUT0 is available on AIN1. 0100 I_OUT0 is available on AIN2. 0101 I_OUT0 is available on AIN3. 1010 I_OUT0 is available on AIN4. 1011I_OUT0 is available on AIN5. 1110I_OUT0 is available on AIN6. 1111I_OUT0 is available on AIN7.
up to seven different ADC setups to be selected in the CHANNEL_m registers. Table 86. Bit Descriptions for CONFIG_n Registers 01 Burnout Current = 0.5 μA. 0 Buffer Bypass on REFIN(+).
Table 86. Bit Descriptions for CONFIG_n Registers (Continued) 0 Buffer Bypass on REFIN(−).
01 REFIN2(+), REFIN2(−)
10 REFOUT, AVSS. Internal reference. CONFIG_n register is set, the PGA_n bits are ignored, and the gain is fixed at 1. field of the same CONFIG_n register are ignored.
specifying the SETUP_m bitfields. Table 87. Bit Descriptions for FILTER_n Registers subsequent repeated conversions determined by the REPEAT_n bits values. any calibration mode is enabled. 0001 Sinc4 + sinc1. Sinc4 averaging mode filter. 50 Hz/60 Hz rejection at a 50 SPS update rate. 0100 Sinc3 + sinc1. Sinc3 averaging mode filter. 0110Sinc3 + Post Filter 2. ODR (Hz) = 24 SPS.
Includes settings for oscillator, LDO, calibration and standby mode configuration. Table 90. Bit Descriptions for MISC Register voltage and improves the outcome of internal gain calibration. determine if P2 is enabled and its value, respectively. 1 Standby Signal to P2 (AIN3).
Table 90. Bit Descriptions for MISC Register (Continued) 0 Diagnostics Disabled in Standby Mode. 1 Diagnostics Enabled in Standby Mode. 0 GPO Disabled in Standby Mode. 1 GPO Enabled in Standby Mode. 0 Power-Down Switch Disabled in Standby Mode. is in standby for the channels using ADC Setup n. 0 Burnout Currents Disabled in Standby Mode. for the channels using ADC Setup n. 0 VBIAS Disabled in Standby Mode. VBIAS is enabled for the respective AINx pin. 0 Excitation Currents Disabled in Standby Mode. 0 Reference Holder Disabled in Standby Mode. 1 Reference Holder Enabled in Standby Mode. 0 Internal Reference and REFOUT Buffer Disabled in Standby Mode.
1 Internal Reference and REFOUT Buffer Enabled in Standby Mode
Control bits for operating the FIFO buffer. Table 91. Bit Descriptions for FIFO_CONTROL Register
Table 91. Bit Descriptions for FIFO_CONTROL Register (Continued) interrupt event in the selected interrupt pin. 0 FIFO Write Error Interrupt Disabled. 1 FIFO Write Error Interrupt Enabled. interrupt event in the selected interrupt pin. 0 FIFO Read Error Interrupt Disabled. 1 FIFO Read Error Interrupt Enabled. an interrupt event in the selected interrupt pin. 0 FIFO High Threshold Interrupt Disabled. 1 FIFO High Threshold Interrupt Enabled. an interrupt event in the selected interrupt pin. 0 FIFO Low Threshold Interrupt Disabled. 1 FIFO Low Threshold Interrupt Enabled. 0 FIFO Overrun Interrupt Disabled. 1 FIFO Overrun Interrupt Enabled. event in the selected interrupt pin. 0 FIFO Watermark Interrupt Disabled. 1 FIFO Watermark Interrupt Enabled. 0 FIFO Empty Interrupt Disabled. 1 FIFO Empty Interrupt Enabled. WATERMARK_FLAG is asserted in the FIFO_STATUS register. 0x00: 256 conversions (entire FIFO length). 0x01: 1 conversion (not recommended).
Contains error flags for the FIFO, which are only triggered when the FIFO is either in watermark mode or streaming mode. Table 92. Bit Descriptions for FIFO_STATUS Register MAIN_ERR bit of the status register is also set to 1 when this MAIN_ERR bit is set to 1. to this error sets and clears together with the error flag. 1 FIFO Write Error Detected. is emptied. An interrupt associated with this flag sets and clears together with the bit.
Table 92. Bit Descriptions for FIFO_STATUS Register (Continued) 1 FIFO High Threshold Flag Triggered. associated with this flag sets and clears together with the bit. 1 FIFO Low Threshold Flag Triggered. watermark field. An interrupt associated with this flag sets and clears together with the bit. FIFO. An interrupt associated with this flag sets and clears together with the bit. Contains upper and lower FIFO threshold values.
Table 93. Bit Descriptions for FIFO_THRESHOLD Register Table 94. Bit Descriptions for FIFO_DATA Register
©2024-2025 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. A | 110 of 110 Package Drawing (Option) Package Type Package Description CP-32-29 LFCSP 32-Lead Lead Frame Chip Scale Package CB-35-3 WLCSP 35-Ball Wafer Level Chip Scale Package For the latest package outline information and land patterns (footprints), go to Package Index. Updated: April 20, 2024 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option AD4129-4BCBZ-RL7 -40°C to +105°C 35-Ball WLCSP Reel, 1500 CB-35-3 AD4129-4BCPZ-RL7 -40°C to +125°C 32-Lead LFCSP Reel, 1500 CP-32-29 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1, 2 Description EVAL-AD4129-8WARDZ Evaluation Board EVAL-SDP-CK1Z Evaluation Board 1 Z = RoHS Compliant Part. 2 The EVAL-AD4129-8WARDZ can be used to evaluate the AD4129-4.