AD4110-1

AD4110-1 (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 74

Technical content

Universal Input Analog Front End with 24-Bit ADC for Industrial Process Control Systems Data Sheet AD4110-1 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

2 software programmable input terminals Current up to ±20 mA Voltage up to ±10 V Thermocouple RTD Replaces existing 3-terminal solutions Field power supply for loop powered current sensors HV input overvoltage protected up to ±30 V Internal current sense resistor Option to use external current sense resistor Current limited input even with no power supply Diagnostic functions for overrange and open wire detect Fast and flexible output data rates: 5 SPS to 125 kSPS 16 noise free bits at 62 kSPS 18 noise free bits at 2.5 kSPS 20 noise free bits at 50 SPS/60 SPS Simultaneous 50 Hz and 60 Hz rejection Serial interface for configuration and diagnostics 4-wire interface compatible with SPI®, QSPI™, MICROWIRE®, and DSP Power supply: ±12 V to ±20 V, +5 V Operating temperature: −40°C to +105°C Package: 40-lead, 6 mm × 6 mm LFCSP

APPLICATIONS

Process control and industrial automation Remote and distributed control systems Instrumentation and measurement Sensor and data acquisition GENERAL DESCRIPTION The AD4110-1 is a complete, single-channel, universal input analog-to-digital front end for industrial process control systems where sensor type flexibility is required. The high voltage input is fully software configurable for current or voltage signals and allows direct interface to all standard industrial analog signal sources such as ±20 mA, ±4 mA to ±20 mA, ±10 V , and all thermocouple types. Field power can be supplied for loop powered current output sensors. A range of excitation current sources for resistance temperature detector (RTD) sensors and other resistive sensors are included. The integrated, fully differential programmable gain amplifier (PGA) offers 16 gain settings from 0.2 to 24. The high voltage input can be programmed to power up in either voltage mode or current mode. When programmed to current mode, the unique input circuit architecture provides a path for the loop current, even in the absence of the system module power supply. The AD4110-1 provides internal, front-end diagnostic functions to indicate overvoltage, undervoltage, open wire, overcurrent, and overtemperature conditions. The high voltage input is thermally protected, overcurrent limited, and overvoltage protected. The AD4110-1 incorporates a precision 24-bit, Σ-Δ, analog-to- digital converter (ADC) offering conversion rates from 5 SPS to 125 kSPS with simultaneous 50 Hz and 60 Hz noise rejection. FUNCTIONAL BLOCK DIAGRAM AD4110-1 AGND ADR0 ADR1 C(+) C(–) DGND REF(–) REF(+) REFOUT

24 BIT Σ-∆ ADC

1.8V LDO AVDD5ADCAVDD 1.8V LDO IOVDD ADCDVDD AFE/ADC SERIAL INTERFACE CRC OVERTEMPERATURE SENSOR DIGITAL FILTERING PROCESSING AND CONTROL SCLK DIN MUX MULTIPLEXER PGA RTD iREFS iREFF AIN(+) EXRF EXRS AIN(–) IN(+) IN(–) RTD 2-WIRE 3-WIRE 4-WIRE RTD AGND FIELD SENSORS iEXC iCOMP VDD VSS VDD VSS VDD VSS AGND RSENSE FIELD POWER SUPPLY VBIAS CS DOUT/RDY ERR SYNC CLKIO REF CLKIO AINCOM(LV)AIN1(LV) AIN2(LV) NO POWER MODE SWITCH CONTROL DIAGNOSTICS RSENSE CHANNEL SELECT VPP VDD VSS AGND NC AGND IOVDDAVDD5 16269-001 ±4mA TO ±20mA TRANSMITTER ±10V TRANSDUCER THERMOCOUPLE Figure 1. Functional Block Diagram

Rev. 0 | Page 2 of 74 TABLE OF CONTENTS Changing The Default Mode of Operation for Future Power-

Rev. 0 | Page 3 of 74

REVISION HISTORY

3/2019—Revision 0: Initial Version

Rev. 0 | Page 4 of 74 SPECIFICATIONS VDD = +12 V to 20 V , VSS = −12 V to −20 V , AVDD5 = +5 V , IOVDD = +5 V , AGND = DGND = 0 V , VBIAS function = off, REFIN(+) = 2.5 V (external reference), REFIN(−) = 0 V , MCLK = 8 MHz (internal ADC clock), TA = −40°C to +105°C, all gains, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments HIGH VOLTAGE ANALOG INPUTS, AIN(±) Pins Differential Input Voltage Range, Reference Voltage (VREF) ≤ 2.5 V −VREF/Gain +VREF/Gain V For specified performance, gain > 0.2 −10 +10 V For specified performance, gain = 0.2 −12.5 +12.5 V Functional range, gain = 0.2 Absolute AIN Voltage VSS + 3 VDD − 3 V For specified performance Overvoltage Protection1, 2 AIN(+) – AGND, AIN(–) – AGND, AIN(+) – AIN(–) Pins ±30 V Using input resistor-capacitor (RC) low- pass filter with resistor (R) = 10 Ω, 0.5 W and capacitor (C) = 47 nF 50 V, VDD/VSS ≤ ±15 V VOLTAGE INPUT MODE Gain Error Before Calibration3 −1 +1 % TA = 25°C Using Calibration Coefficient4 −0.03 +0.03 % TA = 25°C, VDD/VSS = ±15 V Gain Drift vs. Temperature2 −3 +3 ppm/°C All gains except gain = 1 −8 +8 ppm/°C Gain = 1 Gain Drift vs. Time5 ±30 ppm Over 1000 hours Input Offset Error6 −350/Gain +350/Gain µV Gain = 0.2 to 3 −100 +100 µV Gain = 4 to 24 Input Offset Drift vs. Temperature2 2 14 µV/°C Gain = 0.2, referred to input 0.2 0.5 µV/°C Gain = 24, referred to input Input Offset Drift vs. Time5 ±50 µV Gain = 0.2, over 1000 hours ±25 µV Gain = 1, over 1000 hours ±4 µV Gain = 24, over 1000 hours Integral Nonlinearity 6 ppm/FSR Gain = 0.2, full-scale range (FSR) = 2 × full scale (FS) 25 75 ppm/FSR Gain = 24 Input Bias Current, AIN(+), AIN(−) Pins2 −0.5 +0.5 µA Input Bias Current, AIN(+) Pin −0.25 −0.15 −0.05 µA AIN(+) − AIN(−) < ±100 mV, AIN(−) =

0 V, VBIAS on/off, gain = 24, source

impedance < 5 kΩ Input Bias Current Drift2 1 2.5 nA/°C AIN(+) and AIN(−) Input Offset Current2 −100 +100 nA Input Impedance7 >1 GΩ ΔVIN ÷ ΔIIN Input Voltage Noise and Resolution2 See Table 16 to Table 21 Input Common-Mode Rejection, DC 125 dB Gain = 24 100 dB Gain = 0.2 Input Common-Mode Rejection, AC 130 dB 50 Hz/60 Hz Power Supply Rejection, DC8 120 dB Related to VSS and VDD 83 dB Related to AVDD5, gain = 1, VIN = 1 V Normal Mode Rejection, 50 Hz/60 Hz 40 dB Sinc5 + sinc1 filter, ±0.5 Hz, external clock 100 dB Sinc3 filter, ±1 Hz

Rev. 0 | Page 5 of 74 Parameter Min Typ Max Unit Test Conditions/Comments CURRENT INPUT MODE USING INTERNAL SENSE RESISTOR9 Gain = 4 Input Current Range10 −20 +20 mA Specified performance range −24 +24 mA Functional range Transimpedance Gain 96 mV/mA Gain = 4, sense resistor (RSENSE) = 24 Ω Gain Error Before Calibration3 ±30 % Using Calibration Coefficient4 −0.1 +0.1 % TA = 25°C, IIN = 20 mA Gain Drift vs. Temperature2 −50 +50 ppm/°C Excludes reference drift, includes RSENSE resistor drift Gain Drift vs. Time5 250 ppm Over 1000 hours Input Offset Error −5 +5 µA Input Offset Drift vs. Temperature2 50 nA/°C Input Offset Drift vs. Time5 ±200 nA Over 1000 hours Integral Nonlinearity 25 75 ppm/FSR FSR = 2 × FS Input Overcurrent Detection ±35 mA Input Current Internal Limit10 ±40 mA Overcurrent self-protection Input Impedance2, 11 30 45 60 Ω I nput current <±24 mA Input Current Noise and Resolution See Table 16 to Table 21 Input Common-Mode Rejection, DC 0.15 µA/V Power Supply Rejection, DC8 0.01 µA/V Related to VDD and VSS CURRENT INPUT MODE USING EXTERNAL SENSE RESISTOR12, 13 E xternal sense resistor (REXT) = 200 Ω, g ain = 0.5 Input Current Range7 −20 +20 mA Specified performance range −24 +24 mA Functional range Input Overcurrent Detection ±35 mA Input Current Internal Limit7 ±40 mA Overcurrent self-protection Gain Drift vs. Temperature2 2.5 ppm/°C Excludes reference drift and drift of external sense resistor ADC SPEED AND PERFORMANCE Output Data Rate2 5 125,000 SPS No Missing Codes2 24 Bits Sinc5 + sinc1 filter setting Resolution See Table 16 to Table 21 NO POWER SUPPLY MODE Input Voltage Drop 5 V Current mode, input current = 24 mA Input Current Internal Limit2 ±55 ±70 mA Current mode, overcurrent self- protection Input Current Loss 70 µA Current mode, 24 mA, GND connected Input Current in Voltage Mode ±0.5 mA Voltage mode FIELD POWER SUPPLY MODE Output Voltage, AIN(+) Pin2 VDD − 2.5 VDD − 1.5 V Output current = 24 mA VDD − 0.1 VDD V No load Output Current, AIN(+) Pin −24 mA Output Current Limit, AIN(+) Pin2 −35 −45 −55 mA Overcurrent self-protection Voltage, AIN(−) Pin2 VSS + 3.6 VSS + 4.2 V AIN(−) with 24 mA, no VSS diode VSS + 2.2 VSS + 2.7 V No load, no VSS diode Input Current Limit, AIN(−) Pin +40 mA

Rev. 0 | Page 6 of 74 Parameter Min Typ Max Unit Test Conditions/Comments RTD EXCITATION CURRENTS14 External reference voltage (VREF) =

2.5 V ± 0%

Current Outputs 0.1 to 1 mA Programmable (see Table 30) Initial Error, Internal Reference Resistor −0.3 +0.3 % Current ≥ 400 µA, TA = 25°C −1 +1 % Current = 100 µA, TA = 25°C Initial Drift 130 ppm See Figure 44 and Figure 45 Drift vs. Temperature2 −45 +45 ppm/°C Internal reference resistor (including reference resistor drift) −18 +18 ppm/°C External reference resistor (excluding reference resistor drift) Drift vs. Time5, 15 150 ppm Internal resistor, over 1000 hours 150 ppm External resistor, over 1000 hours Load Regulation2 0.01 %/V Line Regulation2 4 ppm/V Related to VSS and VDD Noise2 See Table 22 and Table 23 TA = 25°C Current Matching15 0.05 % AIN(+) and AIN(−) pins, excludes 100 µA Current Matching Drift 0.0002 %/°C AIN(+) and AIN(−) pins, excludes 100 µA Compliance VDD − 5 V REFERENCE VOLTAGE (INPUT) Reference Voltage Input, VREF2, 14 1 2.5 AVDD5 – 1.6 V REFIN(+) − REFIN(−) = VREF RTD mode disabled 2.45 2.5 2.55 V RTD mode enabled VREF Input Current 200 nA VREF+ reference buffer on 100 µA VREF− reference buffer on 36 µA/V VREF+ reference buffer off 75 µA/V VREF− reference buffer off VREF Input Current Drift 1.3 nA/°C VREF+ reference buffer on −3.5 nA/°C VREF− reference buffer on 10 nA/V/°C VREF+ reference buffer off 10 nA/V/°C VREF− reference buffer off AGND AVDD5 V Reference buffer on Common-Mode Rejection 95 dB REFERENCE VOLTAGE (OUTPUT) Output Voltage 2.5 V REFOUT pin Initial Accuracy2 −0.16 +0.16 V TA = 25°C Temperature Coefficient2 10 50 ppm/°C Long Term Stability5 600 ppm Over 1000 hours Reference Load Current, ILOAD 10 mA Power Supply Rejection 93 dB Load Regulation 75 µV/mA VBIAS Voltage AGND V Output Current Limit ±50 µA Source or sink, depending on the AIN(−) pin potential referenced to AGND OPEN WIRE DETECTION CURRENTS Current Output ±0.71 ±1 ±1.45 µA ±100 µA Compliance VSS + 2 VDD − 2 V

Rev. 0 | Page 7 of 74 Parameter Min Typ Max Unit Test Conditions/Comments INPUT OVERVOLTAGE DETECTION Positive Overvoltage Threshold VDD − 2.0 VDD − 2.8 V Negative Overvoltage Threshold VSS + 2.0 VSS + 2.8 V OVERTEMPERATURE PROTECTION Overtemperature Detection Threshold 120 °C Junction temperature Thermal Shutdown Threshold 145 °C Junction temperature Thermal Shutdown Hysteresis 30 °C ANTIALIASING FILTER RESISTOR AIN(±) to C(±) Resistance 1600 Ω Includes internal switch resistance Resistance Variation2 ±35 % Mismatch 0.2 % Resistor pair per channel LOW VOLTAGE ANALOG INPUTS, AIN1(LV), AIN2(LV), AND AINCOM(LV) Differential Input Range ±VREF V Input Current ±65 nA Input Current Drift ±75 pA/°C AGND + 0.2 V to AVDD5 – 0.2 V ±1 nA/°C AGND to AVDD5 High Voltage (HV) to Low Voltage (LV) Channel Crosstalk16 −120 dB Input frequency (fIN) = 1 kHz, Gain (HV Channel) = 1 Input Common-Mode Rejection, DC 95 dB Input Common-Mode Rejection, AC 120 dB 50 Hz/60 Hz, V IN = 1 V DIGITAL INPUTS Input High Voltage, VIH2 0.7 × IOVDD V IOVDD = 2 V to 5.5 V Input Low Voltage, VIL2 0.8 V IOVDD = 3.3 V to 5.5 V

0.4 V IOVDD = 2 V

Input Leakage Current −10 +10 μA Input Pin Capacitance 10 pF DIGITAL OUTPUTS VOH2 0.8 × IOVDD V IOVDD = 5 V, source current (ISOURCE) = 1 mA 0.8 × IOVDD V IOVDD = 3.3 V, I SOURCE = 500 μA 0.8 × IOVDD V IOVDD = 2 V, I SOURCE = 500 μA VOL2 0.4 V IOVDD = 5 V, sink current (I SINK) = 2 mA 0.4 V IOVDD = 3.3 V, I SINK = 1 mA

0.4 V IOVDD = 2 V, I SINK = 1 mA

Floating State Leakage Current −10 +10 μA Floating State Output Capacitance 12 pF ERROR OUTPUT (OPEN DRAIN) Output Low Voltage, VOL 0.4 V I SINK = −100 μA Output High Leakage Current, IOH −10 +10 μA Output voltage (V OUT) = 5 V CLOCK INPUT/OUTPUT Internal Oscillator 8 MHz Internal Oscillator Accuracy −3.5 +3.5 % ADC clock Clock Input Frequency 8 MHz Duty Cycle, External Clock2 45 50 55 % VIH2 0.8 × IOVDD V VOH 0.8 × IOVDD V VOL 0.4 V VIL2 0.4 V

Rev. 0 | Page 8 of 74 Parameter Min Typ Max Unit Test Conditions/Comments Input Leakage Current −10 +10 µA Pin Capacitance 12 pF Duty Cycle, Internal Clock 50 % POWER REQUIREMENTS See the Power Supply Sequence section VDD − VSS Voltage 24 30 40 V AGND Voltage (VDD − VSS)/2 V AVDD5 − AGND Voltage 4.5 5 5.5 V DGND Voltage AGND V IOVDD − DGND Voltage 2.0 5 5.5 V VDD Supply Current Field Power Supply Off 5.5 8 mA All current sources off and disabled 7.5 10 mA RTD current sources on, other current sources off, VBIAS off Field Power Supply On2 29.5 mA Field power supply current = 24 mA to AGND, all current sources off and disabled, VBIAS off VSS Supply Current Field Power Supply Off −5.5 −8 mA All current sources off and disabled −5.5 −10 mA RTD current sources on, other current sources off, VBIAS off Field Power Supply On2 −5.8 mA Field power supply current = 24 mA to AGND, all current sources off and disabled, VBIAS off AVDD5 Supply Current 10 12 mA IOVDD Supply Current 2.5 3.5 mA 1 The device is specified to operate with an input voltage from VSS + 3 V to VDD − 3 V on any AIN(±) pin. The device is protected against overvoltage on the AIN(+) and AIN(−) pins up to ±30 V (referred to the AGND supply). The limitation of VDD = VSS ≤ ± 15 V only applies when field power supply mode is enabled. Applying a voltage to a high voltage pin that is more negative than the potential of the system negative power supply can only be accomplished by connecting an external diode from the VSS pin to the system negative power supply (see Figure 29). The absolute maximum ratings must not be exceeded at any time (see Table 3). 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 Gain error prior to applying software error correction algorithm. See the Gain Calibration Data Register section. 4 Gain error after applying software error correction algorithm. See the Gain Calibration Application Examples section. 5 Data based on the following test methods: - Moisture/Reflow Sensitivity (MSL) Classification for nonhermetic Solid State Surface Mount Devices and High Temperature Operating Life (HTOL). 6 Offset voltage seen at the inputs in voltage mode. Note that RTD currents can cause an additional I × R offset voltage (±V) due to any mismatch in IC or PCB trace resistance. System calibration may be required when changing RTD excitation and compensation current levels. 7 DC input impedance is derived from measuring the change in input current for a change in input voltage, (ΔVIN ÷ ΔIIN). 8 Referred to input. 9 PGA gain = 4 for all specifications related to the current input mode with internal sense resistor. 10 Input current in current input mode must be within ±20 mA for fully specified performance. The device is functional up to ±24 mA. The internal protection limits the input overcurrent to approximately 40 mA. 11 Current mode input impedance is the total impedance between the AIN(+) and AIN(−) pins, which includes the on-chip sense resistor, on-chip current mode switches, and other on-chip circuits. The relationship between the analog input current and the analog output voltage is represented by the gain and offset specifications. 12 REXT = 200 Ω an d gain = 0.5 for all specifications related to the current input mode with external sense resistor. 13 The external resistor transfers the input current to a voltage for additional signal processing in this mode. The AD4110-1 specifications exclude the effect of any changes in the external resistor resistance. Performance of the external resistor must be considered to assess system performance in this mode. 14 The AD4110-1 RTD excitation currents are designed to operate with a 2.5 V reference voltage. The AD4110-1 RTD excitation current value scales proportionally to small changes in the VREF input voltage. The AD4110-1 RTD excitation current specifications exclude the effect of any changes in the VREF input voltage. 15 RTD current source enabled and current flowing continuously. 16 This specification relates to the worst high voltage and low voltage channel pair. A 20 V p-p, 1 kHz sine wave input on the HV channel is attenuated by this amount on the other LV channels. The interferer signal is applied to an unselected channel. The filter network connected to C(+) and C(−) is implemented as shown in Figure 29. There is no filter network implemented on the input terminals.

TA = 25°C, unless otherwise noted. 1 HV pins are AIN(+), AIN(−), RTD, EXRS, and EXRF.

2 Applying a voltage to an HV pin that is more negative than the potential of

3 Pins with the same name must be shorted together. 4 Using an input RC low-pass filter with R = 10 Ω, 0.5 W and C = 47 nF, 50 V.

5 It is recommended to short AGND and DGND pins together as close to the

PCB thermal design is required. Table 4. Thermal Resistance are based on simulated data.

1. NIC = NOT INTERNALLY CONNECTED.
2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A PAD ON THE PCB TO

Figure 4. Pin Configuration Table 5. Pin Function Descriptions1 1 REFIN(−) Reference Input Negative. This pin works with the REFIN(+) pin. Connect to AGND. excitation current functionality operates with a 2.5 V reference only. external resistor. Connect this pin and the iREFS pin in a star point to the top of the external precision resistor. more information, see the RTD Mode section. No other circuit connections are allowed. and iREFF pins. For more information, see the RTD Mode section. No other circuit connections are allowed. 6 ADCAVDD Decoupling Node for the Internal Linear Regulator Output. Decouple this pin using a 1 µF capacitor to AGND (Pin 7). close to the device as possible. together as close to the device as possible. 9 AVDD5 Analog Power Supply (5 V). Power supply for the ADC core. 10 NIC Not internally connected. 11 AVDD5 Analog Power Supply (5 V). Power supply for the AFE.

Rev. 0 | Page 12 of 74 Pin No. Mnemonic Description 13 CLKIO Clock Input/Output. This pin is the input for an external clock or the output of the on-chip clock. 14 DOUT/RDY Serial Interface Data Output (DOUT). This pin functions as a serial data output to access the output register of the ADC. The data is placed on the DOUT/RDY pin after the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is tristated. D ata Ready Output (RDY). When CS is low, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. 15 DIN Serial Interface Data Input. Digital input. 16 SCLK Serial Interface Clock. Digital input. 17 CS Serial Interface Chip Select/Frame. Digital input. 18 ERR Error Input/Output. Open-drain digital output. 19 SYNC ADC Synchronization Input. When SYNC is brought low, the ADC aborts any active ADC conversion, and brings RDY high if it is low. When SYNC is brought high, the ADC starts a new conversion within a number of clock cycles. If multiple ADC channels are enabled the conversions restart with the first channel in the sequence. 20, 21 IOVDD Digital Power Supply (2 V to 5 V). Power supply for digital inputs and outputs. 22 DGND Digital Ground (0 V). Reference ground for the digital inputs and outputs. It is recommended to short the AGND and DGND pins together as close to the device as possible. 23 ADCDVDD Decoupling Node for the Internal Linear Regulator Output. Decouple this pin using a 1 µF capacitor to DGND (Pin 22). 24, 25 ADR0, ADR1 Serial Interface Address. Digital input. 26 AINCOM(LV ) Low Voltage Analog Input. AIN1(LV) and AIN2(LV) are referenced to this pin when the device is configured in pseudo differential mode. 27 AIN1(LV) Low Voltage Analog Input. This input can be configured as a fully differential input with AIN2(LV) or as a single- ended or pseudo differential input when configured for use with AINCOM(LV). 28 AIN2(LV) Low Voltage Analog Input. This input can be configured as a fully differential input with AIN1(LV) or as a single- ended or pseudo differential input when configured for use with AINCOM(LV). 29 C(−) Capacitor Terminal Negative. Filter capacitors can be connected between this pin and C(+) and/or between this pin and analog ground (AGND). No other circuit connections are allowed. 30 C(+) Capacitor Terminal Positive. Filter capacitors can be connected between this pin and C(−) and/or between this pin and analog ground (AGND). No other circuit connections are allowed. 31 AIN(−) Analog Input Negative. In voltage mode, this pin is the negative input. In a 3-wire RTD connection, RTD compensation current flows out of this terminal. This pin also functions as the negative sense voltage terminal for the external sense resistor in current mode. 32 EXRS External Resistor Sense. Sense (voltage) terminal for an external sense resistor in current mode. 33 EXRF Ex ternal Resistor Force. Force (current) terminal for an external sense resistor in current mode. If an external sense resistor is not used in the application, this pin must be connected to the AIN(−) pin for current mode operation; that is, the external resistor must be replaced by a short connection or a 0 Ω re sistor. 34 AIN(+) Analog Input Positive. In voltage and current modes, this pin is the positive input. In a 3-wire RTD connection, RTD excitation current flows out of this terminal. This pin also functions as a positive field power supply output in field power supply mode. 35 RTD Resistance Temperature Detector Pin. In a 4-wire RTD connection, RTD excitation current flows out of this terminal. 36 VSS2 Negative Power Supply (−12 V to −20 V). A 10 µF decoupling capacitor is recommended. 37 VDD Positive Power Supply (12 V to 20 V). A 10 µF decoupling capacitor is recommended. 38 VPP Internal 5 V node. A decoupling capacitor must be connected to this pin; no other circuit connections are allowed. Connect a 0.1 µF ceramic capacitor between the VPP and the VSS pins. 39 VDD Positive Power Supply (12 V to 20 V). 40 VSS2 Negative Power Supply (−12 V to −20 V). EPAD VSS2 Exposed Pad. Solder the exposed pad to a pad on the PCB to confer mechanical strength to the package. The exposed pad must be connected to VSS. 1 Pins with the same name must be shorted together. 2 Applying a voltage to an HV pin that is more negative than the potential of the system negative power supply can only be accomplished by connecting an external diode from the VSS pin to the system negative power supply. See Figure 29 for the connection diagram.

Rev. 0 | Page 18 of 74 POWER SUPPLY SEQUENCE A power supply sequence is recommended for the AD4110-1, please see Table 6. After all power supplies are stable, a device reset is required. See the Resetting the AD4110-1 section. PROTECTION DIODE Applying a voltage to an HV pin that is more negative than the potential of the system negative power supply can only be accomplished by connecting an external diode from the VSS pin to the system negative power supply. A diode with a very low reverse leakage current should be considered. See Figure 29 for the connection diagram. ANALOG INPUT The AD4110-1 has one high voltage differential input, which can be configured to accept a voltage or current. When the input is a current, the internal resistor (R SENSE) can be used to convert the current to a voltage. Alternatively, a high precision external resistor can be used. PULL-UP/PULL-DOWN CURRENTS Each AD4110-1 high voltage input pin can use a pull-up or pull-down current. These currents can have a value of 1 µA or 100 µA and are used to detect the presence of an open wire. ANTIALIASING FILTER The AD4110-1 input pins are linked to the inputs of the internal PGA by a nominal series resistance of 1.6 kΩ. Using external capacitors on the C(±) pins, a first-order antialiasing filter can be implemented. A 0.1 µF capacitor is recommended because the differential capacitor and 0.01 µF capacitors to ground provide a −3 dB cutoff frequency at approximately 500 Hz. RTD EXCITATION CURRENTS The AD4110-1 high voltage input can connect to 2-wire, 3-wire, and 4-wire RTD sensors. The device includes two matched excitation currents that can be programmed to 100 µA, 400 µA, 500 µA, or any combination of these values. FIELD POWER SUPPLY MODE The AD4110-1 provides an option to power an external current output sensor connected between the AIN(+) and AIN(−) terminals with up to 24 mA. NO POWER SUPPLY MODE When the AD4110-1 is configured to power up in current mode and there is no power supply connected to VDD/VSS, the AD4110-1 can power itself from the ±4 mA to ±20 mA loop with limited functionality. Both the current path through the loop and the loop overcurrent protection are maintained. BIAS VOLTAGE GENERATOR The AD4110-1 incorporates a bias voltage generator (VBIAS) that can be used to connect the AIN(−) pin to AGND. See Figure 34 for an equivalent circuit diagram. This feature is software selectable and is included for applications where the sensor output signal is floating. PGA The PGA removes potentially large common-mode signals and subsequently applies gain or attenuates the input signal to maximize the resolution of the conversions from the ADC. CALIBRATION REGISTERS The AD4110-1 provides gain calibration registers that contain gain correction coefficients for all 16 gain settings in voltage mode. For current mode, there is one gain calibration register containing the gain correction coefficient for a gain of 4. SERIAL INTERFACE The AD4110-1 has a 4-wire serial peripheral interface (SPI). The on-chip registers are accessed via the serial interface. Up to four devices can be connected on the same SPI bus. The AD4110-1 has two address pins (ADR0 and ADR1) to set the address of each device. CLOCK The AD4110-1 has two internal 8 MHz clocks. For specified performance, it is recommended that the AFE be driven with the ADC clock. The internal clock can be made available on the CLKIO pin and an external clock can be supplied to the CLKIO pin. ADC The output of the high voltage analog front end is applied to the ADC input multiplexer. The 24-bit ADC is fully buffered (analog inputs and reference inputs) with a maximum output data rate of 125 kSPS. The Σ-Δ modulator output is digitally filtered. The AD4110-1 provides three separate types of digital filtering. The application selects one of these filter responses:

• Sinc5 + sinc1 averager for fast channel switching
• Sinc3 filter response to maximize rejection of interferers
• Enhanced filter set to maximize the simultaneous rejection of 50 Hz and 60 Hz while minimizing the settling time ADC FILTER REGISTERS The AD4110-1 provides four filter registers that allow different output data rates to be selected for the high voltage channel and the three low voltage channels. The filter registers share the same memory address. Therefore, when the filter register is written to, the contents are copied to the filter register for each channel enabled in the ADC_CONFIG register. ADC GAIN AND OFFSET REGISTERS The AD4110-1 provides four sets of gain and offset registers for each of the four channels, the high voltage channel and the three low voltage channels.

through a low impedance sense resistor for measurement. voltage mode after the next power cycle. operate as high impedance inputs.

1. Set the IMODE bit (Bit 1) in the AFE_CNTRL2 register

0 selects voltage mode (see Table 7 and Table 29).

1. Write the value 0x00B1 to the NO_PWR_DEFAULT_SEL

egister (Address 0xE, see Table 8).

1. Issue the refresh command (0x00A1) immediately to the

count value is loaded correctly. required to change the default mode of operation on power-up. AD4110-1 is disconnected for some reason. that the default power-up mode is current mode. The default mode of operation can be changed only 100 times. Table 6. Power Supply Sequence

1 VSS VDD AVDD5 IOVDD

2 VDD VSS AVDD5 IOVDD

3 VDD AVDD5 VSS IOVDD

4 VDD AVDD5 IOVDD VSS

use the CLKIO pin as its source (see Table 28 and Table 39).

• Set Bits[3:2] = 01 in the ADC_MODE register.
• Set Bits[4:3] = 10 in the AFE_CLK_CTRL register. When an external clock source is used, it is necessary to reconfigure the ADC clock to use the CLKIO pin as its source.
• Set Bits[3:2] = 10 in the ADC_MODE register.

Table 7. Bit Descriptions for the AFE_CNTRL2 Register Table 8. Bit Descriptions for the NO_PWR_DEFAULT_SEL and NO_PWR_DEFAULT_STATUS Registers

mode is bipolar (see Table 41). offset voltage, and is converted by the ADC as 0 V .

• Channel 1: AIN1(LV) − AIN2(LV)
• Channel 2: AIN1(LV) − AINCOM(LV)
• Channel 3: AIN2(LV) − AINCOM(LV) By default, these auxiliary channels are disabled. To enable the auxiliary channels, set Bits[3:1] of the ADC_CONFIG register (see Table 41). A set of gain, offset, and filter registers is available for each channel. These registers can be programmed separately from the registers for the main high voltage channel. DIGITAL FILTER Four digital filter registers on the AD4110-1 allow different output data rates to be selected for the high voltage channel and the three low voltage channels (see Table 43). The filter registers share the same memory address, therefore, when the filter register is written to, the contents are copied to the filter register for each channel enabled in the ADC_CONFIG register. CONTINUOUS CONVERSION MODE Continuous conversion mode on the high voltage channel is the default mode of operation for the ADC after power-up. The AD4110-1 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is complete. To read a conversion, the user writes to the commu- nications register indicating that the next operation is a read of the data register. When the data-word has been read from the data register, DOUT/RDY goes high. The application can read the data register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion; otherwise, the new conversion word is lost. Because he ADC conversion control logic and the SPI interface are not synchronized, take care when reading the ADC result register after CS is brought low (see the DOUT/RDY pin description in the Serial Peripheral Interface section for further details). INPUT AUTO SEQUENCING When more than one channel is enabled, the ADC automatically sequences through each channel and generate a conversion result. When all channels have been converted, the sequence starts again with the first channel. The channels are converted in order from lowest enabled channel to highest enabled channel. The data register is updated as soon as each conversion is available. The DOUT/RDYpin pulses low each time a conversion is available. The user can then read the conversion while the ADC converts the next enabled channel. The ADC data register conversion result contains no channel identification. Therefore, when more than one channel is enabled, it is necessary to append the contents of the ADC status register to the ADC data register. This is configured by setting Bit 6 of the ADC_INTERFACE register (see Table 9 and Table 40). A filter settling time is associated with switching channels. Therefore, the output data rate of the AD4110-1 is reduced, depending on the number of channels selected. See Table 16 to Table 21 for the channel filter settling time and switching rates. Because the input channels are multiplexed, an input settling time can be required before the ADC starts the conversion process. The AD4110-1 provides an ADC conversion delay feature, see the ADC Conversion Delay section.

Table 9. Bit Descriptions for the ADC_INTERFACE Register

Rev. 0 | Page 22 of 74 SINGLE CONVERSION MODE In single conversion mode, the AD4110-1 performs a single conversion, and is then placed in standby mode after the conversion is complete. DOUT/RDY goes low to indicate the completion of a conversion. When the data-word has been read from the data register, DOUT/RDY goes high. The data register can be read several times, if required, even when DOUT/RDY has gone high. To enable single conversion mode, set the MODE bits of the ADC_MODE register to 001, see Table 10 and Table 39 for details of the MODE bits If several channels are enabled, the ADC automatically sequences through the enabled channels and performs a conversion on each channel. When a conversion is started, DOUT/ RDY goes high and remains high until a valid conversion is available and CS is low. When the conversion is available, DOUT/RDY goes low. The ADC then selects the next channel and begins a conversion. The application can read the present conversion while the next conversion is being performed. When the next conversion is complete, the data register is updated. Therefore, the user has a limited period in which to read the conversion. When the ADC has performed a single conversion on each of the selected channels, it returns to standby mode. ADC CONVERSION DELAY When the AFE configuration is changed or more than one channel is enabled and the ADC is programmed to automatically sequence through each channel, an input signal settling time can be required before the ADC starts the conversion process. The AD4110-1 provides the capability to program a conversion delay from 8 µs to 2 ms (see Table 39 for programming options). For output data rates of 10.39 kSPS or less, the delay allows the data rate of the ADC to remain at the required update rate with only a minor impact on the resolution of the conversion result. The delay is effectively absorbed by the filter by reducing the amount of averaging performed. The correct delay selection vs. the output data rate minimizes any effect on resolution. This delay can only be absorbed when the requested delay is less than half the original settling time. For output data rates of greater than 10.39 kSPS, the delay time is added to the overall conversion time. This delay function is not valid when using the sinc3 filter or when rejecting 16.7 Hz, 50 Hz, 60 Hz, and 400 Hz interferers. BIAS VOLTAGE GENERATOR The AD4110-1 incorporates a bias voltage generator (VBIAS) that can be used to connect the AIN(−) pin to AGND. This feature is software selectable and is included for applications where the sensor output signal is floating. AGND VDD VSS AIN(–) 50µA 50µA 16269-034 F igure 34. VBIAS Equivalent Circuit Diagram The VBIAS generator acts as a 0 V voltage source with respect to AGND, see Figure 34 for the equivalent circuit diagram. It can source or sink up to a maximum of 50 µA from the sensor device connected to the AIN(+) and AIN(−) pins. If a sensor output connected to the input of the AD4110-1 is floating, the VBIAS function is used to bias the sensor output so that the sensor and AD4110-1 measuring system share the same ground. A typical example of a sensor that has a floating output is a thermocouple (see Figure 35). The VBIAS function is controlled by Bits[7:6] in the AFE_ CNTRL2 register (see Table 7 and Table 29). By default, the VBIAS function is disabled. Ta ble 10. Bit Descriptions for the ADC_MODE Register Addr. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x1 ADC_MODE [15:8] REF_EN Reserved DELAY [ 7:0] Reserved MODE CLK_SEL Reserved

Rev. 0 | Page 24 of 74 CURRENT MODE Current mode is selected by setting the IMODE bit to 1 in the AFE_CNTRL2 register (see Table 7 and Table 29). The analog inputs of the AD4110-1, AIN(+) and AIN(−), can interface directly to standard industrial analog sensors operating as current loops with 0 mA to +20 mA, ±4 mA to ±20 mA, or ±20 mA output. The current loop of the transmitter module terminals is connected directly to the differential analog inputs of the AD4110-1. The loop current flows through the internal switches, through the internal sense resistor, RSENSE, and then through the external sense resistor, REXT, as shown in Figure 37. The voltage drop across RSENSE, which is proportional to the input current, is then filtered by an analog RC filter. The AIN(+) and AIN(−) input pins are linked to the inputs of the internal PGA by a nominal series resistance of 1.6 kΩ. Using external capacitors, a first-order antialiasing filter can be implemented by connecting capacitors to the C(+) and C(−) pins. A 0.1 µF capacitor is recommended as the differential capacitor, and 0.01 µF capacitors to ground give a −3 dB cutoff frequency at approximately 500 Hz (see the Antialiasing Filter section). The resulting voltage is amplified by the on-chip PGA, and the analog output of the PGA is then routed to the buffered input of the ADC through a multiplexer. Set the gain of the PGA so that the PGA output voltage is within ±2.5 V to maximize the resolution of the 24-bit Σ-Δ ADC. When using the internal R SENSE resistor, the path from the EXRF pin to the AIN(−) pin must be connected. This connection can be implemented by shorting these pins externally or by populating the resistor REXT as a 0 Ω link. The current flowing through the RSENSE resistor is continuously monitored by the AD4110-1. If the current reaches the specified limit, the overcurrent flag (AIN_OC) is set in the AFE_DETAIL_ STATUS register (see Table 32). The AD4110-1 has built in self protection circuitry that limits the maximum current flowing through the device. VBIAS AIN(+) AIN(–) AGND C(–) C(+) EXRS EXRF VDD VSS VSS MUXPGA RSENSE 1kΩ 1kΩ 10Ω 10Ω 47nF AGND IN1(+) IN(–) AD4110-1 CURRENT MODE GAIN = 4 Σ-Δ ADC 47nF AGND 34 30 mA REXT ≥0Ω 16269-037 F igure 37. Current Input Mode, Internal Sense Resistor, Gain = 4

Rev. 0 | Page 26 of 74 VBIAS AIN(+) AIN(–) AGND C(–) C(+) EXRS EXRF VDD VSS VSS MUXPGA RSENSE 1kΩ 1kΩ 10Ω 10Ω 47nF AGND IN1(+) IN(–) AD4110-1 CURRENT MODE GAIN = 4 Σ-Δ ADC 47nF AGND 34 30 mA REXT 200Ω 16269-039 F igure 39. Current Input Mode, REXT Resistor

Rev. 0 | Page 28 of 74 Input Scaling for Voltage Mode Figure 41 shows the scaling of the voltage mode. The output of the front-end PGA is routed to the buffered input of the ADC through a multiplexer. To maximize the resolution of the 24-bit Σ-Δ ADC, the gain or attenuation of the PGA is selected so that the analog output voltage is within the range of ±2.5 V. Figure 41 shows the maximum input of ±12.5 V , which can be converted when the gain of 0.2 is selected. For specified performance as shown in Table 1, the input range is ±10 V and the functional range is ±12.5 V . If an overvoltage or undervoltage condition occurs on the AIN(+) or AIN(−) input, the corresponding error flag is set in the AFE_DETAIL_STATUS register. For more information, see the Overvoltage and Undervoltage Detection section. PGA AIN(–) AIN(+) Σ-Δ ADC 2.5V VREF 0xFFFFFF 0x000000 BIPOLAR CODING 0xFFFFFF 0x000000 UNIPOLAR CODING GAIN = 0.2 0x800000 VDD VSS AVDD5 AINP_OV AINN_OV AINP_UV AINN_UV 2.0V 2.0V 1FRONT-END SWITCHES, 1kΩ INTERNAL RESISTORS, AND EXTERNAL CAPACITORS NOT SHOWN ON AIN(+), AIN(–) INPUTS. 2IDEAL OUTPUT CODE FOR +10V AND –10V INPUT VOLTAGE IN BIPOLAR MODE. 3IDEAL OUTPUT CODE FOR +10V INPUT VOLTAGE IN UNIPOLAR MODE. AGND ±12.5V FUNCTIONAL RANGE ±10.0V SPECIFIED PERFORMANCE 0x1999992 0xCCCCCC3 16269-041 F igure 41. Voltage Input Mode Scaling

operation is used when connecting the device to RTD sensors. the PGA_RTD_CTRL register (see Table 11 and Table 30). Generating RTD Currents with an External Resistor section). to the iREFS and iREFF pins. connected in the same way as shown in Figure 43. amplifier offset error and the ratio error. where TC is typically specified in ppm/°C. Table 11. Bit Descriptions for the PGA_RTD_CTRL Register

1. STAR POINT CONNECTION FROM iREFF AND iREFS TO EXTERNAL PRECISION RESISTOR.
2. KEEP REFIN(–), THE EXTERNAL REFERENCE GROUND, AND THE EXTERNAL RESISTOR

DIFFERENCE IN POTENTIAL BETWEEN THE NODES.

1. NOT DRAWN TO SCALE; REFERENCE DECOUPLING NOT SHOWN.

Figure 43. Connecting an External Reference Resistor to Generate RTD Excitation Currents

Rev. 0 | Page 34 of 74 2-Wire RTD Figure 48 shows the connection diagram for a 2-wire sensor. Configure the AD4110-1 to operate in voltage mode by clearing the IMODE bit in the AFE_CNTRL2 register (see Table 7). The AD4110-1 provides a single precision current source on the high voltage channel for use with 2-wire RTD sensors. By default, the AD4110-1 is configured to operate in 4-wire RTD mode. When 2-wire RTD mode is required, set the RTD_3W4W bit in the PGA_RTD_CTRL register (see Table 11 and Table 30). In 2-wire mode, only the 100 µA excitation current can be used and this current is available on the AIN(+) pin. When using 2-wire mode, the compensation current must be disabled (see Table 30). When using a 2-wire RTD sensor, enable the VBIAS function (see the Bias Voltage Generator section). Enable the 100 µA pull- down current source on the AIN(−) input by setting the AINN_DN100 bit in the AFE_CNTRL2 register (see Table 7). The excitation current flows through the RL1 and RL2 lead resistances and through the sensor. In 2-wire mode, it is not possible to compensate for the lead resistance. Therefore, the voltage generated between AIN(+) and AIN(−) equals the sum of the voltage generated across the RTD and the voltage generated by the lead resistance. Alternative 3-Wire Configuration An alternative 3-wire configuration is possible using a link wire between the AIN(−) and AGND, and is usually mounted on the module screw terminals. With this configuration, 3-wire RTD mode operation is possible. However, the excitation current flows through the RL1 and RL2 lead resistances, so the voltage generated between AIN(+) and AIN(−) equals the sum of the voltage generated across the RTD and the voltage generated by the lead resistance. VBIAS AIN(+) RTDx AIN(–) AGND C(–) C(+) EXRS EXRF VDD IEXC VSS VSS MUXPGA RSENSE 1kΩ 1kΩ 10Ω 10Ω 47nF AGND IN1(+) IN(–) AD4110-1 VOLTAGE MODE GAIN = 0.2 Σ-Δ ADC RL1 RL2 RTD SENSOR GND 47nF AGND AGND REXT ≥0Ω ICOMP 100Ω OPTIONAL LINK WIRE 16269-048 F igure 48. 2-Wire RTD

Rev. 0 | Page 35 of 74 FIELD POWER SUPPLY MODE The AD4110-1 provides an option to supply power to a current output sensor connected between the AIN(+) and AIN(−) pins with up to 24 mA. When Bit 3, EN_FLD_PWR, in the AFE_CNTRL2 register is set to 1, the voltage at the VDD pin –1.5V is routed through internal circuitry to the AIN(+) pin. The voltage drop of 1.5V is a typical value based on the specified maximum output current of 24 mA. The sensor return current flows from the AIN(−) pin through internal circuitry to the VSS pin via a 2.5 V regulator, see Figure 49 below. The voltage seen at the AIN(−) pin is typically VSS + 3.6 V . It is also necessary to set the mode of operation to current mode by setting the IMODE bit to 1 in the AFE_CNTRL2 register. The internal self-protection circuitry of the AD4110-1 limits the supply current from the AIN(+) pin to typically 55 mA, and the return current into the AIN(−) pin to typically 40 mA. If the supply current limit is exceeded, the overcurrent flag (FLD_ PWR_OC) is set in the AFE_DETAIL_STATUS register. If the return current limit is exceeded, the overcurrent flag (AIN_OC) is set in the AFE_DETAIL_STATUS register (see Table 32). Using external capacitors on C(+) and C(−), combined with the nominal 1.6 kΩ series resistance, a first-order, low-pass anti- aliasing filter can be implemented at the PGA input. A 0.1 µF capacitor is recommended as the differential capacitor, and 0.01 µF capacitors to ground give a -3dB cutoff frequency at approximately 500 Hz (see the Antialiasing Filter section). To maximize the supply voltage to a current output field transmitter, select the internal current sense resistor. Apply a 0 Ω link in place of the R EXT resistor, as shown in Figure 49. Since the voltage at VDD is routed through internal circuitry to provide a voltage of VDD − 1.5 V at the AIN(+) pin and the AIN(−) is typically 3.6 V above VSS, both the overvoltage flag on AIN(+) and the undervoltage flag on AIN(−) can be set. This is expected behavior and these flags can be ignored in this case. Alternatively, these flags can be masked out using the AFE error disable register (see Table 31). Overvoltage Protection When field power supply mode is enabled, the power supply (VDD/VSS) must be limited to ± 15 V . This requirement is to prevent exceeding the absolute maximum rating for any high voltage pin to VSS, as shown in Table 3. VBIAS AIN(+) AIN(–) AGND C(–) C(+) EXRS EXRF VDD VSS VSS MUXPGA RSENSE 1kΩ 1kΩ 10Ω 10Ω 47nF AGND IN1(+) IN(–) AD4110-1 CURRENT MODE GAIN = 0.2 Σ-Δ ADC 47nF AGND 34 30 REXT ≥0Ω ±4mA TO ±20mA FIELD TRANSMITTER FIELD POWER SUPPLY CONTROL 2.5V REG 16269-049 F igure 49. Field Power Supply Mode, REXT = 0 Ω

Rev. 0 | Page 36 of 74 NO POWER SUPPLY MODE When the AD4110-1 has no power supply connected on the VDD and VSS pins, the high voltage analog input of the AD4110-1 defaults to its preprogrammed input mode, either voltage mode or current mode, (see the Default Mode of Operation on Power-Up section). Voltage Mode If voltage mode is configured as the default mode of operation, the high voltage inputs operate as high impedance inputs. Typically, in this mode, there is a current flowing between the AIN(+) and AIN(−) pins of ±0.5 mA, see Figure 23. Current Mode If current mode is configured as the default mode of operation, the loop is not broken and the ±4 mA to ±20 mA loop current continues to pass through the analog inputs. The AD4110-1 monitors the loop current, and its selfprotection circuitry limits the maximum current through the high voltage inputs to ±55 mA (typical). In this mode, the voltage drop across the AIN(+) and AIN(−) pins is typically 5V, see Figure 26. System Redundancy Because the ±4 to ±20 mA loop is not broken when the device has no power supply connected, a second system connected in the loop can continue to operate and provide system redundancy. An example connection diagram is shown in Figure 50.

Figure 50. No Power Supply Mode in Redundancy Configuration

calibration data is stored for the high voltage channel only. register (Address 0xD) stores the coefficient for current mode. AFE_CAL_DATA register (Address 0xC). compensate for any measured gain error. Table 13. Coefficient Examples correction coefficient is stored. reading the AFE_RSENSE_DATA register (Address 0xD). voltage mode correction coefficient for the required gain setting. in the context of a maximum PGA gain error requirement of ±1%. in a microcontroller- or microprocessor- based implementation. every data sample read from the ADC. maximum thin film resistor estimated at ±20%.

Rev. 0 | Page 39 of 74 AUTOCALIBRATION MODES After each conversion, the ADC conversion result is scaled using the channel ADC offset and gain registers before being written to the data register. In unipolar mode, 20x4000000x800000)( 20. 75 23 ×× VData REF IN I n bipolar mode, 0x8000000x4000000x800000)( 20.75 23 +× GainOffsetV V Data REF IN T he default value of the offset register is 0x800000 and means that there is no offset to be added or subtracted. The nominal value of the gain register is 0x555555 and means that the ADC gain error is zero. However, during factory calibration of the ADC, the default value is adjusted so that any ADC gain error is compensated for. The AD4110-1 provides two calibration modes within the ADC that can be used to eliminate the system offset and gain errors on a per setup basis (see Table 39):

• System offset (zero-scale) calibration.
• System gain (full-scale) calibration. To start a calibration, write the relevant value to the MODE bits in the ADC_MODE register, see Table 39. The DOUT/RDY pin and the RDY bit in the status register go high when the calibration initiates. When the calibration is complete, the contents of the corresponding offset or gain register are updated, the RDY bit in the status register is reset, the DOUT/RDY pin returns low and the AD4110-1 reverts to standby mode. Only one channel can be active during either calibration mode. System calibrations expect the system zero-scale (offset) and system full-scale (gain) voltages to be applied to the AIN(+) and AIN(−) pins before initiating the calibration mode. As a result, errors external to the ADC are removed. The calibration range of the ADC gain is from 0.4 × VREF to 1.05 × VREF. A zero-scale (offset) calibration, if required, must always be performed before a full-scale (gain) calibration. Set the system software to monitor the RDY bit in the status register or the DOUT/RDY pin to determine the end of a calibration via a polling sequence or an interrupt-driven routine. All calibrations require a time equal to the settling time of the selected filter and output data rate to be completed. Calibration can be performed at any output data rate. Using lower output data rates results in improved calibration accuracy and is then accurate for all higher output data rates. The AD4110-1 provides the application with access to the on-chip gain calibration registers, allowing the microprocessor to read the gain correction coefficients of the device and to write calibration coefficients. A read or write of the offset and gain registers can be performed at any time except during a selfcalibration. This calibration method is only valid for one PGA gain setting at a time. If the PGA gain is changed, this process must be repeated. Alternatively, the application software retrieves previously stored calibration data and reprograms the gain and offset registers directly. After a power cycle, these registers return to their default values.

Rev. 0 | Page 40 of 74 APPLICATION EXAMPLES Example 1 The following example demonstrates how to read the AFE gain calibration register data, calculate the gain correction coefficient, and then apply the gain correction coefficient to the ADC conversion result within the application software. This example uses the following settings:

• Voltage mode with PGA gain set to 0.2
• Input signal applied is 5.00 V
• ADC result = 5.05 V (this result is within ±1%)
• AFE_CAL_DATA register = 94 (for gain = 0.2) The calculations are PGA_GAINCOEFFICIENT = (94 − 28 + 214)/214 PGA_GAINCOEFFICIENT = 0.9901123047 Multiply ADC Result × PGA_GAINCOEFFICIENT New ADC Result = 5.000067 V This result is within ±0.03%. Example 2 The following example demonstrates how to use the AFE gain calibration register data, calculate the gain correction coefficient, and then reprogram the ADC gain register so that the gain correction coefficient is automatically applied to the ADC conversion result. With this method, it is necessary to combine the factory stored ADC gain correction coefficient with the PGA gain correction coefficient, and then reprogram the ADC gain register. This example uses the following settings:
• Voltage mode with PGA gain set to 0.2
• AFE_CAL_DATA Register = 94 (for gain = 0.2)
• PGA_GAIN COEFFICIENT = 0.9901123047
• ADC_GAINREGISTER = 0x5556B0HEX (5592752 (dec))
• ADC_GAINNOMINAL = 0x555555HEX (5592405 (dec)) The calculations are PGA_GAINACTUAL = PGA_GAINNOMINAL/PGA_GAINCOEFFICIENT = 0.2019972876 ADC_GAINACTUAL = ADC_GAINNOMINAL/ADC_GAINREGISTER = 0.9999379554 SYS_GAIN ACTUAL = PGA_GAINACTUAL × ADC_GAINACTUAL = 0.2019847548 ADC_GAIN MODIFY = SYS_GAINNOMINAL/SYS_GAINACTUAL = 0.9901737398 ADC_GAIN REGISTER = ADC_GAINNOMINAL × ADC_GAINMODIFY = 5592405 × 0.9901737398 = 5537453 Reprogram as ADC_GAINREGISTER = 0x547EAD

indicate that a fault condition is present. undervoltage detection range. The AD4110-1 operates from a power supply of ±12 V to ±20 V. the analog input voltage is within the specified range. Table 15. Bit Descriptions for the AFE_ERR_DISABLE Register

Rev. 0 | Page 44 of 74 OPEN WIRE DETECTION When the AD4110-1 is configured for the voltage mode of operation, open wire detection currents can be used to detect a broken wire in the connection from the voltage source to the AD4110-1 inputs. Two constant current generators are available on the AIN(+) and AIN(−) inputs. These nonprecision current sources can be programmed to source or sink 1 µA or 100 µA and are disabled by default. See Figure 55 for the configuration diagram. For programming options, see the AFE_CNTRL2 Register section. These currents can be used to verify that an external transducer remains connected before attempting to take measurements. After the open wire detection currents are turned on, the current flows in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. If a sensor wire is broken, either the overvoltage flag or the undervoltage flag is set. Because the open wire detection currents can produce an error voltage due to sensor lead resistance, use them only periodically to check for an open wire prior to a measurement. It can take some time for the open wire detection current to detect an open circuit condition because the currents must charge any external capacitance. The strength of the open wire detection current can be selected as either 1 µA or 100 µA, depending on the amount of external capacitance in the circuit vs. the response time required to diagnose an external open circuit. DIAGNOSTICS FOR RTD MEASUREMENTS AND RTD FLAGS The RTD excitation and compensation currents have an output compliance of VDD − 5 V . Therefore, for correct operation, the voltage generated at the RTD pin or at the AIN(+) and AIN(−) pins must be less than VDD − 5 V. Out of compliance flags are available in the AFE_DETAIL_STATUS register (see Table 32). The AD4110-1 can monitor the voltages on the RTD, AIN(+), and AIN(−) pins. The voltage on the RTD or AIN(+) pin is monitored when the excitation current is active. When the output compliance is exceeded, the I_EXC bit in the AFE_DETAIL_STATUS register is set to 1. For example, this bit is set to 1 if a wire is broken, preventing the excitation current from flowing to ground. Similarly, the voltage on the AIN(−) pin is monitored when the compensation current is active. When the output compliance is exceeded, the I_COM bit in the AFE_DETAIL_STATUS register is set to 1. For example, this bit is set to 1 if a wire is broken, preventing the compensation current from flowing to ground. Note that in 4-wire RTD mode, no current flows from the AIN(+) and AIN(−) pins. Therefore, the open wire detection currents described in the Open Wire Detection section must also be used. In 4-wire RTD mode, only the excitation current is used. The out-of-compliance flag is set only when the RTD pin wire or the GND wire is broken (see Figure 46). PGA AIN(–) 31 AIN(+) 34 Σ-Δ ADC 2.5V VREFAVDD5 VSS VDD VDD VSS AINP_UP AINP_DN AINN_DN AINN_UP OPEN WIRE DETECTION VOLTAGE SOURCE MULTIPLEXER 16269-055 F igure 55. Voltage Input Mode, Open Wire Detection Options

Table 16. Sinc5 + Sinc1 Filter Response—Peak-to-Peak Noise and Resolution (Data Based on 1000 Samples, 500 Samples for Output Data

Table 18. Sinc3 Filter Response—Peak-to-Peak Noise and Resolution (Data Based on 1000 Samples, 500 Samples for ODR < 50 SPS) Table 19. Sinc3 Filter Response—RMS Noise and Resolution (Data Based on 1000 Samples, 500 Samples for ODR < 50 SPS)

be selected when using the enhanced filters. plots of the responses from the enhanced filters.

50 Hz/60 Hz

1 The switching rate = 1/tSETTLE. Table 21. Enhanced Filter Response—RMS Noise and Resolution (Data Based on 500 Samples) 1 The switching rate = 1/tSETTLE.

interfacing to the AD4110-1. end of the chip select frame. about the CRC, see the CRC Checksum section. after a device reset before reading or writing to registers. subsequent read or write of the selected register. write to either the analog front end (AFE) or the ADC registers. by a 16-bit/24-bit data write, depending on the register selected. Figure 67. AFE/ADC Bit Used to Address the Two AD4110-1 Register Maps Table 24. Communications Register (Write Only Register) 7 AFE/ADC The AFE/ADC bit routes the communication write to either the AFE register map or the ADC register map. 0 ADC register map selected. 1 AFE register map selected. 6 R/W Read/write enable. This bit enables a read or write of the selected register. 0 Write to selected register. serial bus are decoded to the correct device when these bits match the state of the ADR1 and ADR0 pins. [3:0] R[3:0] Register address bits. These bits map to the register addresses on both the AFE and ADC register maps.

to access in the AFE or ADC register map. ADC conversion is ready to be read (see Figure 70). setting the CRC_EN bits in both the AFE and ADC register maps. data command received on DIN and the transmitted register data. impedance state at the end of the chip select frame. Figure 69. Serial Interface Read Sequence for All Registers Except the ADC_DATA Register

1 LSB LSB

0 DUMMY DATA

Figure 70. Serial Interface Read Sequence for the ADC_DATA Register (Conversion Result)

connection to IOVDD or DGND is also possible. bits cannot be changed during a CS frame. Figure 71. SPI Wiring Connections for Multiple Devices Figure 72. Serial Interface Read Sequence for the ADC_DATA Register with Multiple Devices on the SPI bus

Rev. 0 | Page 56 of 74 Polynomial CRC Calculation of a 24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) An example of generating the 8-bit checksum using the polynomial based checksum is as follows: 6 5 4 3 2 1 Initial value: 0110 0101 0100 0011 0010 0001 Left shifted eight bits: 0110 0101 0100 0011 0010 0001 0000 0000 Polynomial: 100 0001 11 XOR 1 10 0100 1000 0011 0010 0001 0000 0000 10 0000 111 XOR 2 100 0110 0011 0010 0001 0000 0000 100 0001 11 XOR 3 111 1111 0010 0001 0000 0000 100 0001 11 XOR 4 11 1110 1110 0001 0000 0000 10 0000 111 XOR 5 1 1110 0000 0001 0000 0000 1 0000 0111 XOR 6 1110 0111 0001 0000 0000 1000 0011 1 XOR 7 110 0100 1001 0000 0000 100 0001 11 XOR 8 10 0101 0101 0000 0000 10 0000 111 XOR 9 101 1011 0000 0000 100 0001 11 XOR 10 1 1010 1100 0000 1 0000 0111 XOR 11 1010 1011 0000 1000 0011 1 XOR 12 10 1000 1000 10 0000 111 CRC Checksum (0x86) 1000 0110

Rev. 0 | Page 57 of 74 XOR Calculation The checksum, which is eight bits wide, is generated by splitting the data into bytes and then performing an XOR of the bytes. XOR CRC calculation of a 24-bit word: 0x654321 (eight command bits and 16-bit data) An example of generating the 8-bit checksum using the polynomial-based checksum is as follows: Divide into three bytes: 0x65, 0x43, and 0x21 0x65 0110 0101 0x43 0100 0011 XOR Result 0010 0110 0x21 0010 0001 CRC Checksum (0x07) 0000 0111

Throughout this section, RW means read and write, R means read only, and W means write only. Table 25. AFE Register Map

AFE_ERR_DISABLE register (Address 0x6). Table 26. Bit Descriptions for the AFE_TOP_STATUS Register 1 Indicates one or more errors detected on the high voltage channel. 1 Indicates an error during SPI communication.

1 Indicates that the chip temperature exceeded the thermal shutdown threshold,

SPI interface remains functional.

1 Indicates that the chip temperature exceeded the overtemperature detection

appropriate actions to lower the device power dissipation. 1 Indicates an error condition that is not masked by the AFE_ERR_DISABLE register. ERR output pin is driven low to indicate an error.

Table 27. Bit Descriptions for the AFE_CNTRL1 Register 10 8-bit CRC enabled on reads and writes. ensure that the AFE and ADC are synchronized with the same clock. Table 28. Bit Descriptions for the AFE_CLK_CTRL Register 10 AFE clocked by ADC (required setting).

the external sense resistor for current input mode and to select the voltage mode or current mode of operation. Table 29. Bit Descriptions for the AFE_CNTRL2 Register 0 Field power supply is off. 0 Internal sense resistor selected. 1 External sense resistor selected. programmed by the application.

the excitation and compensation currents. This register is also used to set the channel gain. Table 30. Bit Descriptions for the PGA_RTD_CTRL Register 0 4-wire (current via RTD pin). 1 2-wire or 3-wire (currents via AIN(+) and AIN(−) pins). 0 Internal RTD resistor selected. 1 External RTD resistor selected.

ERR pin and by the AFE_ERROR bit to customize the system diagnostics for the requirements of the application. Table 31. Bit Descriptions for the AFE_ERR_DISABLE Register

error condition is captured by the error logic and indicated by the appropriate error bit until this register is read. Table 32. Bit Descriptions for the AFE_DETAIL_STATUS Register nine bits wide and uses offset binary coding. Bit 9 is a parity bit that is set so that the overall number of 1s in the register is an odd number. The gain error at each gain is measured during device production test, and the corresponding correction coefficient is stored in this register. and then reading this register. Table 33. Bit Descriptions for the AFE_CAL_DATA Register

15 bits wide and uses offset binary coding. Bit 15 is a parity bit that is set so that the overall number of 1s in the register is an odd number. and then reading this register. Table 34. Bit Descriptions for the AFE_RSENSE_DATA Register can be changed, as described in the Default Mode of Operation on Power-Up section. Table 35. Bit Descriptions for the NO_PWR_DEFAULT_SEL Register AFE_CNTRL2 register at Address 0x4). of remaining changes to the default mode of operation is provided by the count bits (Bits[7:0]). Table 36. Bit Descriptions for the NO_PWR_DEFAULT_STATUS Register

1 This error flag is set if there was an error in the communication while reading

repeated to ensure that the read is accurate. operation of the AD4110-1 can be changed up to 100 times.

Table 37. ADC Register Map

is selected, the contents of the ADC_STATUS register are read automatically with each ADC conversion result. Table 38. Bit Descriptions for the ADC_STATUS Register by a read of the data register. 0 New ADC data result is available. 1 Waiting for new data result. 6 ADC_ERR This bit by default indicates if an ADC overrange or underrange has occurred. if configured as an input (see the Error Pin section). 1 An error occurred during communication. active for the ADC conversion whose result is currently in the data register. This value may differ from the channel that is currently being converted. 00 Channel 0 (high voltage channel): AIN(+) − AIN(−). 01 Channel 1 (low voltage channel): AIN1(LV ) − AIN2(LV). 10 Channel 2 (low voltage channel): AIN1(LV ) − AINCOM(LV). 11 Channel 3 (low voltage channel): AIN2(LV) − AINCOM(LV). the ADC sampling. A write to this register resets the digital filter and the RDY bit in the ADC_STATUS register and starts a new conversion. ensure that the AFE and ADC are synchronized with the same clock. Table 39. Bit Descriptions for the ADC_MODE Register 1 Enabled, buffered output to REFOUT pin.

Rev. 0 | Page 68 of 74 Bits Bit Name Settings Description Reset Access [10:8] Delay C onversion delay. If the application switches through a sequence of channels for conversion by the ADC, a settling time is associated with each switched analog input. These bits allow the user to configure a delay that is added after a channel switch. This delay allows settling of the external circuitry before the ADC starts processing its input. The delay allows the data rate of the ADC to remain at the required update rate with only a minor impact on the resolution of the conversion result. The correct delay selection vs. the output data rate minimizes any effect on resolution. This function is not valid when rejecting 50 Hz/60 Hz interferers. 0x0 RW 000 Off (no delay). 001 1 cycle (1 cycle = 8 µs). 010 4 cycles. 011 10 cycles. 100 25 cycles. 101 50 cycles. 110 125 cycles. 111 250 cycles. 7 Reserved R eserved. 0x0 R [6:4] Mode ADC conversion mode. These bits control the operating mode of the ADC. 0x0 RW 000 Continuous conversion. The ADC continually converts the selected input channel at the selected conversion rate, or sequences around channels if more than one channel is enabled. 001 Single conversion. This performs a single conversion of the selected channel or channels. The ADC returns to Standby mode on completion of the sequence. 010 Standby mode. 011 Power-down mode. All ADC blocks are powered down and registers lose their contents. The ADC can only enter power-down mode if the previous mode was set to standby mode. To exit power-down mode it is necessary to reset the SPI interface, see the Resetting the AD4110-1 section.

100 Reserved

101 Reserved

110 System offset (zero-scale) calibration. This mode performs an offset calibration using the applied analog input as the zero scale point. The calibration result is stored in the appropriate offset register for the channel and the ADC then enters standby mode. This calibration allows any offset error present in the full channel to be removed. Select only one channel at a time for an offset calibration. See the Autocalibration Modes section for a detailed description. Note that this calibration method is valid for one PGA gain setting and must be repeated if the PGA gain is changed. 111 System gain (full-scale) calibration. This mode performs a gain calibration using the applied analog input as the full-scale point. The calibration result is stored in the appropriate gain register for the channel and the ADC then enters standby mode. This calibration allows any gain error present in the full channel to be removed. Select only one channe at a time for a gain calibration. See the Autocalibration Modes section for a detailed description. Note that this calibration method is valid for one PGA gain setting and must be repeated if the PGA gain is changed. [3:2] CLK_SEL C lock source select. These bits select the ADC clock source. 0x0 RW 00 Internal clock. 01 Internal clock connected to CLKIO pin (required for AFE). 10 External clock from CLKIO pin. 11 Reserved. [1:0] Reserved R eserved. 0x0 R

instead of the default 24 bits. Table 40. Bit Descriptions for the ADC_INTERFACE Register 01 8-bit XOR checksum on reads, 8-bit CRC on writes. 10 8-bit CRC on reads and writes. 0 Conversion result is 24 bits long. 1 Conversion result is 16 bits long. negative REFIN_BUFF and AIN_BUFF buffers as a pair. Table 41. Bit Descriptions for the ADC_CONFIG Register 0 Unipolar coded output (straight binary). 1 Bipolar coded output (offset binary). 01 Enable negative input buffer only. 10 Enable positive input buffer only.

01 Enable negative input buffer only. 10 Enable positive input buffer only. REF_EN bit (Bit 15) in the ADC_MODE register (Address 0x1) must also be set. 00 External voltage reference connected to REFIN(+)/REFIN(−) pins. 10 Internal 2.5 V reference. automatically when Bits[3:0] = 00. Table 42. Bit Descriptions for the Data Register the ADC_INTERFACE register, this register is rounded to 16 bits.

to be selected for the high voltage channel and the three low voltage channels. These filter registers share the same memory address. the ADC_CONFIG register (see Table 41). Table 43. Bit Descriptions for the Filter Register of 50 Hz and 60 Hz simultaneously while also reducing the settling time. 0 Disable enhanced 50 Hz/60 Hz filter. 1 Enable enhanced 50 Hz/60 Hz filter. 011 ODR = 25 SPS, settling time = 40 ms. 101 ODR = 20 SPS, settling time = 50 ms. 110 ODR = 16.67 SPS, settling time = 60 ms. 00 Sinc5 + sinc1 (fast settling filter).

The ADC_GPIO_CONFIG register controls the general-purpose I/O pins of the ADC: SYNC and ERR. Table 44. Bit Descriptions for the ADC_GPIO_CONFIG Register used to combine the AFE and ADC errors into the ADC_ERR bit. 10 Output (open-drain, active low). The read only ID register returns the 16-bit device ID. For the AD4110-1, this value is 0x98DX. Table 45. Bit Descriptions for the ID Register 0x98DX AD4110-1. (where X is the ADC silicon revision). The ADC_OFFSET0 register configures the offset for Channel 0 (high voltage channel, AIN(+) − AIN(−) inputs). Table 46. Bit Descriptions for the ADC_OFFSET0 Register The ADC_OFFSET1 register configures the offset for Channel 1 (low voltage channel, AIN1(LV) − AIN2(LV) inputs). Table 47. Bit Descriptions for the ADC_OFFSET1 Register

The ADC_OFFSET2 register configures the offset for Channel 2 (low voltage channel, AIN1(LV) − AINCOM(LV) inputs). Table 48. Bit Descriptions for the ADC_OFFSET2 Register The ADC_OFFSET3 register configures the offset for Channel 3 (low voltage channel, AIN2(LV) − AINCOM(LV) inputs). Table 49. Bit Descriptions for the ADC_OFFSET3 Register The ADC_GAIN0 register configures the gain for Channel 0 (high voltage channel, AIN(+) − AIN(−) input). Table 50. Bit Descriptions for the ADC_GAIN0 Register The ADC_GAIN1 register configures the gain for Channel 1 (low voltage channel, AIN1(LV) − AIN2(LV) input). Table 51. Bit Descriptions for the ADC_GAIN1 Register The ADC_GAIN2 register configures the gain for Channel 2 (low voltage channel, AIN1(LV) − AINCOM(LV) input). Table 52. Bit Descriptions for the ADC_GAIN2 Register The ADC_GAIN3 register configures the gain for Channel 3 (low voltage channel, AIN2(LV) − AINCOM(LV) input). Table 53. Bit Descriptions for the ADC_GAIN3 Register

Rev. 0 | Page 74 of 74 OUTLINE DIMENSIONS 03-03-2017-B 0.50 BSC BOTTOM VIEWTOP VIEW PIN 1 INDICATOR

0.05 MAX

0.02 NOM

0.20 REF

0.08 0.30 0.25 0.18 6.10 6.00 SQ 5.90 1.00 0.95 0.85 0.45 0.40 0.35

0.25 MIN

4.70 4.60 SQ 4.50 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5 11 10 END VIEW EXPOSED PAD PKG-003653/5050 SEATING PLANE PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) DETAIL A (JEDEC 95) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Fi gure 75. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm × 6 mm Body and 0.95 mm Package Height (CP-40-15) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD4110-1BCPZ −40°C to +105°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-15 AD4110-1BCPZ-RL −40°C to +105°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-15 AD4110-1BCPZ-RL7 −40°C to +105°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-15 1 Z = RoHS Compliant Part. ©2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16269-0-3/19(0)