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16-Bit, 2 MSPS/1 MSPS, Precision, Differential SAR ADCs Data Sheet AD4001/AD4005 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Throughput: 2 MSPS/1 MSPS options INL: ±0.4 LSB maximum Guaranteed 16-bit no missing codes Low power 9.5 mW at 2 MSPS, 4.9 mW at 1 MSPS (VDD only) 80 μW at 10 kSPS, 16 mW at 2 MSPS (total) SNR: 96.2 dB typical at 1 kHz, VREF = 5 V; 95.5 dB typical at 100 kHz THD: −123 dB typical at 1 kHz, VREF = 5 V; −99 dB typical at 100 kHz Ease of use features reduce system power and complexity Input overvoltage clamp circuit Reduced nonlinear input charge kickback High-Z mode Long acquisition phase Input span compression Fast conversion time allows low SPI clock rates SPI-programmable modes, read/write capability, status word Differential analog input range: ±VREF 0 V to VREF with VREF from 2.4 V to 5.1 V Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface SAR architecture: no latency/pipeline delay, valid first conversion First accurate conversion Guaranteed operation: −40°C to +125°C SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface Ability to daisy-chain multiple ADCs and busy indicator 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP
APPLICATIONS
Precision data acquisition systems GENERAL DESCRIPTION The AD4001/AD4005 are low noise, low power, high speed, 16-bit, precision successive approximation register (SAR) analog-to-digital converters (ADCs). The AD4001 offers a 2 MSPS throughput, and the AD4005 offers a 1 MSPS throughput. They incorporate ease of use features that reduce signal chain power consumption, reduce signal chain complexity, and enable higher channel density. The high-Z mode, coupled with a long acquisition phase, eliminates the need for a dedicated high power, high speed ADC driver, thus broadening the range of low power precision amplifiers that can drive these ADCs directly, while still achieving optimum performance. The input span compression feature enables the ADC driver amplifier and the ADC to operate off common supply rails without the need for a negative supply while preserving the full ADC code range. The low serial peripheral interface (SPI) clock rate requirement reduces the digital input/output power consumption, broadens processor options, and simplifies the task of sending data across digital isolation. Operating from a 1.8 V supply, the AD4001/AD4005 have a ±VREF fully differential input range with VREF ranging from 2.4 V to 5.1 V. The AD4001 consumes only 16 mW at 2 MSPS with a minimum SCK rate of 70 MHz in turbo mode, and the AD4005 consumes only 8 mW at 1 MSPS. The AD4001/AD4005 both achieve ±0.4 LSB integral nonlinearity error (INL) maximum, guaranteed no missing codes at 16 bits with 96.2 dB typical signal-to-noise ratio (SNR) for 1 kHz inputs. The reference voltage is applied externally and can be set independently of the supply voltage. The SPI-compatible, versatile serial interface features seven different modes including the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus, and provides an optional busy indicator. The AD4001/AD4005 are compatible with 1.8 V , 2.5 V , 3 V , and 5 V logic, using the separate VIO supply. The AD4001/AD4005 are available in a 10-lead MSOP or LFCSP with operation specified from −40°C to +125°C. The devices are pin compatible with the 18-bit, 2 MSPS AD4003 (see Table 8). FUNCTIONAL BLOCK DIAGRAM GND IN+ IN– SDI SCK SDO CNV AD4001/ AD4005 16-BIT SAR ADC SERIAL INTERFACE VIO REF VDD VREF VREF VREF/2 VREF/2 HIGH-Z MODE CLAMP SPAN COMPRESSION TURBO MODE STATUS BITS 2.4V TO 5.1V 1.8V10µF 1.8V TO 5V 3-WIRE OR 4-WIRE SPI INTERFACE (DAISY CHAIN, CS) 15368-001 Figure 1.
Rev. B | Page 3 of 37 Changes to Layout Guidelines Section and Evaluating the 1/2017—Revision 0: Initial Version
Rev. B | Page 4 of 37 SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V , VREF = 5 V , all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4001 and fS = 1 MSPS for the AD4005, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range VIN+ − VIN− −VREF +VREF V Span compression enabled −VREF × 0.8 +VREF × 0.8 V Operating Input Voltage VIN+, VIN− to GND −0.1 VREF + 0.1 V Span compression enabled 0.1 × VREF 0.9 × VREF V Common-Mode Input Range VREF/2 − 0.125 VREF/2 VREF/2 + 0.125 V Common-Mode Rejection Ratio (CMRR) fIN = 500 kHz 68 dB Analog Input Current Acquisition phase, T = 25°C 0.3 nA High-Z mode enabled, converting dc input at 2 MSPS 1 µA THROUGHPUT Complete Cycle AD4001 500 ns AD4005 1000 ns Conversion Time 290 320 ns Acquisition Phase1 AD4001 290 ns AD4005 790 ns Throughput Rate2 AD4001 0 2 MSPS AD4005 0 1 MSPS Transient Response3 250 ns DC ACCURACY No Missing Codes 16 Bits Integral Nonlinearity Error (INL) −0.4 ±0.2 +0.4 LSB Differential Nonlinearity Error (DNL) −0.5 ±0.2 +0.5 LSB Transition Noise 0.35 LSB Zero Error −1.5 ±0.1 +1.5 LSB Zero Error Drift4 −0.28 +0.28 ppm/°C Gain Error −16.5 ±0.4 +16.5 LSB Gain Error Drift4 −0.23 +0.23 ppm/°C Power Supply Sensitivity VDD = 1.8 V ± 5% 0.25 LSB 1/f Noise5 Bandwidth = 0.1 Hz to 10 Hz 6 µV p-p AC ACCURACY Dynamic Range 96.3 dB Total RMS Noise 54 µV rms fIN = 1 kHz, −0.5 dBFS, VREF = 5 V Signal-to-Noise Ratio (SNR) 95.6 96.2 dB Spurious-Free Dynamic Range (SFDR) 122 dB Total Harmonic Distortion (THD) −123 dB Signal-to-Noise-and-Distortion Ratio (SINAD) 95.5 96 dB Oversampled Dynamic Range Oversampling ratio (OSR) = 256, VREF = 5 V 120 dB
Rev. B | Page 5 of 37 Parameter Test Conditions/Comments Min Typ Max Unit fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V SNR 92.1 93.2 dB SFDR 118 dB THD −117 dB SINAD 92 93 dB fIN = 100 kHz, −0.5 dBFS, VREF = 5 V SNR 95.5 dB THD −99 dB SINAD 93.8 dB fIN = 400 kHz, −0.5 dBFS, VREF = 5 V SNR 91 dB THD −92 dB SINAD 89 dB −3 dB Input Bandwidth 10 MHz Aperture Delay 1 ns Aperture Jitter 1 ps rms REFERENCE Voltage Range, VREF 2.4 5.1 V Current VREF = 5 V AD4001 2 MSPS 1.1 mA AD4005 1 MSPS 0.5 mA INPUT OVERVOLTAGE CLAMP IN+/IN− Current, IIN+/IIN− VREF = 5 V 50 mA VREF = 2.5 V 50 mA VIN+/VIN− at Maximum IIN+/IIN− VREF = 5 V 5.4 V VREF = 2.5 V 3.1 V VIN+/VIN− Clamp On/Off Threshold VREF = 5 V 5.25 5.4 V VREF = 2.5 V 2.68 2.8 V Deactivation Time 360 ns REF Current at Maximum IIN+/IIN− VIN+/VIN− > VREF 100 µA DIGITAL INPUTS Logic Levels Input Low Voltage, VIL VIO > 2.7 V −0.3 +0.3 × VIO V VIO ≤ 2.7 V −0.3 +0.2 × VIO V Input High Voltage, VIH VIO > 2.7 V 0.7 × VIO VIO + 0.3 V VIO ≤ 2.7 V 0.8 × VIO VIO + 0.3 V Input Low Current, IIL −1 +1 µA Input High Current, IIH −1 +1 µA Input Pin Capacitance 6 pF DIGITAL OUTPUTS Data Format Serial 16 bits, twos complement Pipeline Delay Conversion results available immediately after completed conversion Output Low Voltage, VOL ISINK = 500 µA 0.4 V Output High Voltage, VOH ISOURCE = −500 µA VIO − 0.3 V POWER SUPPLIES VDD 1.71 1.8 1.89 V VIO 1.71 5.5 V Standby Current VDD = 1.8 V, VIO = 1.8 V, T = 25°C 1.6 µA
Rev. B | Page 6 of 37 Parameter Test Conditions/Comments Min Typ Max Unit Power Dissipation VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V 10 kSPS, high-Z mode disabled 80 µW 1 MSPS, high-Z mode disabled 8 9.3 mW 2 MSPS, high-Z mode disabled 16 18.5 mW 1 MSPS, high-Z mode enabled 10 12.3 mW 2 MSPS, high-Z mode enabled 20 24.5 mW VDD Only 1 MSPS, high-Z mode disabled 4.9 mW 2 MSPS, high-Z mode disabled 9.5 mW REF Only 1 MSPS, high-Z mode disabled 2.8 mW 2 MSPS, high-Z mode disabled 5.5 mW VIO Only 1 MSPS, high-Z mode disabled 0.4 mW 2 MSPS, high-Z mode disabled 1.0 mW Energy per Conversion 8 nJ/sample TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +125 °C 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4001 and 1 MSPS for the AD4005. 2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, but not production tested. 5 See the 1/f noise plot in Figure 23.
noted. See Figure 2 for the timing voltage levels. Table 2. Digital Interface Timing AD4001 and 1 MSPS for the AD4005. 2 For turbo mode, tCNVH must match the tQUIET1 minimum. throughput for different modes of operation. 4 A 50% duty cycle is assumed for SCK. 5 See Figure 22 for SINAD vs. tQUIET2. Figure 2. Voltage Levels for Timing
Table 3. Register Read/Write Timing 1 For turbo mode, tCNVH must match the tQUIET1 minimum. Table 4. Achievable Throughput for Different Modes of Operation
overvoltage condition for an indefinite amount of time. 1 See the Analog Inputs section for an explanation of IN+ and IN−. PCB thermal design is required. Table 6. Thermal Resistance
1 Test Condition 1: thermal impedance simulated values are based upon use
of 2S2P JEDEC PCB. See the Ordering Guide. measured in a one cubic foot sealed enclosure. 3 θJC is the junction-to-case thermal resistance.
Figure 3. 10-Lead MSOP Pin Configuration
10 VIO
9 SDI
8 SCK
7 SDO
6 CNV
- CONNECT THE EXPOSED PAD TO GND.
MEET THE SPECIFIED PERFORMANCE. Figure 4. 10-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions decoupled closely to the GND pin with a 10 µF, X7R ceramic capacitor. 3 IN+ AI Differential Positive Analog Input. See the Differential Input Considerations section. 4 IN− AI Differential Negative Analog Input. See the Differential Input Considerations section. 5 GND P Power Supply Ground. enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. level on SDI is output on SDO with a delay of 16 SCK cycles. on SDI on the rising edge of SCK. 1 AI is analog input, P is power, DI is digital input, and DO is digital output.
Rev. B | Page 16 of 37 TERMINOLOGY Integral Nonlinearity Error (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 31). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal midscale voltage, that is, 0 V , from the actual voltage producing the midscale output code, that is, 0 LSB. Gain Error ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: ENOB = (SINAD dB − 1.76)/6.02 ENOB is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of IN+ and IN− of frequency, f. CMRR (dB) = 10log(P ADC_IN/PADC_OUT) where: PADC_IN is the common-mode power at the frequency, f, applied to the IN+ and IN− inputs. PADC_OUT is the power at the frequency, f, in the ADC output. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency, f. PSRR (dB) = 10 log(PVDD_IN/PADC_OUT) where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output.
Figure 30. ADC Simplified Schematic precise, 16-bit ADCs based on a SAR architecture. which the ADC does not need to be constantly converting. making them ideal for multiplexed applications. use features that result in a lower system power and footprint. protects the device from overvoltage damage on the analog inputs. charge kickback seen from a typical switched capacitor SAR input. load for the amplifier, improving stability and power dissipation. multiplexing, disable high-Z mode. amplifier to access the full range of the ADC. running at their maximum throughput rates of 2 MSPS/1 MSPS. achieved only with turbo mode enabled. the 14-/16-/18-/20-bit precision SAR ADCs listed in Table 8. Table 8. MSOP and LFCSP 14-/16-/18-/20-Bit Precision SAR
201 AD40202
181 AD7989-12 AD76912 AD76902,
161 AD7684 AD76872 AD76882,
163 AD7680,
143 AD7940 AD79422 AD79462 Not applicable
Table 14. The overvoltage clamp flag (OV) is a read only sticky bit, condition when it is set to 0. Table 12. Register Bits Table 13. Command Register mode is enabled, SDO goes low on the rising edge of CNV . Register reads are not allowed in daisy-chain mode. A register write requires three signal lines: SCK, CNV , and SDI. on SDO. However, the register write occurs regardless. this scenario, the user may need to set the final SDI state. in register read, write, and daisy-chain mode. Table 14. Register Map Figure 48. Register Read Timing Diagram (X Means Don’t Care)
Table 15. The status bits must be enabled in the register setting. updates on a per conversion basis. including status bits, is shown in Figure 51. Table 15. Status Bits (Default Conditions) Figure 51. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram, Including Status Bits (SDI High)
0.50 BSC
1.10 MAX
Figure 68. 10-Lead Mini Small Outline Package [MSOP]
0.20 REF
0.05 MAX
0.02 NOM
0.20 MIN
Figure 69. 10-Lead Lead Frame Chip Scale Package [LFCSP] 2 The EVAL-AD4001FMCZ can also be used to evaluate the AD4005 by setting the throughput to 1 MSPS in its software (see UG-1042). registered trademarks are the property of their respective owners.