AD4002/AD4006/AD4010 (Rev. A)
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- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 39
Technical content
18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Data Sheet AD4002/AD4006/AD4010 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. O Tel: 781.329.4700 ©2018–2021 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential analog input range
0 V to V
REF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±3.2 LSB maximum Guaranteed 18-bit, no missing codes SNR: 95 dB at f IN = 1 kHz at VREF = 5 V THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17) Oversampled dynamic range 98 dB for OSR = 2 125 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C
APPLICATIONS
Precision data acquisition systems Instrumentation and control systems FUNCTIONAL BLOCK DIAGRAM GND IN+ IN– SDI SCK SDO CNV AD4002/ AD4006/ AD4010 18-BIT SAR ADC SERIAL INTERFACE VIO REF VDD VREF VREF/2 HIGH-Z MODE CLAMP SPAN COMPRESSION TURBO MODE STATUS BITS 2.4V TO 5.1V 1.8V10µF 1.8V TO 5V 3-WIRE OR 4-WIRE SPI INTERFACE (DAISY CHAIN, CS) 16233-001 Figure 1. GENERAL DESCRIPTION The AD4002/AD4006/AD4010 are high accuracy, high speed, low power, 18-bit, Easy Drive, precision successive approximation register (SAR) analog-to-digital converters (ADCs) that operate from a single power supply, VDD. The reference voltage, VREF, is applied externally and can be set independent of the supply voltage. The AD4002/AD4006/AD4010 power scales linearly with throughput. Easy Drive features reduce both signal chain complexity and power consumption while enabling higher channel density. The reduced input current, particularly in high-Z mode, coupled with a long signal acquisition phase, eliminates the need for a dedicated ADC driver. Easy Drive broadens the range of companion circuitry that is capable of driving these ADCs (see Figure 2). Input span compression eliminates the need to provide a negative supply to the ADC driver amplifier while preserving access to the full ADC code range. The input overvoltage clamp protects the ADC inputs against overvoltage events, minimizing disturbances on the reference pin and eliminating the need for external protection diodes. Fast device throughput up to 2 MSPS allows users to accurately capture high frequency signals and to implement oversampling techniques to alleviate the challenges associated with antialias filter designs. Decreased serial peripheral interface (SPI) clock rate requirements reduce digital input/output power consumption, broadens digital host options, and simplifies the task of sending data across digital isolation. The SPI-compatible serial user interface is compatible with 1.8 V , 2.5 V , 3 V , and 5 V logic by using the separate VIO logic supply. –25 –20 –15 –10 ANALOG INPUT CURRENT (μA) INPUT DIFFERENTIAL VOLTAGE (V) HIGH-Z DISABLED, 2MSPS HIGH-Z ENABLED, 2MSPS 16233-402 Fig ure 2. Input Current vs. Input Differential Voltage
Data Sheet AD4002/AD4006/AD4010 Rev. A | Page 3 of 39 Changes to Layout Guidelines Section and Evaluating the 1/2018—Revision 0: Initial Version
AD4002/AD4006/AD4010 Data Sheet Rev. A | Page 4 of 39 SPECIFICATIONS VDD = 1.71 V to 1.89 V , VIO = 1.71 V to 5.5 V , REF = VREF = 5 V , all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4002, fS = 1 MSPS for the AD4006, and fS = 500 kSPS for the AD4010, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 18 Bits ANALOG INPUT Voltage Range IN+ Voltage (V IN+) − IN− Voltage (VIN−) 0 V REF V Operating Input Voltage V IN+ to GND −0.1 V REF + 0.1 V V IN− to GND −0.1 +0.1 V Span compression enabled 0.1 × V REF 0.9 × V REF V Analog Input Current Acquisition phase, T A = 25°C 0.3 nA High-Z mode enabled, converting dc input at 2 MSPS 1 μA THROUGHPUT Complete Cycle AD4002 500 ns AD4006 1000 ns AD4010 2000 ns Conversion Time 270 290 320 ns Acquisition Phase1 AD4002 290 ns AD4006 790 ns AD4010 1790 ns Throughput Rate2 AD4002 0 2 MSPS AD4006 0 1 MSPS AD4010 0 500 kSPS Transient Response3 290 ns DC ACCURACY No Missing Codes 18 Bits Integral Nonlinearity Error (INL) −3.2 ±0.8 +3.2 LSB Differential Nonlinearity Error (DNL) −0.8 ±0.5 +0.8 LSB Transition Noise 1.6 LSB Zero Error −18 +18 LSB Zero Error Drift4 −2.2 +2.2 ppm/°C Gain Error −45 ±10 +45 LSB Gain Error Drift4 −2.6 +2.6 ppm/°C Power Supply Sensitivity VDD = 1.8 V ± 5% 2 LSB 1/f Noise5 Bandwidth = 0.1 Hz to 10 Hz 6 μV p-p AC ACCURACY Dynamic Range 95.3 dB Oversampled Dynamic Range Oversampling ratio (OSR) = 2 98 dB OSR = 256 119 dB OSR = 1024 125 dB Total RMS Noise 30.4 μV rms
Data Sheet AD4002/AD4006/AD4010 Rev. A | Page 5 of 39 Parameter Test Conditions/Comments Min Typ Max Unit fIN = 1 kHz, −0.5 dBFS, VREF = 5 V Signal-to-Noise Ratio (SNR) 92.5 95 dB Spurious-Free Dynamic Range (SFDR) 122 dB Total Harmonic Distortion (THD) −125 dB Signal-to-Noise-and-Distortion Ratio (SINAD) 92 95 dB fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V SNR 87 89 dB SFDR 122 dB THD −123.5 dB SINAD 87 89 dB fIN = 100 kHz, −0.5 dBFS, VREF = 5 V SNR 95 dB THD −108 dB SINAD 94.8 dB fIN = 400 kHz, −0.5 dBFS, VREF = 5 V SNR 94 dB THD −92 dB SINAD 90 dB −3 dB Input Bandwidth 10 MHz Aperture Delay 1 ns Aperture Jitter 1 ps rms REFERENCE VREF Voltage Range REF − GND 2.4 5.1 V Current V REF = 5 V AD4002 2 MSPS 0.75 mA AD4006 1 MSPS 0.375 mA AD4010 500 kSPS 0.19 mA INPUT OVERVOLTAGE CLAMP IN+/IN− Current, IIN+/IIN− V REF = 5 V 50 mA V REF = 2.5 V 50 mA VIN+/VIN− at Maximum IIN+/IIN− V REF = 5 V 5.4 V V REF = 2.5 V 3.1 V VIN+/VIN− Clamp On/Off Threshold V REF = 5 V 5.25 5.4 V V REF = 2.5 V 2.68 2.8 V Deactivation Time 360 ns REF Current at Maximum IIN+ V IN+ > VREF 100 μA DIGITAL INPUTS Logic Levels Input Low Voltage, VIL VIO > 2.7 V −0.3 +0.3 × VIO V VIO ≤ 2.7 V −0.3 +0.2 × VIO V Input High Voltage, VIH VIO > 2.7 V 0.7 × VIO VIO + 0.3 V VIO ≤ 2.7 V 0.8 × VIO VIO + 0.3 V Input Low Current, IIL −1 +1 μA Input High Current, IIH −1 +1 μA Input Pin Capacitance 6 pF
AD4002/AD4006/AD4010 Data Sheet Rev. A | Page 6 of 39 Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL OUTPUTS Data Format Serial 18 bits, straight binary Pipeline Delay Conversion results available immediately after completed conversion Output Low Voltage, VOL Output current = 500 μA 0.4 V Output High Voltage, VOH Output current = −500 μA VIO − 0.3 V POWER SUPPLIES VDD 1.71 1.8 1.89 V VIO 1.71 5.5 V Standby Current VDD and VIO = 1.8 V, T A = 25°C 1.6 μA Power Dissipation VDD = 1.8 V, VIO = 1.8 V, V REF = 5 V 10 kSPS, high-Z mode disabled 70 μW 500 kSPS, high-Z mode disabled 3.5 4.4 mW 1 MSPS, high-Z mode disabled 7 8.4 mW 2 MSPS, high-Z mode disabled 14 16.5 mW 500 kSPS, high-Z mode enabled 3.8 5.4 mW 1 MSPS, high-Z mode enabled 7.6 10.8 mW 2 MSPS, high-Z mode enabled 15.2 21.5 mW VDD Only 500 kSPS, high-Z mode disabled 2.5 mW 1 MSPS, high-Z mode disabled 4.9 mW 2 MSPS, high-Z mode disabled 9.75 mW REF Only 500 kSPS, high-Z mode disabled 0.95 mW 1 MSPS, high-Z mode disabled 1.9 mW 2 MSPS, high-Z mode disabled 3.65 mW VIO Only 500 kSPS, high-Z mode disabled 0.1 mW 1 MSPS, high-Z mode disabled 0.2 mW 2 MSPS, high-Z mode disabled 0.6 mW Energy per Conversion 7 nJ/sample TEMPERATURE RANGE Specified Performance T MIN to TMAX −40 +125 °C 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4002, 1 MSPS for the AD4006, and 500 kSPS for the AD4010. 2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±2 LSB accuracy. See Figure 43 for more information on ADC input settling for multiplexed applications. 4 The minimum and maximum values are guaranteed by characterization, but not production tested. 5 See the 1/f noise plot in Figure 25.
turbo mode enabled, and fS = 2 MSPS for the AD4002, fS = 1 MSPS for the AD4006, and fS = 500 kSPS for the AD4010, unless otherwise noted. See Figure 47 to Figure 50, Figure 52, Figure 54, Figure 56, Figure 58, Figure 60, Figure 62, and Figure 64 for timing diagrams. Table 2. Digital Interface Timing AD4002, 1 MSPS for the AD4006, and 500 kSPS for the AD4010. 3 For turbo mode, tCNVH must match the tQUIET1 minimum. throughput for different modes of operation. 5 A 50% duty cycle is assumed for SCK. 6 See Figure 24 for SINAD vs. tQUIET2.
Table 3. Register Read/Write Timing 1 See Figure 47 to Figure 50, Figure 52, Figure 54, Figure 56, Figure 58, Figure 60, Figure 62, and Figure 64. 2 For turbo mode, tCNVH must match the tQUIET1 minimum. Table 4. Achievable Throughput for Different Modes of Operation
overvoltage condition for an indefinite amount of time. 1 See the Analog Inputs section for an explanation of IN+ and IN−. 2 Current condition tested over a 10 ms time interval. PCB thermal design is required. resistance measured in a one cubic foot sealed enclosure. θJC is the junction-to-case thermal resistance. Table 6. Thermal Resistance
1 Test Condition 1: thermal impedance simulated values are based upon use
of a 2S2P JEDEC PCB. See the Ordering Guide.
Figure 3. 10-Lead MSOP Pin Configuration
10 VIO
6 CNV
- CONNECT THE EXPOSED PAD TO GND.
MEET THE SPECIFIED PERFORMANCE. Figure 4. 10-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions decoupled closely to the GND pin with a 10 μF, X7R ceramic capacitor. 4 IN− AI Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. Connect to the ground plane of the board. SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high. 8 SCK DI Serial Data Clock Input. When the device is select ed, the conversion result is shifted out by this clock. level on SDI is output on SDO with a delay of 18 SCK cycles. 2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor. performance. Note that the exposed pad only applies to the LFCSP . 1 AI is analog input, P is power, DI is digital input, and DO is digital output.
Figure 23. SNR vs. Decimation Rate for Various Input Frequencies, 2 MSPS Figure 24. SINAD vs. tQUIET2 Figure 25. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 50 kSPS,
2500 Samples Averaged per Reading
Figure 26. THD vs. Input Frequency for Various Source Impedances Figure 27. Zero Error and Gain Error vs. Temperature Figure 28. Analog Input Current vs. Input Differential Voltage
Data Sheet AD4002/AD4006/AD4010 Rev. A | Page 17 of 39 TERMINOLOGY Integral Nonlinearity Error (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 38). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal voltage that results in the first code transition (1/2 LSB above analog ground) and the actual voltage producing that code. Gain Error ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the root mean square (rms) amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: ENOB = (SINAD dB − 1.76)/6.02 ENOB is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to acquire a full-scale input step to ±0.5 LSB accuracy. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency, f. PSRR (dB) = 10 log(P VDD_IN/PADC_OUT) where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output.
Figure 37. ADC Simplified Schematic capable of converting 500,000 samples per second (500 kSPS). making them ideal for multiplexed applications. charge kickback seen from a typical switched capacitor SAR input. for the amplifier, improving stability and power dissipation. 100 kHz and multiplexing functionality, disable high-Z mode. amplifier to access the full range of the ADC. rate of 2 MSPS can be achieved only with turbo mode enabled. Table 8. MSOP, LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs
201 Not
181 AD7989-12 AD76912 AD40112,
183 AD4010 2 AD40022,
161 AD7684 AD7687 2 AD76882,
163 AD7680,
143 AD7940 AD7942 2 AD79462 Not applicable
(DAC). Figure 37 shows the simplified schematic of the ADC. connect the other terminal of each capacitor to the analog inputs. acquire the analog signal on the IN+ and IN− inputs. binary weighted voltage steps (VREF/2, VREF/4, …, VREF/262,144). ADC output code and a busy signal indicator. AD4010 are shown in Figure 38 and Table 9. Figure 38. ADC Ideal Transfer Function (FSR Is Full-Scale Range) Table 9. Output Codes and Ideal Input Voltages 1 This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF with span compression disabled and above 0.9 × VREF with span compression enabled). 2 This output code is also the code for an underranged analog input (VIN+ − VIN− below 0 V with span compression disabled and below 0.1 × VREF with span compression enabled).
Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths input filter, if one is used. commensurate with the AD4002/AD4006/AD4010. capacitor array at an 18-bit level (0.000384%, 3.84 ppm). must be verified prior to driver selection. to the Nyquist frequency of the sample rate in use.
supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and 5.5 V . with SPI, QSPI™, and MICROWIRE® digital hosts and DSPs. the conversions, to be independent of the readback timing (SDI). the Daisy-Chain Mode section.
2 MSPS for the AD4002 can only be achieved with turbo mode
descriptions of turbo mode operation. on the states of CNV and SDI, as shown in Table 11. Table 11. State of SDO on Power-Up ND is the ADC resolution (18 bits). NS is the number of status bits being accessed.
Table 12. AD4002/AD4006/AD4010 Configuration Register
3 Span compression enable Enables span compression (see the Input Span
0: disables span compression. 1: enables span compression.
0 OV clamp flag Indicates an overvoltage event triggered the input
when read after the overvoltage event has ended. 0: indicates an overvoltage event has occurred. 1: indicates no overvoltage event has occurred. Table 13. SCK Frequency Requirements for Various Throughputs
1 MSPS (AD4002/AD4006) 25 MHz
1 MSPS (AD4002/AD4006) 33 MHz
1 MSPS (AD4002/AD4006) 30 MHz
1 MSPS (AD4002/AD4006) 38 MHz
Frequency Requirements and the Status Bits section sections.
a description of each status bit. the number of SCK pulses required per conversion period. out for each connected device. without busy indicator with all six status bits clocked out. Table 15. Status Bit Descriptions
5 OV clamp flag Indicates the state of the OV clamp
flag in the configuration register.
4 Span compression Indicates the state of the span
3 High-Z mode Indicates the state of the High-Z
2 Turbo mode Indicates the state of the turbo mode
Figure 50. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram, Including Status Bits
0.50 BSC
1.10 MAX
Figure 67. 10-Lead Mini Small Outline Package [MSOP]
0.20 REF
0.05 MAX
0.02 NOM
0.20 MIN
Figure 68. 10-Lead Lead Frame Chip Scale Package [LFCSP]
Data Sheet AD4002/AD4006/AD4010 Rev. A | Page 39 of 39 ORDERING GUIDE Model1, 2 Integral Nonlinearity (INL) Temperature Range Package Description Ordering Quantity Package Option Marking Codes AD4002BRMZ ±3.2 LSB −40°C to +125°C 10-Lead MSOP , Tube 50 RM-10 C8E AD4002BRMZ-RL7 ±3.2 LSB −40°C to +125°C 10-Lead MSOP , Reel 1000 RM-10 C8E AD4002BCPZ-RL7 ±3.2 LSB −40°C to +125°C 10-Lead LFCSP , Reel 1500 CP-10-9 C8E AD4006BRMZ ±3.2 LSB −40°C to +125°C 10-Lead MSOP , Tube 50 RM-10 C8Q AD4006BRMZ-RL7 ±3.2 LSB −40°C to +125°C 10-Lead MSOP , Reel 1000 RM-10 C8Q AD4006BCPZ-RL7 ±3.2 LSB −40°C to +125°C 10-Lead LFCSP , Reel 1500 CP-10-9 C8Q AD4010BCPZ-RL7 ±3.2 LSB −40°C to +125°C 10-Lead LFCSP , Reel 1500 CP-10-9 C8U EVAL-AD4002FMCZ AD4002 Evaluation Board compatible with EVAL-SDP-CH1Z 1 Z = RoHS Compliant Part. 2 The EVAL-AD4002FMCZ can also be used to evaluate the AD4006 and AD4010 by limiting the throughput to 1 MSPS and 500 kSPS in its software, respectively (see UG-1042). ©2018–2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the pro perty of their respective owners. D16233-2/21(A)