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16-Bit, 2 MSPS Precision Pseudo Differential ADC Data Sheet AD4000 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Throughput: 2 MSPS maximum INL: ±1.0 LSB maximum Guaranteed 16-bit no missing codes Low power 9.75 mW at 2 MSPS (VDD only) 70 µW at 10 kSPS, 14 mW at 2 MSPS (total) SNR: 93 dB typical at 1 kHz, 90 dB typical at 100 kHz THD: −115 dB typical at 1 kHz, −95 dB typical at 100 kHz Ease of use features reduce system power and complexity Input overvoltage clamp circuit Reduced nonlinear input charge kickback High-Z mode Long acquisition phase Input span compression Fast conversion time allows low SPI clock rates SPI-programmable modes, read/write capability, status word Pseudo differential (single-ended) analog input range: 0 V to VREF with VREF between 2.4 V to 5.1 V Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface SAR architecture: no latency/pipeline delay Guaranteed operation: −40°C to 125°C Serial interface SPI-/QSPI-/MICROWIRE-/DSP-compatible Ability to daisy-chain multiple ADCs and busy indicator 10-lead package: 3 mm × 3 mm LFCSP and 3 mm × 4.90 mm MSOP
APPLICATIONS
Precision data acquisition systems GENERAL DESCRIPTION The AD4000 is a low noise, low power, high speed, 16-bit,
2 MSPS precision successive approximation register (SAR)
analog-to-digital converter (ADC). It incorporates ease of use features that lower the signal chain power, reduce signal chain complexity, and enable higher channel density. The high-Z mode, coupled with a long acquisition phase, eliminates the need for a dedicated high power, high speed ADC driver, thus broadening the range of low power precision amplifiers that can drive this ADC directly while still achieving optimum performance. The input span compression feature enables the ADC driver amplifier and the ADC to operate off common supply rails without the need for a negative supply while preserving the full ADC code range. The low serial peripheral interface (SPI) clock rate requirement reduces the digital input/output power consumption, broadens processor options, and simplifies the task of sending data across digital isolation. Operating from a 1.8 V supply, the AD4000 samples an analog input (IN+) between 0 V to VREF with respect to a ground sense (IN−) with VREF ranging from 2.4 V to 5.1 V. The AD4000 consumes only 14 mW at 2 MSPS with a minimum of 75 MHz SCK rate in turbo mode and achieves ±1.0 LSB INL maximum, no missing codes at 16 bits with 93 dB SNR. The reference voltage is applied externally and can be set independently of the supply voltage. The SPI-compatible versatile serial interface features seven different modes including the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus and provides an optional busy indicator. The AD4000 is compatible with 1.8 V , 2.5 V , 3 V , and 5 V logic, using the separate VIO supply. The AD4000 is available in a 10-lead MSOP or a 10-lead LFCSP with operation specified from −40°C to +125°C. The device is pin compatible with the 18-bit, 2 MSPS AD4003. FUNCTIONAL BLOCK DIAGRAM GND IN+ IN– SDI SCK SDO CNV AD4000 18-BIT SAR ADC SERIAL INTERFACE VIO REF VDD VREF VREF/2 HIGH-Z MODE CLAMP SPAN COMPRESSON TURBO MODE STATUS BITS 2.5V TO 5V 1.8V10µF 1.8V TO 5V 3-WIRE OR 4-WIRE SPI INTERFACE (DAISY CHAIN, CS) 14956-001 Figure 1.
AD4000* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts View a parametric search of comparable parts Evaluation Kits
- AD4000/AD4003 Evaluation Board Documentation Data Sheet
- AD4000: 16-Bit, 2 MSPS Precision Pseudo Differential ADC Data Sheet User Guides
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Rev. 0 | Page 2 of 32 TABLE OF CONTENTS
REVISION HISTORY
10/2016—Revision 0: Initial Version
Rev. 0 | Page 3 of 32 SPECIFICATIONS VDD = 1.8 V; VIO = 1.71 V to 5.5 V; VREF = 5 V; all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, and turbo mode enabled, (fS = 2 MSPS), unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range VIN+ − VIN− 0 VREF V Operating Input Voltage VIN+ to GND −0.1 VREF + 0.1 V VIN− to GND −0.1 +0.1 V Span compression enabled 0.1 × VREF 0.9 × VREF V Input Leakage Current Acquisition phase, T = 25°C 0.3 nA High-Z mode enabled, converting dc input at 2 MSPS 1 µA THROUGHPUT Complete Cycle 500 ns Conversion Time 290 320 ns Acquisition Phase1 290 ns Throughput Rate2 0 2 MSPS Transient Response3 150 ns DC ACCURACY No Missing Codes 16 Bits Integral Linearity Error −1.0 ±0.2 +1.0 LSB Differential Linearity Error −0.5 ±0.15 +0.5 LSB Transition Noise 0.5 LSB Zero Error −4.5 +4.5 LSB Zero Error Drift4 −0.55 +0.55 ppm/°C Gain Error −20 ±3 +20 LSB Gain Error Drift4 −0.92 +0.92 ppm/°C Power Supply Sensitivity VDD = 1.8 V ± 5% 0.5 LSB 1/f Noise5 Bandwidth = 0.1 Hz to 10 Hz 6 µV p-p AC ACCURACY Dynamic Range 93.5 dB Total RMS Noise 37 µV rms fIN = 1 kHz, −0.5 dBFS, VREF = 5 V Signal-to-Noise Ratio (SNR) 91 93 dB Spurious-Free Dynamic Range (SFDR) 112 dB Total Harmonic Distortion (THD) −115 dB Signal-to-Noise-and-Distortion Ratio (SINAD) 91 92.5 dB Oversampled Dynamic Range Oversampling ratio (OSR) = 256, VREF = 5 V 117 dB fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V SNR 85.5 87.5 dB SFDR 115 dB THD −113 dB SINAD 85.5 87 dB fIN = 100 kHz, −0.5 dBFS, VREF = 5 V SNR 90 dB THD −95 dB SINAD 89 dB fIN = 400 kHz, −0.5 dBFS, VREF = 5 V SNR 85 dB THD −91 dB SINAD 84 dB
Rev. 0 | Page 4 of 32 Parameter Test Conditions/Comments Min Typ Max Unit −3 dB Input Bandwidth 10 MHz Aperture Delay 1 ns Aperture Jitter 1 ps rms REFERENCE Voltage Range (VREF) 2.4 5.1 V Current 2 MSPS, VREF = 5 V 0.75 mA OVERVOLTAGE CLAMP IIN+/IIN− VREF = 5 V 50 mA VREF = 2.5 V 50 mA VIN+/VIN− at Maximum IIN+/IIN− VREF = 5 V 5.4 V VREF = 2.5 V 3.1 V VIN+/VIN− Clamp On/Off Threshold VREF = 5 V 5.25 5.4 V VREF = 2.5 V 2.68 2.8 V Deactivation Time 360 ns REF Current at Maximum IIN+ VIN+ > VREF 100 µA DIGITAL INPUTS Logic Levels Input Low Voltage, VIL VIO > 2.7 V −0.3 +0.3 × VIO V VIO ≤ 2.7 V −0.3 +0.2 × VIO V Input High Voltage, VIH VIO > 2.7 V 0.7 × VIO VIO + 0.3 V VIO ≤ 2.7 V 0.8 × VIO VIO + 0.3 V Input Low Current, IIL −1 +1 µA Input High Current, IIH −1 +1 µA Input Pin Capacitance 6 pF DIGITAL OUTPUTS Data Format Serial 16 bits, straight binary Pipeline Delay Conversion results available immediately after completed conversion Output Low Voltage, VOL ISINK = 500 µA 0.4 V Output High Voltage, VOH ISOURCE = −500 µA VIO − 0.3 V POWER SUPPLIES VDD 1.71 1.8 1.89 V VIO 1.71 5.5 V Standby Current VDD and VIO = 1.8 V, T = 25°C 1.6 µA Power Dissipation VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V 10 kSPS, high-Z mode disabled 70 µW
1 MSPS, high-Z mode disabled 7 mW
2 MSPS, high-Z mode disabled 14 16 mW
1 MSPS, high-Z mode enabled 8 mW
2 MSPS, high-Z mode enabled 16 19 mW
VDD Only 2 MSPS, high-Z mode disabled 9.75 mW REF Only 2 MSPS, high-Z mode disabled 3.75 mW VIO Only 2 MSPS, high-Z mode disabled 0.5 mW Energy per Conversion 7 nJ/sample TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +125 °C 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS. 2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full scale input step to ±0.5 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, not production tested. 5 See the 1/f noise plot in Figure 18.
Table 2. Digital Interface Timing 1 See Figure 2 for the timing voltage levels. 2 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS. 3 For turbo mode, tCNVH must match the tQUIET1 minimum. 4 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. 5 A 50% duty cycle is assumed for SCK. 6 See Figure 22 for SINAD, SNR, and ENOB vs. tQUIET2.
Table 3. Register Read/Write Timing 1 For turbo mode, tCNVH must match the tQUIET1 minimum. Figure 2. Voltage Levels for Timing Table 4. Achievable Throughput for Different Modes of Operation
1 See the Analog Inputs section for an explanation of IN+ and IN−. PCB thermal design is required. Table 6. Thermal Resistance
1 Test Condition 1: thermal impedance simulated values are based upon use
of 2S2P JEDEC PCB. See the Ordering Guide.
Figure 3. 10-Lead MSOP Pin Configuration
10 VIO
6 CNV
- CONNECT THE EXPOSED PAD TO GND.
MEET THE SPECIFIED PERFORMANCE. Figure 4. 10-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions decoupled closely to the GND pin with a 10 μF X7R ceramic capacitor. 3 IN+ AI Differential Positive Analog Input. 4 IN− AI Differential Negative Analog Input. 5 GND P Power Supply Ground. CNV is low. In daisy-chain mode, the data is read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows. by clocking in a 16-bit word on SDI on the rising edge of SCK. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor. 1 AI is analog input, P is power, DI is digital input, and DO is digital output.
Rev. 0 | Page 9 of 32 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 30). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal midscale voltage, that is, 0 V , from the actual voltage producing the midscale output code, that is, 0 LSB. Gain Error ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: ENOB = (SINAD dB − 1.76)/6.02 ENOB is expressed in bits. Noise Free Code Resolution Noise free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as Noise Free Code Resolution = log2(2N/Peak-to-Peak Noise) Noise free code resolution is expressed in bits. Effective Resolution Effective resolution is calculated as Effective Resolution = log2(2N/RMS Input Noise) Effective resolution is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to to acquire a full-scale input step to ±0.5 LSB accuracy. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency, f. PSRR (dB) = 10 log(P VDD_IN/PADC_OUT) where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output.
Figure 29. ADC Simplified Schematic first conversion after being powered down for long periods. making it ideal for multiplexed applications. features that result in a lower system power and footprint. device from overvoltage damage on the analog inputs. multiplexing, disable high-Z mode. amplifier to access the full range of the ADC. rate of 2 MSPS can be achieved only with turbo mode. that allows space savings and flexible configurations. Table 8. MSOP, LFCSP 14-/16-/18-Bit Precision SAR ADCs
181 AD7989-12 AD7691 AD7690, AD7989-5 AD4003,
161 AD7684 AD7687 AD7688, AD7693,
163 AD7680,
143 AD7940 AD7942 AD7946
Rev. 0 | Page 15 of 32 two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the IN+ and IN− inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and V REF, the comparator input varies by binary weighted voltage steps REF/2, VREF/4, …, VREF/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and a busy signal indicator. Because the AD4000 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. TRANSFER FUNCTIONS The ideal transfer characteristics for the AD4000 are shown in Figure 30 and Table 9. 000...000 000...001 000...010 111...101 111...110 111...111 ADC CODE (STRAIGHT BINARY) ANALOG INPUT +FSR – 1.5 LSB +FSR – 1 LSB–FSR + 1 LSB–FSR –FSR + 0.5 LSB 14956-007 Figure 30. ADC Ideal Transfer Function (FSR Is Full-Scale Range) Table 9. Output Codes and Ideal Input Voltages
Description
Input, VREF = 5 V VREF = 5 V with Span Compression Enabled (V) Digital Output Code (Hex) FSR − 1 LSB 4.999924 V 4.499939 FFFF 1 Midscale + 1 LSB 2.500076 V 2.500061 8001 Midscale 2.5 V 2.5 8000 Midscale − 1 LSB 2.499924 V 2.499939 7FFF −FSR + 1 LSB 76.3 μV 0.50006103 0001 −FSR 0 V 0.5 00002
1 This output code is also the code for an overranged analog input (VIN+ − VIN−
above VREF − 0 V).
2 This output code is also the code for an underranged analog input (VIN+ −
VIN− below 0 V).
together, daisy-chain mode is always selected. is low when the ADC conversion ends. depending on the states of CNV and SDI, as shown in in Table 11. Table 11. State of SDO on Power-Up data if the status bits are enabled in the configuration register. There are six status bits in total as described in Table 15. of 70 MHz and allows the AD4000 to run at 2 MSPS. Table 14. The overvoltage clamp flag is a read only sticky bit, overvoltage condition when it is set to 0. Table 12. Register Bits Table 13. Command Register mode is enabled, SDO goes low on the rising edge of CNV . Register reads are not allowed in daisy-chain mode. Register write requires three signal lines: SCK, CNV , and SDI. on SDO; however, the register write occurs regardless. 3-wire, 4-wire, and daisy-chain mode. Table 14. Register Map
status bit updates on a per conversion basis. including status bits, is shown in Figure 46. Table 15. Status Bits (Default Conditions) Figure 46. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram, Including Status Bits (SDI High)
turbo mode is enabled and using a minimum SCK rate of 70 MHz. The timing diagram is shown in Figure 47. programming the turbo mode bit, Bit 1 (see Table 14). after the last falling edge of SCK to when CNV is brought high. SDO returns to high impedance. Figure 47. CS Mode, 3-Wire Turbo Mode Serial Interface Timing Diagram (SDI High)
timing diagram is shown in Figure 52. programming the turbo mode register, Bit 1 (see Table 14). With SDI high, a rising edge on CNV initiates a conversion. last falling edge of SCK to when CNV is brought high. SDO returns to high impedance. Figure 52. CS Mode, 4-Wire Turbo Mode Timing Diagram
0.50 BSC
1.10 MAX
Figure 61. 10-Lead Mini Small Outline Package [MSOP]
0.20 REF
0.05 MAX
0.02 NOM
0.20 MIN
Figure 62. 10-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the property of their respective owners.