AD4000

AD4000/AD4004/AD4008 (Rev. F)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 38

Technical content

16-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Rev. F DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Easy Drive expands signal chain flexibility ►High-Z mode significantly reduces signal chain settling re- quirements ►Fast conversion phase extends the ADC acquisition time ►Input overvoltage protection clamp sinks up to 50 mA ►High performance ►First conversion accurate, no latency or pipeline delay ►Guaranteed 16-bit, no missing codes ►Throughput: 2 MSPS/1 MSPS/500 kSPS options ►INL: ±1.0 LSB maximum ►SNR: 93 dB at fIN = 1 kHz, VREF = 5 V ►THD: −115 dB at fIN = 1 kHz; −95 dB at fIN = 100 kHz ►Pseudo differential input range ►Flexible external reference voltage range (2.4 V to 5.1 V) ►Low power ►Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface ►2.5 mW at 500 kSPS (VDD only) ►70 µW at 10 kSPS, 14 mW typical at 2 MSPS (total power) ►SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface ►10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP ►Guaranteed operation: −40°C to +125°C

APPLICATIONS

►Automated test equipment ►Machine automation ►Medical equipment ►Battery-powered equipment ►Precision data acquisition systems ►Instrumentation and control systems GENERAL DESCRIPTION The AD4000/AD4004/AD4008 are high accuracy, high speed, low power, 16-bit, precision successive approximation register (SAR) analog-to-digital converters (ADCs). These ADCs incorporate Easy Drive features, such as high-Z mode and an extended acquisition phase, which provide signal chain architectural flexibility by expand- ing the range of companion circuitry that can be paired with these ADCs. Operating from a single power supply, VDD, these ADCs allow the reference voltage, VREF, to be applied externally and set inde- pendently of the supply voltage. With fast device throughput up to 2 MSPS, the AD4000/AD4004/AD4008 can accurately capture high-frequency signals and implement oversampling techniques to alleviate the challenges associated with antialias filter designs. Additionally, the power consumption of these ADCs scales linearly with throughput. The AD4000/AD4004/AD4008 eliminate the need for a negative supply to the ADC driver amplifier by employing input span com- pression, while preserving access to the full ADC code range. Furthermore, the input overvoltage clamp protects the ADC inputs against overvoltage events, minimizing disturbances on the refer- ence pin and eliminating the need for external protection diodes. By reducing the serial peripheral interface (SPI) clock rate require- ments, the AD4000/AD4004/AD4008 reduce digital input and output power consumption, broaden digital host options, and simplify the task of sending data across digital isolation. The SPI-compatible serial user interface supports 1.8 V, 2.5 V, 3.3 V, and 5 V logic by using the separate VIO logic supply. FUNCTIONAL BLOCK DIAGRAM Figure 1.

Data Sheet AD4000/AD4004/AD4008 TABLE OF CONTENTS analog.com Rev. F | 2 of 38 Evaluating the AD4000/AD4004/AD4008

REVISION HISTORY

5/2023—Rev. E to Rev. F

Data Sheet AD4000/AD4004/AD4008 SPECIFICATIONS analog.com Rev. F | 3 of 38 VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, REF = VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4000, fS = 1 MSPS for the AD4004, and fS = 500 kSPS for the AD4008, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range IN+ voltage (VIN+) − IN− voltage (VIN−) 0 VREF V Operating Input Voltage VIN+ to GND −0.1 VREF + 0.1 V VIN− to GND −0.1 +0.1 V Span compression enabled 0.1 × VREF 0.9 × VREF V Analog Input Current Acquisition phase, T = 25°C 0.3 nA High-Z mode enabled, converting dc input at 2 MSPS 1 µA THROUGHPUT Complete Cycle AD4000 500 ns AD4004 1000 ns AD4008 2000 ns Conversion Time 270 290 320 ns Acquisition Phase1 AD4000 290 ns AD4004 790 ns AD4008 1790 ns Throughput Rate2 AD4000 0 2 MSPS AD4004 0 1 MSPS AD4008 0 500 kSPS Transient Response3 150 ns DC ACCURACY No Missing Codes 16 Bits Integral Nonlinearity Error (INL) −1.0 ±0.2 +1.0 LSB Differential Nonlinearity Error (DNL) −0.5 ±0.15 +0.5 LSB Transition Noise 0.5 LSB Zero Error −4.5 +4.5 LSB Zero Error Drift4 −0.55 +0.55 ppm/°C Gain Error −20 ±3 +20 LSB Gain Error Drift4 −0.92 +0.92 ppm/°C Power Supply Sensitivity VDD = 1.8 V ± 5% 0.5 LSB 1/f Noise5 Bandwidth = 0.1 Hz to 10 Hz 6 µV p-p AC ACCURACY Dynamic Range 93.5 dB Oversampled Dynamic Range Oversampling ratio (OSR) = 2 96 dB OSR = 256 117 dB OSR = 1024 123 dB Total RMS Noise 37 µV rms fIN = 1 kHz, −0.5 dBFS, VREF = 5 V Signal-to-Noise Ratio (SNR) 91 93 dB Spurious-Free Dynamic Range (SFDR) 112 dB

Table 1. (Continued)

2 MSPS, high-Z mode disabled 14 16 mW

2 MSPS, high-Z mode enabled 16 19 mW

MSPS for the AD4004, and 500 kSPS for the AD4008. for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±0.5 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, but not production tested. 5 See the 1/f noise plot in Figure 24.

noted. See Figure 45 to Figure 48, Figure 50, Figure 52, Figure 54, Figure 56, Figure 58, Figure 60, and Figure 62 for timing diagrams. Table 2. Digital Interface Timing MSPS for the AD4004, and 500 kSPS for the AD4008. 3 For turbo mode, tCNVH must match the tQUIET1 minimum.

5 A 50% duty cycle is assumed for SCK. 6 See Figure 23 for SINAD, SNR, and ENOB vs. tQUIET2. Table 3. Register Read/Write Timing 1 See Figure 45 to Figure 48, Figure 50, Figure 52, Figure 54, Figure 56, Figure 58, Figure 60, and Figure 62. 2 For turbo mode, tCNVH must match the tQUIET1 minimum. Table 4. Achievable Throughput for Different Modes of Operation

age condition for an indefinite amount of time. 1 See the Analog Inputs section for an explanation of IN+ and IN−. 2 Current condition tested over a 10 ms time interval. ing conditions for extended periods may affect product reliability. measured in a one cubic foot sealed enclosure. θJC is the junction-to-case thermal resistance. Table 6. Thermal Resistance

1 Test Condition 1: thermal impedance simulated values are based upon use of

2S2P JEDEC PCB. See the Ordering Guide. damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 2. 10-Lead MSOP Pin Configuration Figure 3. 10-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions the GND pin with a 10 µF, X7R ceramic capacitor. IN− on the leading edge on CNV. The operating input range of IN+ − IN− is 0 V to VREF. 4 IN− AI Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. Connect to the ground plane of the board.

6 CNV DI

daisy-chain mode, the data is read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. The SDO pin is synchronized to the SCK signal on the SCK pin. 8 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. device by clocking in a 16-bit word on SDI on the rising edge of SCK.

10 VIO P

Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor. exposed pad only applies to the LFCSP. 1 AI is analog input, P is power, DI is digital input, and DO is digital output.

Figure 34. Standby Current vs. Temperature Figure 35. tDSDO vs. Load Capacitance

Data Sheet AD4000/AD4004/AD4008 TERMINOLOGY analog.com Rev. F | 16 of 38 Integral Nonlinearity Error (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 37). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal voltage that results in the first code transition (½ LSB above analog ground) and the actual voltage producing that code. Gain Error ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: ENOB = (SINAD − 1.76)/6.02 (1) ENOB is expressed in bits and SINAD is expressed in dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic compo- nents to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to acquire a full-scale input step to ±0.5 LSB accuracy. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency, f. PSRR (dB) = 10 log(PVDD_IN/PADC_OUT) (2) where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output.

Figure 36. ADC Simplified Schematic making them ideal for multiplexed applications. charge kickback seen from a typical switched capacitor SAR input. the amplifier, improving stability and power dissipation. multiplexing functionality, disable high-Z mode. cess the full range of the ADC. even when running at their respective maximum throughput rates. be achieved only with turbo mode enabled. of the 14-/16-/18-/20-bit precision SAR ADCs listed in Table 8. Table 8. MSOP and LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs

201 Not applicableNot applicable AD40222 AD40202,

181 AD7989-12 AD76912 AD40112,

183 AD40102 AD40022,

161 AD7684 AD76872 AD76882,

163 AD7680,

143 AD7940 AD79422 AD79462 Not applicable

Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths 1 See the High-Z Mode section. commensurate with the AD4000/AD4004/AD4008. level and must be verified prior to driver selection. can be exported for simulation in LTspice. multiplexer, an ADC driver, and the precision SAR ADC.

descriptions of turbo mode operation. its full throughput of 2 MSPS. the states of CNV and SDI, as shown in Table 11. Table 11. State of SDO on Power-Up mode, and turbo mode, as well as an overvoltage detection flag. and descriptions of each field in the configuration register. Table 12. AD4000/AD4004/AD4008 Configuration Register 0: disables span compression. 1: enables span compression. overvoltage event has ended. 0: indicates an overvoltage event has occurred. 1: indicates no overvoltage event has occurred.

ND is the ADC resolution (16 bits). NS is the number of status bits being accessed. Table 13. SCK Frequency Requirements for Various Throughputs

1 MSPS (AD4000/AD4004) 22

1 MSPS (AD4000/AD4004) 30

1 MSPS (AD4000/AD4004) 27

1 MSPS (AD4000/AD4004) 37

Frequency Requirements and Status Bits sections.

Bit 5 through Bit 0 shown in Table 14 to perform the SPI read/write. tion register are updated after the device receives the full byte. of the configuration register, enable and read the status bits. Table 14. Register Access Command Figure 45. Register Read Timing Diagram

the sixth status bit is clocked out (except in daisy-chain mode). all six status bits must be clocked out for each connected device. without busy indicator with all six status bits clocked out. Table 15. Status Bit Descriptions

5 OV clamp flag Indicates the state of the OV clamp flag in

4 Span compression Indicates the state of the span

3 High-Z mode Indicates the state of the High-Z mode

enable field in the configuration register.

2 Turbo mode Indicates the state of the turbo mode

enable field in the configuration register. Figure 48. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram, Including Status Bits

Data Sheet AD4000/AD4004/AD4008 OUTLINE DIMENSIONS ©2016-2023 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. F | 38 of 38 Updated: May 29, 2023 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option Marking Code AD4000BCPZ-RL7 -40°C to +125°C 10-Lead LFCSP (3mm x 3mm) Reel, 1500 CP-10-9 Y61 AD4000BRMZ -40°C to +125°C 10-Lead MSOP RM-10 Y61 AD4000BRMZ-RL7 -40°C to +125°C 10-Lead MSOP Reel, 1000 RM-10 Y61 AD4004BCPZ-RL7 -40°C to +125°C 10-Lead LFCSP (3mm x 3mm) Reel, 1500 CP-10-9 C8F AD4004BRMZ -40°C to +125°C 10-Lead MSOP RM-10 C8F AD4004BRMZ-RL7 -40°C to +125°C 10-Lead MSOP Reel, 1000 RM-10 C8F AD4008BCPZ-RL7 -40°C to +125°C 10-Lead LFCSP (3mm x 3mm) Reel, 1500 CP-10-9 C8S AD4008BRMZ -40°C to +125°C 10-Lead MSOP RM-10 C8S AD4008BRMZ-RL7 -40°C to +125°C 10-Lead MSOP Reel, 1000 RM-10 C8S 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1, 2 Description EVAL-AD4000FMCZ AD4000 Evaluation Board Compatible with EVAL-SDP-CH1Z 1 Z = RoHS Compliant Part. 2 The EVAL-AD4000FMCZ can also be used to evaluate the AD4004 and AD4008 by setting the throughput to 1 MSPS and 500 kSPS in its software, respectively (see UG-1042).