AD363 AD | Alldatasheet
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ANALOG Complete 16-Channel, 12-Bit DEVICES Data Acquisition Systems FEATURES AD363 FUNCTIONAL BLOCK DIAGRAM AD363 rertencs 16-Channel Data Acquisition Input Stage with: rede nAD36S LIL 'AD363. esa | Digitally Controlled Channel Selection/Mode Control oi fe oe ‘BECTON oxy anatoo-ro-oaraL "Ye cssren =~ |
16 Single-Ended or 8 Differential Channels EL, tS owe OF es g
25 kHz Throughput Rate ind Ean NI v4 Hees g Guaranteed No Missing Codes Over Temperature ik tI ra mr, [> S| = pad : AD364 Teele a Ei Res 3 16-Channel Data Acquisition Input Stage with: aa a IY cf) | Nes Digitally Controlled Channel Selection/Mode Control al N ian |
16 Single-Ended or 8 Differential Channels res | ier os
20 kHz Throughput Rate rit | al eas Guaranteed No Missing Codes Over Temperature AE AZAY AD) CHANNEL SINGLE-ENDY Three-State Buffered Digital Output Comma, | Seer gerne. et PRODUCT DESCRIPTIONS The AD363 and AD364 are complete 16-channel data acquisi- D864 FUNCTIONAL:BLOCK DipenoM tion systems which condition and subsequently convert an ana- face log voltage into digital form. Each system consists of two ree AD3ee LL abaea s8 devices, an analog input stage (AIS) and an analog-to-digital 5 | AE aioe 0-000, converter (ADC). The AIS includes a two 8-channel multiplex- A tS] ax wor 2 Lanne [Pifoorcon ers, a channel address register, a unity gain instrumentation am- 4 i r= Eas N om iM plifier, and a sample-hold amplifier. The multiplexers may be ie oak, [> fear) 4 [Pi omer connected to the instrumentation amplifier in either an 8- Le . Aj | channel differential or 16-channel single ended configuration. A Uso [each [Fy 000-003 unique feature of these products is an internal user controlled aus oe EY switch which connects the multiplexers in either single-ended or differential mode. This allows a single device to perform in ei- ia | aS aie ther mode with hard-wire programming and permits interfacing a mixture of single-ended and differential signals by dynamically Sor”) TS ere switching the input mode control. CMR Si 5 AA TB OUEST The AD363 and AD364 differ in ADC performance. Each ADC is a complete 12-bit successive approximation converter includ- ing an internal clock and a precision reference. Active laser trimming results in maximum linearity errors of +0.012% with conversion times of 25 ws (AD363) or 32 s (AD364). The hy- brid AD363-ADC has five user selectable input ranges (+2.5, +5.0, +10.0, 0 to +5, and 0 to +10 volts) and includes a high impedance buffer amplifier. The AD364-ADC is a monolithic converter with 3-state output buffer circuitry for direct interface to an 8-, 12-, or 16-bit processor bus and three user selected input ranges (+5, +10, and 0 to +10 volts). Both products are specified for operation over both the commer- cial (0°C to +70°C) and military (-35°C to +125°C) temperature ranges. The AD363 and AD364 are available with environmen- tal screening. Please contact the factory or nearest sales office for details. Information furnished by Analog Devices is believed to be accurate and which may result from its use. No license is granted by implication or Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 otherwise under any patent or patent rights of Analog Devices. Telex: 924491 Cable: ANALOG NORWOODMASS.
AD363/AD364 _ SPECIFICATIONS (typical @ +25°C, +15 V and +5 V unless otherwise noted) Parameter AD363RS ANALOG INPUTS Number of Inputs 16 Single-Ended or 8 Differential (Electronically Selectable) | * Input Voltage Ranges Bipolar 2.5 V, +5.0 V, +10.0 V * Unipolar 0t0 +5. V,0t0 +10V * Input (Bias) Current, per Channel +50 nA max * Input Impedance ON Channel 10!° 2, 100 pF * OFF Channel 10!° 0, 10 pF * Input Fault Current (Power OFF or ON) 20 mA, max, Internally Limited * Common-Mode Rejection Differential Mode 70 dB min (80 dB) typ) @ 1 kHz, 20 V p-p * Mux Crosstalk (Interchannel, Any OFF Channel to Any ON Channel) | —80 dB max (—90 dB typ) @ 1 kHz, 20 V p-p * RESOLUTION g ACCURACY Gain Error! +0.05% FSR (Adjustable to Zero) * Unipolar Offset Error +10 mV (Adjustable to Zero) * Bipolar Offset Error +20 mV (Adjustable to Zero) * Linearity Error 1/2 LSB max ad Differential Linearity Error +1 LSB max (1/2 LSB typ) * Relative Accuracy +0.025% FSR * Noise Error 1 mV p-p, 0.1 Hz to 1 MHz * TEMPERATURE COEFFICIENTS Gain +30 ppm/°C max (+10 ppnv/°C typ) +25 ppm/°C max (+15 ppmv/°C typ) Offset, +10 V Range +15 ppm/°C max (+5 ppmv/°C typ) +8 ppmv/"C max (+5 ppm/"C typ) Differential Linearity No Missing Codes Over Temperature Range * SIGNAL DYNAMICS Conversion Time? 25 us max (22 us typ) * Throughput Rate, Full Rated Accuracy 25 kHz min (30 kHz typ) * Sample-and-Hold Aperture Delay 200 ns max (150 ns typ) * Aperture Uncertainty 500 ps max (100 ps typ) * Acquisition Time To +0.01% of Final Value 18 us max (10 pss typ) Lj For Full-Scale Step Feedthrough ~70 4B max (~80 dB typ) @ 1 kHz * Droop Rate 2. mV/ms max (1 mV/ms typ) * DIGITAL INPUT SIGNALS? Convert Command (to ADC Section, Pin 21) Positive Pulse, 200 ns min Width. Leading Edge (“0” to 1") Resets Register, Trailing Edge (“1” to “0”) Starts Conversion *
1 TTL Load *
Input Channel Select (to Analog Input Section, Pins 28-31) 4-Bit Binary Channel Address *
1 LS TTL Load *
Channel Select Latch (to Analog (Input Section, Pin 32) “1” Latch Transparent * “0” Latched *
4 LS TTL Loads *
Sample-Hold Command (to Analog Input Section Pin 13 Normally “0” Sample Mode * Connected to ADC “Status,” “1” Hold Mode * Pin 20) 2 LS TTL Loads * Short Cycle (to ADC Section Pin 14) Connect to +5 V for 12-Bits Resolution * Connect to Output Bit n + 1 for n Bits Resolution * Single-Ended/Differential Mode Select (to Analog Input Section, Pin 1) “0” Single Ended Mode * “1” Differential Mode (+4.0 V min) *
3 TTL Loads *
=—2—
DIGITAL OUTPUT SIGNALS? (All Codes Positive True) Parallel Date Unipolar Code Binary * Bipolar Code Offset Binary/Twos Complement * Output Drive 2 TTL Loads * Serial Data (NRZ Format) Unipolar Code Binary * Bipolar Code Offset Binary bd Output Drive 2 TTL Loads id Status (Status) Logic “1” (“0”) During Conversion * Output Drive 2 TTL Loads * Internal Clock Output Drive 2 TTL Loads * Frequency 500 kHz * INTERNAL REFERENCE VOLTAGE, +10.00 V, +10 mV * ‘Max External Current +lmA * Voltage Temperature Coefficient +20 ppm/°C max * POWER REQUIREMENTS Supply Voltages/Currents +15 V, 5% @ +45 mA max (+38 mA typ) * =15 V, 5% @ —45 mA max (—38 mA typ) * +5 -V, 5% @ +136 mA max (+113 mA typ) * Total Power Dissipation 2 Watts max (1.7 Watts typ) * TEMPERATURE RANGE Specification OFC to +70°C =55°C to +125°C Storage =55°C to +150°C =55°C to +150°C PACKAGE OPTIONS Analog Input Section (DH-32E) AD363RKD AD363RSD AD Section (DH-32C) AD363RKD AD363RSD NOTES ‘With 50 , 1% fixed resistor in place of Gain Adjust pot. *Conversion time of ADC Section. @ Vy = 0.4 Vy yy = 20 pA max @ Vyyq = 2.7 V. *Specifications same as AD363RK. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS (ALL MODELS) +V, Digital Supply 6.0.00. e eee eee ee F55V AGND:to: DGND iscsi aes weenie 22 Setecear SPV -3-
D363 PIN FUNCTION DESCRIPTION ANALOG INPUT SECTION ANALOG-TO-DIGITAL CONVERTER SECTION Number Number | Function
1 Single-End/Differential Mode Select 1 Data Bit 12 (Least Significant Bit) Out
“0”: Single-Ended Mode 2 Data Bit 11 Out “1”; Differential Mode (+4.0 V min) 3 Data Bit 10 Out
2 Digital Ground 4 Data Bit 9 Out
3 Positive Digital Power Supply, +5 V 5 Data Bit 8 Out
4 “High” Analog Input, Channel 7 6 Data Bit 7 Out 5 “High” Analog Input, Channel 6 7 Data Bit 6 Out 6 “High” Analog Input, Channel 5 8 Data Bit 5 Out 7 “High” Analog Input, Channel 4 9 Data Bit 4 Out 8 “High” Analog Input, Channel 3 10 Data Bit 3 Out 9 “High” Analog Input, Channel 2 u Data Bit 2 Out 10 “High” Analog Input, Channel 1 12 Data Bit 1 (Most Significant Bit) Out oT “High” Analog Input, Channel 0 13 Data Bit | (MSB) Out
12 No Connect 4 Short Cycle Control
13 Sample-Hold Command Connect to +5 V for 12 Bits
“Q”: Sample Mode Connect to Bit (n + 1) Out for n Bits “1”: Hold Mode 15 Digital Ground Normally Connected to ADC Pin 20 16 Positive Digital Power Supply, +5 V
14 Offset Adjust 17 Status Out
15 Offset Adjust “0”: Conversion in Progress
16 Analog Output (Parallel Data Not Valid)
Normally Connected to ADC “1”; Conversion Complete “Analog In” (Parallel Data Valid)
17 Analog Ground 18 +10 V Reference Out
18 “High” (“Low”) Analog Input, Channel 15 (7) 19 Clock Out (Runs During Conversion) 19 “High” (“Low”) Analog Input, Channel 14 (6) 20 Status Out
20 Negative Analog Power Supply, —15 V “0”: Conversion Complete
21 Positive Analog Power Supply, +15 V (Parallel Data Valid)
22 “High” (“Low”) Analog Input, Channel 13 (5) “1”: Conversion in Progress 23 “High” (“Low”) Analog Input, Channel 12 (4) (Parallel Data Not Valid) 24 “High” (“Low”) Analog Input, Channel 11 (3) 21 Convert Start In 25 “High” (“Low”) Analog Input, Channel 10 (2) Reset Logic ___—— 26 “High” (“Low”) Analog Input, Channel 9 (1) Start Convert W¥— 27 “High” (“Low”) Analog Input, Channel 8 (0) 2 Comparator In
28 Input Channel Select, Address Bit AE 23 Bipolar Offset
29 Input Channel Select, Address Bit AO Open for Unipolar Inputs
30 Input Channel Select, Address Bit Al Connect to ADC Pin 22 for
31 Input Channel Select, Address Bit A2 Bipolar Inputs
32 Input Channel Select Latch 24 10 V Span R In
“0”: Latched 25 20 V Span R In “1”: Latch “Transparent” 26 Analog Ground
7 Gain Adjust
28 Positive Analog Power Supply, +15 V
29 Buffer Out (for External Use)
30 Buffer In (for External Use)
31 Negative Analog Power Supply, 15 V
32 Serial Data Out
Each Bit Valid on Trailing (~¥_) Edge Clock Out, ADC Pin 19 aa
SPECIFICATIONS pica co +25, +15:v and +5 vuness oterwise notes AD363/AD364 Peamae Uni ANALOG INPUTS Number of Inputs 16 Single-Ended or 8 Differential (Electronically Selectable) Input Voltage Range Tess 00 Te +10 * * * v Input (Bias) Current per Channel +50 * * * nA Input Impedance ON Channel 10100 * * i QlpF OFF Channel 10°10 * * * Q\\pF Input Fault Current 20 * * * mA max (Power ON or OFF) (Internally Common-Mode Rejection Limited) Differential Mode 1 kHz 20 V p-p__ | 70 min (80 typ) * * * 4B ‘Mux Crosstalk (Any OFF CHANNEL to Any ON Channel) 1 kHz 20V pp 80 max (—90 typ) * * * 4B Offset, Channel to Channel 5 * * * mV max ACCURACY Gain Error! 0.3 * % of FSR Unipolar Offset Error? +10 +8 mV Bipolar Offset Error +50 +20 mV Linearity Error 0.024 0.012 % of FSR max Teasg to Tina 0.024 0.012 % of FSR max Differential Linearity Error 0.024 0.012 % of FSR max Torin 10 Terex 0.024 0.012 % of FSR max Noise Error 1 mV p-p 0.1 Hz to 1 MHz * TEMPERATURE COEFFICIENTS Gain 54 31 * bi ppm/°C Offset (+10 V Range) 2 7 * ” ppm/°C Operating Temperature Range 0°C to +70°C * =55°C to +125°C | *#* ppm/*C SIGNAL DYNAMICS Conversion Time 32 max (25 typ) = ps Throughput Rate, Full Accuracy 20 min (25 typ) *, kHz Sample-Hold Aperture Delay 200 max (150 typ) * ns Aperture Uncertainty 500 max (100 typ) * ps Acquisition Time To 0.01% of Final Value For Full-Scale Step 18 max (10 typ) * bs Feedthrough at 1 kHz 70 max (—80 typ) * 4B Droop Rate 2 max (1 typ) * mV/ms DIGITAL INPUT SIGNALS Analog Input Section Input Channel Select 4 Bit Binary Address * *
1 LS TTL Load * *
Channel Select Latch “1” Latch Transparent * * “0” Latched * *
4 LS TTL Loads * *
Single-Ended/Differential “0” Single Ended * * Mode Select “1” Differential (+4 V min) * *
3 TTL Loads * *
Sample-and-Hold Command “0” Sample Mode * * “1” Hold Mode * *
1 TTL Load * *
ADC Section? 4.5<V, <5.5 Logic Input Threshold Teg to Tez Logic “1” 2.0 * * V min Logic “0” 0.8 « = V max Logic Input Current Trnin tO Tmax Logic “1” 20 * * pA max Logic “0” 20 * * pA max
Logic Outputs Twain t0 Trnax Sink Current Vour = 0.4 V 16 mA min Source Current Vour = 2.4 V 0.5 mA min Output Leakage When in Three State +40 HA max Output Coding Unipolar Positive True Binary Bipolar Positive True Offset Binary POWER REQUIREMENTS Supply Voltages/Currents +15 V, 5% @ 36 mA max -15 V, =5% @ 65 mA max +5 V, +5% @ 75 mA max PACKAGE OPTIONS Analog Input Section (DH-32E) AD364RJD AD364RKD | AD364RSD AD364RTD ADC Section (D-28) AD364RJD AD364RKD_| AD364RSD AD364RTD NOTES {With 50 resistor from REF IN to REF OUT. Adjustable to zero. 2Adjustable to zero. 3128 line must be hard wired to Voce oF digital common. *Specifications same as AD364RJ. Specifications same as AD364RK *Specifications same as AD364RS. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS (ALL MODELS) AV; -Digital'Supply: % sscionies os casa sepocwea tS VY: -6-
AD364 PIN FUNCTION DESCRIPTION ANALOG INPUT SECTION ANALOG-TO-DIGITAL CONVERTER SECTION oe ee [ed Number Number | Function
1 Single-End/Differential Mode Select 1 Logic Power Supply, +5 V
“Q” Single-Ended Mode 2 Data Mode Select (12/8) “1” Differential Mode “0”: 8 Upper Bits or
2 Digital Common 4 Lower Bits as Selected by Byte
3 Positive Digital Power Supply, +5 V Select (Ag))
4 “High” Analog Input, Channel 7 3 Chip Select (CS) 5 “High” Analog Input, Channel 6 “0”: Device Selected 6 “High” Analog Input, Channel 5 “1”: Device Inhibited 7 “High” Analog Input, Channel 4 4 Byte Address/Short Cycle (Ao) 8 “High” Analog Input, Channel 3 “0”: Upper 8 Bits Enabled (12/8 “0”)/ 9 “High” Analog Input, Channel 2 12-Bit Cycle 10 “High” Analog Input, Channel 1 “1”: Lower 4 Bits Enabled (12/8 “1”)/ ry “High” Analog Input, Channel 0 8-Bit Cycle
12 No Connect 5 Read Convert (R/C)
1B Sample-Hold Command “0”: Convert Start “0”: Sample Mode “1: Read Enable “1”: Hold Mode 6 Chip Enable (CE) Normally Connected to ADC Pin 28 _& : RIC “0,” CS “0” Initiates Conversion
14 Offset Adjust F : RC “1,” CS “0” Initiates Read
15 Offset Adjust “0”: Device Disabled
16 Analog Output “1”: Device Enabled
Normally Connected to ADC 7 Analog Power Supply, +15 V (Vec) “Analog In” 8 Reference Out, +10 V
7 Analog Common 9 Analog Common (AC)
18 “High” (“Low”) Analog Input, Channel 15 (7) 10 Reference In 19 “High” (“Low”) Analog Input, Channel 14 (6) ul Analog Power Supply, —15 V (Vp)
20 Negative Analog Power Supply, —15 V 12 Bipolar Offset
21 Positive Analog Power Supply, +15 V B 10 V Span Input
22 “High” (“Low”) Analog Input, Channel 13 (5) 14 20 V Span Input 23 “High” (“Low”) Analog Input, Channel 12 (4) 15 Digital Common (DC) 24 “High” (“Low”) Analog Input, Channel 11 (3) 16 Data Bit 0 25 “High” (“Low”) Analog Input, Channel 10 (2) 7 Data Bit 1 26 “High” (“Low”) Analog Input, Channel 9 (1) 18 Data Bit 2 27 “High” (“Low”) Analog Input, Channel 8 (0) 19 Data Bit 3
28 Input Channel Select, Address Bit AE 20 Data Bit 4
29 Input Channel Select, Address Bit AO 21 Data Bit 5
30 Input Channel Select, Address Bit Al 22 Data Bit 6
31 Input Channel Select, Address Bit A2 23 Data Bit 7
32 Input Channel Select Latch 24 Data Bit 8
“0”: Latched 25 Data Bit 9. “1”: Latch “Transparent” 26 Data Bit 10
27 Data Bit 11
28 Status Out
AR 20008, min processor interface applications, the Ag line must be properly Sane Bun, max controlled during both the convert start and read functions. Toon stoce Io, STANDARD FULL CONTROL INTERFACE eee BSS SY % % ete So The timing for the standard full control interface is shown in starus_ F2—— conversion w prooness =] Figure 5. In this operating mode, CS is used as the address in- es err put which selects the particular device, R/C selects between the = read data and start conversion functions, and CE is used to time wire A\\\\ 2 i ai the actual functions. a ag 2 aaah Fe «ff ?7 _ one ' ee ets ee = oe SL eee = ees or TE +f} +, — CN aE es aS rr rd me es gg ol Weer a : So Figure 5. AD364-ADC Timing Diagram tte) ball \\\\N TS cd Eo oad SS left side of the figure shows the conversion start control. CS . ee " . and R/C are brought low (their sequence does not matter), then ee Tee ren aly code the start pulse is applied to CE. The timing diagram shows a time delay for CS and R/C prior to the start pulse at CE. If less 4 re time than this is allowed, the conversion will still be started, but The two major control functions, convert start and read enable, an appropriately longer pulse will be needed at CE. However, s ‘el ‘ ger il . > are controlled by CB, CS, and R/C. Athoughiall:three inputs if the hold times for CS and R/C after the rising edge of the must be in the correct state to perform the function (for convert 1 CE followed, thi zs be start, CE = 1, CS = 0, R/C = 0; for read enable, CE = 1, CS ‘ses a AUC EIATS OLN O WSR /Mie conver aowmuay/nee = 0, RIC = 1), the sequence does not matter. For large sys- tivated , , tems, typically microprocessor controlled, standard operation for The Ag line determines the conversion cycle length and must be convert start would be to first set R/C = 0 (from R/W line); ad- _selected prior to conversion initiation. If Ao is low, a 12-bit cy- dress the chip with CS = 0, then apply a positive start pulse to _cle results; if Ao is high, an 8-bit short cycle results. Minimum CE. A read would be done similarly but with R/C = 1. setup and hold times are shown. The status line goes high to Pa . dicate conversion in progress. The analog input signal is al- Ao (byte select) and 12/8 (data format) inputs work together to a ; ‘ control the output data and conversion eycle. In almost all situa- Owed to vary nati the STS goes high. It must then be held tions 12/8 is hard-wired “high” (to Vi ogic) or “low” (to Digital — *°@dy unui AGRI DOES POW. ALE: COME, CORYEESION: Common). If it is wired high, all 12 data lines will be enabled The data read function operates in a similar fashion except that when the read function is called by the general control inputs. RIC is now held high. The data is stored in the output register For an 8-bit bus interface, 12/8 will be wired low. In this mode, and can be recalled at will until a new conversion cycle is com- only the 8 upper bits or the 4 lower bits can be enabled at once, manded. In addition, if the converter is arranged in the 8-bit as addressed by Ag. For these applications, the 4 LSBs (Pins data mode, the Ag line now functions as the byte select address, 16-19) should be hard-wired to the 4 MSB (Pins 24-27). Thus, with setup and hold times as shown. With Ao low, Pins 20 to during a read, when Ao is low, the upper 8 bits are enabled and 27 (DB4-11) come dut of three-state and present data. With Ag present data on Pins 20 through 27. When Ao goes high, the high, Pins 16-19 (DBO-3) come out of three-state with data and upper 8 data bits are disabled, the 4 LSBs then present data to Pins 20-23 present active trailing zeros. In the 8-bit mode, Pins Pins 24 to 27, and the 4 middle bits are overridden so that zeros 16-19 will be hard-wired directly to Pin 24-27 for direct two are presented to Pins 20 through 23. byte loading onto an 8-bit bus. There are two delay times for ‘The Ag input performs an additional function of controlling the data lines after CE is brought low: typ is the delay until the conversion length. If Ag is held low prior to cycle initiation, a outputs are fully into the high impedance state. full 12-bit, 25 ps cycle will result; if Ao is held high prior to STANDALONE OPERATION cycle initiation, a shortened 8-bit, 16 ps cycle will result. The For simpler control functions, the AD364-ADC can be con- Ao line must be set prior to cycle initiation and held in the de- trolled with just R/C. In this case, CE is wired high, CS low, sired position at least until STS goes high. Thus, for micro- 12/8 high, and Ao low. There are two ways of cycling the device gl o -9-
When the channel address is changed, six microseconds must be ANALOG allowed for the Analog Input Section to settle to within +0.01% oes of its final output (including settling times of all elements in the signal path). The effect of this delay may be eliminated by per- - saupte forming the address change while a conversion is in progress ourpur aN (with the sample-and-hold in the “hold” mode). All unused in- HOLD puts must be grounded. Input Channel Address Latch soonrVY/ |" The AIS is equipped with a latch for the Input Channel Select OFFSET VOLTAGE address bits. If the Latch Control pin (Pin 32) is at Logic “1,” AONE. TOE ANALOG (15) input channel select address information is passed through to Figure 8. AIS Offset Voltage Adjustment the multiplexers. A Logic “0” “freezes” the input channel ee at the inputsiat the 1 "-to-"0) mansicion Under normal conditions, all calibration is performed at the ADC Section. This feature is useful when input channel address information is . provided from an address, data or control bus that may be re- Gain Adjust, AD363-ADC: Gain may be adjusted by connect- quired to service many devices. The ability to latch an address ising @ 100 © potentiometer between +10 V Reference Output helpful whenever the user has no control of when address infor- and Gain Adjust Input (ADC Pins 18 and 27). A multi-turn, mation may change. low Lay nies coefficient Poeenenee such asa oon cermet device, is recommended. This potentiometer may be re- Semple-aed-Hold Mode(Coatrol Sa placed with a 50 0, 0.1% resistor to obtain an absolute gain cali- The Sample-and-Hold Mode Control input (Pin 13) is normally bration of 0.05% without trimming. connected to the Status output (Pin 20) from an analog-to-digital . oo, converter. When a conversion is initiated by applying a Convert Offset Adjust, AD363-ADC: The simplest offset adjust circuit Staet command t0 the ADC, Status goes-to Loaic “1,” :purting requires a 20-turn, 20 kM cermet potentiometer and a 3.9 MO the sample-and-hold in to the “Hold” mode. This “freezes” the _Tesistor as shown in Figure 9a. This arrangement has an adjust- information to be digitized for the period of conversion. When ment range of +8 LSBs, and will contribute a maximum of the conversion is complete, Status returns to Logic “0” and 2.3 ppm/°C offset drift with a carbon composition fixed resistor the sample-and-hold returns to the “Sample” mode. Eighteen (TC = -1200 ppm/*C). Drift contributions from the offset ad- ‘icssacicida aaa oe Manned teeta xemnnke-nk bald tae just circuit can be reduced well below this level using metal-film quire (“catch up” to) the analog input to within +0.01% of the resistors and the circuit of Figure 9b. final value before a new Convert Start command is issued. Gain Adjust, AD364-ADC: Gain may be adjusted by connect- The purpose of a sample-and-hold is to “stop” fast changing ing a 100 © potentiometer between the Reference Output and input signals long enough to be converted. In this application, it Reference Input (ADC Pins 8 and 10). A multi-turn, low tem- aloo uallciees the ser 10 charge channels andicr SE/DERI mode perature coefficient potentiometer, such as a 20T cermet device, while a conversion is in progress thus eliminating the effects of is recommended. A fixed 50 0, 1% resistor should be connected multiplexer, analog switch and differential amplifier settling between Pins 8 and 10 if no gain trim is required. times, If maximum throughput rate is required for slowly changing signals, the Sample-and-Hold Mode Control may be aT som wired to ground (Logic “0”) rather than to ADC Status thus 20k : ‘AD363-ADe leaving the sample-and-hold in a continuous sample mode. am Analog Input Section Offset Adjust Circuit ze Although the offset voltage of the AIS may be adjusted, that Figure 9a adjustment is normally performed at the ADC. In some special 7 applications, however, it may be helpful to adjust the offset of 4tsv the Analog Input Section. An example of such a case would be ee if the input signals were small (<10 mV) relative to the AIS 20k al -—(3) AD363-ADC voltage offset and if a gain stage was to be inserted between the 20T 11k MF AIS and the ADC. To adjust the offset of the AIS, the circuit ~15V shown in Figure 8 is recommended. Figure 9b. Offset Adjust, AD364-ADC: Offset adjust circuits for unipolar and bipolar operation are shown in Figures 10a and 10b. In each case the potentiometer should be a multi-turn, low temperature coefficient device, such as 20-turn cermet. Lowest offset drift in unipolar operation will be realized when the fixed resistors are low-TC (100 ppm/*C) metal-film types. -1-
AD363/AD364 ORDERING GUIDE Temperature Model Range Package Option AD363RKD | 0°C to +70°C DH-32E (Analog Input Section) DH-32C (ADC Section) AD363RSD | —55°C to +125°C | DH-32E (Analog Input Section) DH-32C (ADC Section) AD364RJD |0°C to +70°C DH-32E (Analog Input Section) D-28 (ADC Section) AD364RKD | 0°C to +70°C DH-32E (Analog Input Section) D-28 (ADC Section) AD364RSD | —55°C to +125°C | DH-32E (Analog Input Section) D-28 (ADC Section) AD364RTD | —55°C to +125°C | DH-32E (Analog Input Section) D-28 (ADC Section) 0.100 (2.58) -| f+ 0.005 (0.13) MIN rman | tr ani rian 0.580 (14.73)
0.232 MAX heel
0.125 (3.18) sie lk L 08s 1.85 F Passo ‘T0174 (0.36) +{frecosiossymm —_acosczasy man} fx 2 ———. SM. 1 | 16 1.620 (41.14) + 0.280 (7.11) MAX 0150(8.87) | | | | | tit 9190088) ST eae if 0.145 (268) = cles clea ak | 0.120 (3.05) max ACE) 0.015 (0.38) 0.930 (23.62) E . =13-
-14-
-16-
o Q Zz a a Fe Fa Fa -16-