AD3551R

AD3551R (Rev.A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 59

Technical content

Single Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►16-bit resolution ►33 MUPS rate in fast mode ►22 MUPS rate in precision mode ►65 ns small signal settling time to 0.1% accuracy ►100 ns large signal settling time to 0.1% accuracy ►Ultra small glitch: < 50 pV×s ►Ultra low latency: 5 ns ►THD: −105 dB at 1 kHz ►Highly configurable output voltage span and offset ►1.2 V and 1.8 V logic level compatible ►Single (classic), dual, and quad SPI modes ►Multiple error detectors, both analog and digital domains ►2.5 V internal voltage reference, 10 ppm/°C maximum tempera- ture coefficient ►5 mm × 5 mm LFCSP

APPLICATIONS

►Instrumentation ►Hardware in the loop ►Process control equipment ►Medical devices ►Automated test equipment ►Data acquisition system ►Programmable voltage sources ►Optical communications GENERAL DESCRIPTION The AD3551R is a low drift, single channel, ultra-fast, 16-bit accu- racy, current output digital-to-analog converter (DAC) that can be configured in multiple voltage span ranges. The AD3551R operates with a fixed 2.5 V reference. Each DAC incorporates three drift compensating feedback resistors for the required external transimpedance amplifier (TIA) that scales the output voltage. Offset and gain scaling registers allow for generation of multiple output span ranges, such as 0 V to 2.5 V, 0 V to 5 V, 0 V to 10 V, −5 V to +5 V, and −10 V to +10 V, and custom intermediate ranges with full 16-bit resolution. The DAC can operate in fast mode for maximum speed or precision mode for maximum accuracy. The serial peripheral interface (SPI) can be configured in quad SPI mode, dual SPI mode, and single SPI (classic SPI) mode with single date rate (SDR) or double data rate (DDR), with logical levels from 1.2 V to 1.8 V. The AD3551R is specified over the extended industrial temperature range (–40°C to +105°C). Table 1. Related Devices with a wide scope and will be phased in as quickly as possible. Thank you for your patience.

analog.com Rev. A | 2 of 59

REVISION HISTORY

3/2023—Rev. 0 to Rev. A Changed 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC to Single Channel, 16-Bit, 33 MUPS,

analog.com Rev. A | 3 of 59 2/2022—Revision 0: Initial Version

analog.com Rev. A | 4 of 59

ELECTRICAL CHARACTERISTICS

noted. Table 2. Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 16 Bits Relative Accuracy (INL) −2 +2 LSB 5 V range only −4 +4 LSB All other ranges2 Differential Nonlinearity (DNL) −1 +1 LSB Precision mode: −40°C to +105°C, fast mode: 0°C to 85°C −2 +2 LSB Fast mode: −40°C to +105°C −2 +2 LSB 0 V to 2.5 V range, fast or precision modes2 Offset Error 0.03 %FSR Midscale, 25°C Offset Error Drift2 2 8 ppm FSR/°C0 V to 5 V and 0 V to 10 V ranges 4 16 ppm FSR/°CAll other ranges Full-Scale Error 0.04 %FSR 25°C Full-Scale Error Drift2 1 5 ppm FSR/°C0 V to 5 V and 0 V to 10 V ranges 4 12 ppm FSR/°CAll other ranges Zero-Scale Error3 0.05 %FSR 25°C Zero-Scale Error Drift2 3.5 8 ppm FSR/°C0 V to 5 V and 0 V to 10 V ranges 7 16 ppm FSR/°CAll other ranges Total Unadjusted Error (TUE) −0.5 +0.5 %FSR DC Power Supply Rejection Ratio (PSRR) 0.6 mV/V DAC code = midscale OUTPUT CHARACTERISTICS Output Current IOUTx 1.6 mA Absolute value REFERENCE OUTPUT Output Voltage 2.492 2.5 2.508 V At 25°C, over lifetime Voltage Reference Temperature Coefficient (TC)4 3 10 ppm/°C Output Impedance 50 mΩ Output Voltage Noise 2.7 µV rms 0.1 Hz to 10 Hz Output Voltage Noise Density 173 nV/ Hz f = 1 kHz, no load on VREF 164 nV/ Hz f = 10 kHz, no load on VREF Capacitive Load Stability2 10 µF Load Regulation 50 µV/mA At 25°C Output Current Load Capability ±8 mA Line Regulation 135 µV/V At 25°C REFERENCE INPUT Reference Current 1 μA Reference Input Range2 VREF 2.4 2.5 2.6 V Reference Input Impedance 3 MΩ LOGIC INPUTS Input Current II −1 +1 µA Per pin Input Low Voltage VIL 0.35 × VLOGIC V Input High Voltage VIH 0.65 × VLOGIC V Pin Capacitance CI 4 pF

Table 2. (Continued) 1 See the Terminology section. 2 Guaranteed by design and characterization, not production tested. 4 Reference temperature coefficient is calculated as per the box method.

Table 3. (Continued) 1 See the Terminology section.

22 MUPS6

1 All input signals are specified with tR = tF = 1 ns/V (10% to 90%) and timed from a voltage level of (VIL + VIH)/2. 2 Guaranteed by design and characterization, not production tested.

3 The SCLK sampling edge refers to the SCLK edge where the data is read in (sampled)

4 Same timing must be expected at power-up from the instant that AVDD = 4 V or DVDD = 0.8 V. 5 Time required to exit power-down to normal mode. 6 MUPS is mega updates per second.

TA = 25°C, unless otherwise noted. ing conditions for extended periods may affect product reliability. θJA is the natural convection junction to ambient thermal resistance. dependent on the test board and test environment. Table 6. Thermal Resistance

1 Simulation values on JEDEC 2S2P board with 9 thermal vias, still air (0 m/sec

damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 12. Pin Configuration Table 7. Pin Function Descriptions 1 DVDD S Digital Core Power Supply. 1.8 V ± 5%. 2 VLOGIC S Digital Interface Power Supply. 1.2 V to 1.8 V. 3 CS DI Chip Select, Active Low Logic Input. This is the frame synchronization signal for the input data. 4 SCLK DI Serial Clock Input. 5 SDI/SDIO0 DI/O Serial Data Input in Classic SPI Mode. Serial Bidirectional Input/Output Bit 0 in Dual or Quad SPI Modes. 6 SDO/SDIO1 DI/O Serial Data Output in Classic SPI Mode. Serial Bidirectional Input/Output Bit 1 in Dual or Quad SPI Modes. 7 SDIO2 DI/O Serial Bidirectional Input/Output Bit 2 in Quad SPI Mode. Pull down if not used. 8 SDIO3 DI/O Serial Bidirectional Input/Output Bit 3 in Quad SPI Mode. Pull down if not used. automatically updated when new data is written to the input register. in the mask register. This pin has an internal configurable pull-up resistor. 12 to 18, 32DNC DNC Do Not Connect. Leave pins floating. 19 AVDD S Analog Power Supply. 5 V ± 5%. 20 VREF AI/O Voltage Reference, 2.5 V. Input when using external reference, output or floating when using internal reference. 21 CVREF AI/O Decoupling Capacitor for Internal Reference, Optional. 22 AGND S Analog Ground Reference. It is recommended to connect DGND and AGND to the same ground plane under the device. 23 RFB4 _0 AI/O Hardware Gain Selection for DAC0, Gain = 4. 24 RFB2 _0 AI/O Hardware Gain Selection for DAC0, Gain = 2. 25 RFB1 _0 AI/O Hardware Gain Selection for DAC0, Gain = 1. 26 IOUT0 AI/O DAC0 Output Current. 27 VCM0 AO Common-Mode Voltage for DAC0 External TIA. 28 NCAP0 AI/O Noise Reduction Capacitor for DAC0, Optional. Capacitor connected to GND. 29 PCAP0 AI/O Noise Reduction Capacitor for DAC0, Optional. Capacitor connected to AVDD. 30 DGND S Digital Ground Reference. It is recommended to connect DGND and AGND to the same ground plane under the device. 31 QSPI DI QSPI Mode Enable. Digital input. A high level enables quad SPI interface mode. EPAD Exposed Pad. Connect this pad to AGND and provide thermal vias, as explained in the Layout Guidelines section. 1 The AD3551R is pin compatible with the AD3552R.

analog.com Rev. A | 21 of 59 Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a meas- urement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. Offset Error Offset error is the vertical deviation from the ideal transfer func- tion after the gain error has been compensated. Offset error is expressed in mV. In the AD3551R, offset error is measured at midscale. The comparison between the ideal output and the actual output is performed at midscale. Offset Error Drift The offset error drift is a measurement of the relative variation of the offset with temperature. It is expressed in ppm/°C. Total offset at a given temperature is calculated as O f f se t T = O f f s et 25 ° C + T C × T − 25 × V R AN G E 10 6 Full-Scale and Zero-Scale Error These errors measure the deviation from the ideal value at full scale and zero scale, at 25°C. The error is expressed as % of full-scale range (FSR). In the case of the AD3551R, the ideal value is calculated as the average of a sufficiently high number of samples. Full-Scale and Zero-Scale Error Drift These parameters measure the variation of the zero-scale and full-scale voltage as a function of the temperature, relative to the ideal zero-scale and full-scale voltages. They are expressed in ppm/°C. The total deviation over temperature is calculated using the same formula used for the offset. DC PSRR and AC PSRR PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in the supplies for midscale output of the DAC. DC PSRR is measured in mV/V, and AC PSRR is measured in dB. VREF is held at 2.5 V, and the supplies are varied by ±200 mV p-p. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level within a given accuracy for a given step change. Typically, it is evaluated for a small step and a large step to account for the effect of amplifier slewing. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV × sec and is measured when the digital input code is changed by 1 LSB. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. Digital feedthrough is specified in nV × sec and measured with a full-scale code change on the data bus, which means from all 0s to all 1s and vice versa. Output Noise Spectral Density Noise spectral density is a measurement of the internally generat- ed random noise. Noise is measured at the DAC output when it is loaded with the midscale code and using an ideal external reference. Noise is also measured at the output of the internal reference, if available. Noise density is expressed in nV/Hz . Figure 32 depicts the spectral density of the noise in the 1/f region and the flat (broadband) region, whereas the specification quoted in Table 2 pertains to the flat region. Total Harmonic Distortion (THD) THD is the difference between the sine wave played by the DAC and an ideal sine wave of the same frequency and amplitude. The deviation from an ideal sine wave is due to time and amplitude discretization and nonlinear distortion. THD is measured as the power ratio of the sum of harmonic components to the fundamental component. It is expressed in dB. Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C, as shown in the following equation: T C = V RE F _ M A X − V R EF _ MI N V RE F _ NOM × TEMP _ R AN GE × 10 6 (1) where: VREF_MAX is the maximum reference output measured over the total temperature range. VREF_MIN is the minimum reference output measured over the total temperature range. VREF_NOM is the nominal reference output voltage, 2.5 V. TEMP_RANGE is the specified temperature range, −40°C to +105°C.

ING_P and CHx_GAIN_SCALING_N, in the CHx_GAIN register.

2 CHx _ G A IN _ SC AL I NG _ P

2 C Hx _ G AI N _ SC A LI N G _ N

which RFBx_y pin is connected, as shown in Table 9. Table 9. Value of Resistors on RFBx_y pins Table 10. Mapping of Offset Value register allows moving the range up or down by 25% of its span. can be shifted by ±2.5 V using the offset register and polarity bit. the Custom Output Voltage Span section. to the noninverting input of the TIA, nominally 2.5 V. RFB is according to the definition given in Table 9. Table 11. Voltage Reference Selection

00 Internal Floating

10 External Input

11 External Input

on CS enables the digital interface and initiates an SPI transaction.

regions of memory (for example, during initial device configuration). The AD3551R is configured in streaming mode by default. the address direction setting) after each byte of data is accessed. address direction, respectively). data phase starts transferring the most significant byte in first place. must always be set as descending. access depending on the register address. until it reaches the top of the addressable space (Address 0x4B). On the subsequent byte access, the address is reset to 0x00. than 0x29 do not update in ascending mode. within the same transaction, which is useful for waveform playback. Table 12. Stream Mode Autoreset

0 Autoreset

1 Keeps previous value

Figure 73. Streaming Mode Register Write with Address Descending

Table 15. DAC Update Modes Quad, Dual and Single SPI CH0_INPUT Falling edge Yes LDAC mask applied, HW_LDAC register. Quad, Dual and Single SPI CH0_INPUT High No Write to SW_LDAC triggers the update. Quad, Dual and Single SPI CH0_INPUT Low No Output updates automatically. Quad, Dual and Single SPI CH0_DAC Not applicable No Output updates immediately. down after reset and becomes active on the first update. The AD3551R implements three different ways to reset the device. cept for the difference explained in the Software Reset section. outputs to 0 V, and keeping the SPI lines in high impedance. IOUTx and VCMx outputs are still at 0 V. the sequencing of the supplies. reset and in case of initialization failure. Table 16. Alarm Mask Register and Corresponding Error Source

6 REF_RANGE_ALARM_MASK ERR_STATUS REF_RANGE_ERR_STATUS

5 CLOCK_COUNT_ALARM_MASK INTERFACE_STATUS_A CLOCK_COUNTING_ERROR

4 MEM_CRC_ALARM_MASK ERR_STATUS MEM_CRC_ERR_STATUS

3 SPI_CRC_ERR_ALARM_MASK INTERFACE_STATUS_A INVALID_OR_NO_CRC

2 WRITE_TO_READ_ONLY_ALARM_MASKINTERFACE_STATUS_A WRITE_TO_READ_ONLY_REGISTER

1 PARTIAL_REGISTER_ACCESS_ALARM_MASKINTERFACE_STATUS_A PARTIAL_REGISTER_ACCESS

0 REGISTER_ADDRESS_INVALID_ALARM_MASKINTERFACE_STATUS_A REGISTER_ADDRESS_INVALID

when the internal reference is shared with another device. MEM_CRC_ERR_STATUS bit is set in the ERR_STATUS register. It is advisable to reset the device if this error occurs. power-up to be able to detect new events via the ALERT signal. know when the device is ready to receive data from the controller. CLOCK_COUNTING_ERR bit is set in the ERR_STATUS register. Valid combinations are shown in Table 17. Table 17. Clock Cycles Required to Transfer One Byte WRITE_TO_READ_ONLY_REGISTER bit. error, write 1 to the PARTIAL_REGISTER_ ACCESS bit. TUS_A register. To clear this error, write 1 to this bit. for the CPU to take action when an error condition arises.

Table 18. Register Summary

Table 19. Detailed Register Summary

Table 19. Detailed Register Summary (Continued)

Interface configuration settings. Table 20. Bit Descriptions for INTERFACE_CONFIG_A register) to the default power-up state.

1 Initiates a software reset if the SW_RESET_LSB bit is also set to 1 in the same

each data byte when streaming or addressing multibyte registers. each data byte when streaming or addressing multibyte registers. register) to the default power-up state.

Additional interface configuration settings. Table 21. Bit Descriptions for INTERFACE_CONFIG_B This register is intended for compatibility with the standardized register map and it has no effect on this device. Table 22. Bit Descriptions for DEVICE_CONFIG

conjunction with the product ID to uniquely identify the AD3551R. Table 23. Bit Descriptions for CHIP_TYPE Table 24. Bit Descriptions for PRODUCT_ID_L High byte of the product ID. Table 25. Bit Descriptions for PRODUCT_ID_H

version of the test procedure. Table 26. Bit Descriptions for CHIP_GRADE This register has no functional purpose. It is provided to test write and read operations. Table 27. Bit Descriptions for SCRATCH_PAD Indicates the SPI interface revision. Table 28. Bit Descriptions for SPI_REVISION

Table 29. Bit Descriptions for VENDOR_L Table 30. Bit Descriptions for VENDOR_H Defines the length of the loop when streaming data. Table 31. Bit Descriptions for STREAM_MODE [7:0] LENGTH Data Byte Loop Count. Specifies the data byte count before looping back to the start address. wraps around at the upper and lower limits of memory.

This register configures the SPI mode used to transfer data and enables looping over the same register section when streaming data. Table 32. Bit Descriptions for TRANSFER_REGISTER

2 STREAM_LENGTH_KEEP_VALUE This bit controls the reset of the LENGTH bit field value in the

0 LENGTH bit field is reset to 0 at the end of the transaction. 1 LENGTH bit field keeps the same value. Additional interface configuration settings. Table 33. Bit Descriptions for INTERFACE_CONFIG_C transaction for the CRC status to be changed.

Table 33. Bit Descriptions for INTERFACE_CONFIG_C (Continued) complementary value of the CRC_ENABLE field. This register flags several error conditions related to SPI communication and register addressing. Table 34. Bit Descriptions for INTERFACE_STATUS_A be reset by writing a 1 to this bit). 0 Interface not ready error not detected. 1 Interface not ready error detected.

Table 34. Bit Descriptions for INTERFACE_STATUS_A (Continued) 0 Clock count error not detected. 1 Clock count error detected. can only be reset by writing a 1 to this bit). reset by writing a 1 to this bit). 1 Write to read-only register detected. be reset by writing a 1 to this bit). 0 Partial access error not detected. 1 Partial access error detected. 0 Invalid address error not detected. 1 Invalid address error detected. This register contains miscellaneous configuration bits affecting SPI communication and electrical parameters of digital signals.

Table 35. Bit Descriptions for INTERFACE_CONFIG_D 0 Internal pull-up disabled. An external pull-up is required. checking of the primary register set and the ROM memory. 0 Memory CRC checking disabled. 1 Memory CRC checking enabled. 01 Medium low SDIO drive strength. 10 Medium high SDIO drive strength. 11 High SDIO drive strength.

This register controls the source and driving of the voltage reference. Table 36. Bit Descriptions for REFERENCE_CONFIG buffer of the amplifier to allow for a greater gain bandwidth. configuration of the reference voltage circuit. 00 Reference voltage generated internally. The VREF pin is floating. 01 Reference voltage generated internally and output on the VREF pin. 10 Reference voltage provided externally and input on the VREF pin. 11 Reference voltage provided externally and input on the VREF pin. This register selects which error conditions cause the assertion of the ALERT pin. Table 37. Bit Descriptions for ERR_ALARM_MASK

Table 37. Bit Descriptions for ERR_ALARM_MASK (Continued) reference dipping below 2 V. the user writing to a read-only register. 1 PARTIAL_REGISTER_ACCESS_ALARM_MASK Partial Register Access Alarm Mask. 0 REGISTER_ADDRESS_INVALID_ALARM_MASK Register Address Invalid Alarm Mask. This register signals a combination of errors in the analog and digital domains. All the bits are sticky and can be cleared by writing 1. Table 38. Bit Descriptions for ERR_STATUS 6 REF_RANGE_ERR_STATUS Reference Alarm Error Status.

5 DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS Dual SPI Exceeds DAC Memory

4 MEM_CRC_ERR_STATUS Memory Map Background CRC

Table 38. Bit Descriptions for ERR_STATUS (Continued) cleared right after initialization. This register controls the individual power-down of the DAC channels. Table 39. Bit Descriptions for POWERDOWN_CONFIG 0 Channel 0 DAC in normal operating mode. 1 Channel 0 DAC is in power-down mode. the corresponding RFBx_0 resistor must be connected to obtain the expected result. Table 40. Bit Descriptions for CH0_OUTPUT_RANGE 000 0 V to 2.5 V range. Requires RFB1_0 connection.

Table 40. Bit Descriptions for CH0_OUTPUT_RANGE (Continued) 001 0 V to 5 V range. Requires RFB1_0 connection. 010 0 V to 10 V range. Requires RFB2_0 connection. 011 −5 V to +5 V range. Requires RFB2_0 connection. 100 −10 V to +10 V range. Requires RFB4_0 connection. Table 41. Bit Descriptions for CH0_OFFSET controls the polarity of the offset value. Table 42. Bit Descriptions for CH0_GAIN 0: Use preconfigured range settings. 1: Use custom range settings.

Table 42. Bit Descriptions for CH0_GAIN (Continued) This register controls the masking of the external LDAC signal to latch data into the DAC register. Table 43. Bit Descriptions for HW_LDAC_16B into the DAC register when the LDAC signal is asserted. 0 Data is latched in DAC Register 0 when the LDAC pin is asserted. This register contains the data currently played on DAC Channel 0. Table 44. Bit Descriptions for CH0_DAC_16B

This register is provided for compatibility with multichannel chips of this family. Table 45. Bit Descriptions for DAC_PAGE_16B copied into the DAC register if the SEL_CH0 bit is set in the CH_SELECT_16B register. This register is provided for compatibility with multichannel chips of this family. Table 46. Bit Descriptions for CH_SELECT_16B copied to the CH0_DAC_16B register. 1 Copy to corresponding register in Channel 0. This register is provided for compatibility with multichannel chips of this family. Table 47. Bit Descriptions for INPUT_PAGE_16B

Table 48. Bit Descriptions for SW_LDAC_16B Table 49. Bit Descriptions for CH0_INPUT_16B This register controls the masking of the external LDAC signal to latch data into the DAC register. Table 50. Bit Descriptions for HW_LDAC_24B into the DAC register when the LDAC signal is asserted. 0 Data is latched in DAC Register 0 when the LDAC pin is asserted.

This register contains the data currently played on DAC Channel 0. Table 51. Bit Descriptions for CH0_DAC_24B This register is provided for compatibility with multichannel chips of this family. Table 52. Bit Descriptions for DAC_PAGE_24B copied into the DAC register if the SEL_CH0 bit is set in the CH_SELECT_24B register. This register is provided for compatibility with multichannel chips of this family. Table 53. Bit Descriptions for CH_SELECT_24B copied to the CH0_DAC_24B register. 1 Copy to corresponding register in Channel 0.

This register is provided for compatibility with multichannel chips of this family. Table 54. Bit Descriptions for INPUT_PAGE_24B Table 55. Bit Descriptions for SW_LDAC_24B Table 56. Bit Descriptions for CH0_INPUT_24B

analog.com Rev. A | 58 of 59 and a decoupling capacitor between power and ground must be placed close to the via of the digital line.

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 93. 32-Lead Lead Frame Chip Package [LFCSP] 2 The EVAL-AD3552RFMC1Z and EVAL-AD3552RFMC2Z can be used to evaluate the AD3551R.