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Single Channel, 16-Bit, 16 MUPS, Multispan, Multi-IO SPI DAC Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►16-bit resolution ►16 MUPS single channel rate in fast mode ►11 MUPS single channel rate in precision mode ►78 ns small signal settling time to 0.1% accuracy ►100 ns large signal settling time to 0.1% accuracy ►Ultrasmall glitch: <50 pV×s ►Ultralow latency: 5 ns ►THD: −105 dB at 1 kHz ►Highly configurable output voltage span and offset ►1.2 V and 1.8 V logic level compatible ►Single (classic) and dual SPI modes ►Multiple error detectors, both analog and digital domains ►2.5 V internal voltage reference, 10 ppm/°C maximum tempera- ture coefficient ►Small package: 4 mm × 4 mm LFCSP

APPLICATIONS

►Instrumentation ►Hardware in the loop ►Process control equipment ►Medical devices ►Automated test equipment ►Data acquisition system ►Programmable voltage sources ►Optical communications GENERAL DESCRIPTION The AD3541R is a low drift, single channel, ultra-fast, 16-bit accu- racy, voltage output digital-to-analog converter (DAC) that can be configured in multiple voltage span ranges. The AD3541R operates with a fixed 2.5 V reference. The device incorporates three drift compensating feedback resis- tors for the internal transimpedance amplifier (TIA) that scales the output voltage. The AD3541R has five preconfigured output ranges: 0 V to 2.5 V, 0 V to 5 V, 0 V to 10 V, −5 V to +5 V, and −2.5 V to +7.5 V. The DAC can operate in fast mode for maximum speed or precision mode for maximum accuracy. The serial peripheral interface (SPI) can be configured in single SPI (classic SPI) mode or dual SPI mode with single date rate (SDR) or double data rate (DDR), with logical levels from 1.2 V to 1.8 V. To improve device robustness, cyclic redundancy check (CRC) can be enabled. Multiple error checkers have also been integrated to detect VREF failures or memory map corruption. The AD3541R is specified over the extended industrial temperature range (–40°C to +105°C). Table 1. Related Devices Figure 1. Functional Block Diagram with a wide scope and will be phased in as quickly as possible. Thank you for your patience.

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REVISION HISTORY

5/2022—Revision 0: Initial Version

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ELECTRICAL CHARACTERISTICS

PVSS ≤ 0 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Table 2. Electrical Characteristics

1 See the Terminology section. 2 Guaranteed by design and characterization, not production tested. 5 Reference temperature coefficient is calculated as per the box method. 6 Measured as current sourced from the PVSS pin.

and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Table 3. AC Characteristics

140 V/µs Full-scale step, all other ranges, −40 °C to +105 °C

1 See the Terminology section. and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Table 4. Timing Characteristics

Figure 8. Start-Up Sequence Timing

TA = 25°C, unless otherwise noted. Table 5. Absolute Maximum Ratings ing conditions for extended periods may affect product reliability. θJA is the natural convection junction to ambient thermal resistance. dependent on the test board and test environment. Table 6. Thermal Resistance1 1 Simulation values on JEDEC 2S2P board, still air (0 m/sec airflow). damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 9. Pin Configuration Table 7. Pin Function Descriptions 1 DVDD S Digital Core Power Supply. 1.8 V ± 5%. 2 VLOGIC S Digital Interface Power Supply. 1.2 V to 1.8 V. 3 CS DI Chip Select, Active Low Logic Input. This is the frame synchronization signal for the input data. 4 SCLK DI Serial Clock Input. 5 SDI/SDIO0 DI/O Serial Data Input in Classic SPI Mode. Serial Bidirectional Input/Output Bit 0 in Dual SPI Mode. 6 SDO/SDIO1 DI/O Serial Data Output in Classic SPI Mode. Serial Bidirectional Input/Output Bit 1 in Dual SPI Mode. updates when new data is written to the input register. in the mask register. This pin has an internal configurable pull-up resistor. 10, 26 AGND S Analog Ground Reference. It is recommended to connect DGND and AGND to the same ground plane under the device. 11 to 15, 28DNC Do Not Connect. Leave these pins floating. 16 PVDD S Positive Supply Voltage for Output Amplifier. 17 AVDD S Analog Power Supply. 5 V ± 5%. 18 VREF AI/O Voltage Reference, 2.5 V. Input when using the external reference, and output or floating when using the internal reference. 19 CVREF AI/O Decoupling Capacitor for Internal Reference, Optional. 20 VOUT0 AI/O Analog Output Voltage for Channel 0. 21 RFB4_0 AI/O Hardware Gain Selection for Channel 0, Gain = 4. 22 RFB2_0 AI/O Hardware Gain Selection for Channel 0, Gain = 2. 23 RFB1_0 AI/O Hardware Gain Selection for Channel 0, Gain = 1. 25 PVSS S Negative Rail for Output Amplifier. 27 DGND S Digital Ground Reference. It is recommended to connect DGND and AGND to the same ground plane under the device. 1 S = supply, DI = digital input, DO = digital output, and AI/O = analog input/output.

Table 9. Voltage Reference Selection

00 Internal Floating

10 External Input

11 External Input

on CS enables the digital interface and initiates an SPI transaction. given in the Timing Characteristics section. Single Instruction Mode section and the Streaming Mode section. instruction, whereas setting R/W high initiates a read instruction. selecting and using these modes. registers depending on the selected registers and access modes. affect the read and write data in the data phase. explained in the Multibyte Registers section. shifting out on the first SCLK edge of the data phase. Figure 71. Basic SPI Write Frame Figure 72. Basic SPI Read Frame in adjacent addresses and are referred to as multibyte registers. bytes or 3 bytes, respectively.

regions of memory (for example, during initial device configuration). The AD3541R is configured in streaming mode by default. the address direction setting) after each byte of data is accessed. address direction, respectively). data phase starts transferring the most significant byte in first place. must always be set as descending. access depending on the register address. until it reaches the top of the addressable space (Address 0x48). On the subsequent byte access, the address is reset to 0x00. than 0x28 do not update in ascending mode. specified in the address phase. An example is shown in Figure 78. bit in the TRANSFER_REGISTER, as shown in Table 10. Table 10. Stream Mode Autoreset

0 Autoreset

1 Keeps previous value

Figure 76. Streaming Mode Register Write with Address Descending Figure 77. Streaming Mode Register Read with Looping Disabled

Figure 78. Looping Enabled with STREAM_MODE = 2

conditions for Address 0x00. which is that DDR is disabled. controller (write) or by the AD3541R (read), as shown in Figure 81. unused or reserved registers. Figure 81. Dual SPI Transaction with CRC

registers is summarized in Figure 87. Figure 87. DAC Data Flow Between Registers Table 13. DAC Update Modes

leaving the output amplifier on. core and the output amplifier. The AD3541R implements three different ways to reset the device. cept for the difference explained in the Software Reset section. DACs are in power-down mode and the VOUT0 output is still at 0 V. on the sequencing of the supplies. reset and in case of initialization failure. Table 14. Alarm Mask Register and Corresponding Error Source

6 REF_RANGE_ALARM_MASK ERR_STATUS REF_RANGE_ERR_STATUS

5 CLOCK_COUNT_ALARM_MASK INTERFACE_STATUS_A CLOCK_COUNTING_ERROR

4 MEM_CRC_ALARM_MASK ERR_STATUS MEM_CRC_ERR_STATUS

3 SPI_CRC_ERR_ALARM_MASK INTERFACE_STATUS_A INVALID_OR_NO_CRC

2 WRITE_TO_READ_ONLY_ALARM_MASKINTERFACE_STATUS_A WRITE_TO_READ_ONLY_REGISTER

1 PARTIAL_REGISTER_ACCESS_ALARM_MASKINTERFACE_STATUS_A PARTIAL_REGISTER_ACCESS

0 REGISTER_ADDRESS_INVALID_ALARM_MASKINTERFACE_STATUS_A REGISTER_ADDRESS_INVALID

when the internal reference is shared with another device. MEM_CRC_ERR_STATUS bit is set in the ERR_STATUS register. It is advisable to reset the device if this error occurs. power-up to be able to detect new events via the ALERT signal. know when the device is ready to receive data from the controller. CLOCK_COUNTING_ERR bit is set in the ERR_STATUS register. Valid combinations are shown in Table 15. Table 15. Clock Cycles Required to Transfer One Byte WRITE_TO_READ_ONLY_REGISTER bit. error, write 1 to the PARTIAL_REGISTER_ ACCESS bit. TUS_A register. To clear this error, write 1 to this bit. for the CPU to take action when an error condition arises.

BLE_PULLUP bit in the INTERFACE_CONFIG_D register. their corresponding registers. modes and the restrictions on specific registers or memory regions. the registers being accessed. Figure 88. Register Access Modes

Table 16. Register Summary

Table 17. Detailed Register Summary

Interface configuration settings. Table 18. Bit Descriptions for INTERFACE_CONFIG_A register) to the default power-up state.

1 Initiates a software reset if the SW_RESET_LSB bit is also set to 1 in the same

each data byte when streaming or addressing multibyte registers. each data byte when streaming or addressing multibyte registers. register) to the default power-up state.

Additional interface configuration settings. Table 19. Bit Descriptions for INTERFACE_CONFIG_B This register is intended for compatibility with the standardized register map and it has no effect on this device. Table 20. Bit Descriptions for DEVICE_CONFIG

conjunction with the product ID to uniquely identify the AD3541R. Table 21. Bit Descriptions for CHIP_TYPE Table 22. Bit Descriptions for PRODUCT_ID_L High byte of the product ID. Table 23. Bit Descriptions for PRODUCT_ID_H

version of the test procedure. Table 24. Bit Descriptions for CHIP_GRADE This register has no functional purpose. It is provided to test write and read operations. Table 25. Bit Descriptions for SCRATCH_PAD Indicates the SPI interface revision. Table 26. Bit Descriptions for SPI_REVISION

Table 27. Bit Descriptions for VENDOR_L Table 28. Bit Descriptions for VENDOR_H Defines the length of the loop when streaming data. Table 29. Bit Descriptions for STREAM_MODE [7:0] LENGTH Data Byte Loop Count. Specifies the data byte count before looping back to the start address. wraps around at the upper and lower limits of memory.

This register configures the SPI mode used to transfer data and enables looping over the same register section when streaming data. Table 30. Bit Descriptions for TRANSFER_REGISTER

2 STREAM_LENGTH_KEEP_VALUE This bit controls the reset of the LENGTH bit field value in the

0 LENGTH bit field is reset to 0 at the end of the transaction. 1 LENGTH bit field keeps the same value. Additional interface configuration settings. Table 31. Bit Descriptions for INTERFACE_CONFIG_C transaction for the CRC status to be changed.

complementary value of the CRC_ENABLE field. This register flags several error conditions related to SPI communication and register addressing. Table 32. Bit Descriptions for INTERFACE_STATUS_A be reset by writing a 1 to this bit). 0 Interface not ready error not detected. 1 Interface not ready error detected.

0 Clock count error not detected. 1 Clock count error detected. can only be reset by writing a 1 to this bit). reset by writing a 1 to this bit). 1 Write to read-only register detected. be reset by writing a 1 to this bit). 0 Partial access error not detected. 1 Partial access error detected. 0 Invalid address error not detected. 1 Invalid address error detected.

This register contains miscellaneous configuration bits affecting SPI communication and electrical parameters of digital signals. Table 33. Bit Descriptions for INTERFACE_CONFIG_D 0 Internal pull-up disabled. An external pull-up is required. checking of the primary register set and the ROM memory. 0 Memory CRC checking disabled. 1 Memory CRC checking enabled. 01 Medium low SDIO drive strength. 10 Medium high SDIO drive strength. 11 High SDIO drive strength.

This register controls the source and driving of the voltage reference. Table 34. Bit Descriptions for REFERENCE_CONFIG buffer of the amplifier to allow for a greater gain bandwidth. configuration of the reference voltage circuit. 00 Reference voltage generated internally. The VREF pin is floating. 01 Reference voltage generated internally and output on the VREF pin. 10 Reference voltage provided externally and input on the VREF pin. 11 Reference voltage provided externally and input on the VREF pin. This register selects which error conditions cause the assertion of the ALERT pin. Table 35. Bit Descriptions for ERR_ALARM_MASK

reference dipping below 2 V. the user writing to a read-only register. 1 PARTIAL_REGISTER_ACCESS_ALARM_MASK Partial Register Access Alarm Mask. 0 REGISTER_ADDRESS_INVALID_ALARM_MASK Register Address Invalid Alarm Mask. This register signals a combination of errors in the analog and digital domains. All the bits are sticky and can be cleared by writing 1. Table 36. Bit Descriptions for ERR_STATUS 6 REF_RANGE_ERR_STATUS Reference Alarm Error Status.

5 DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS Dual SPI Exceeds DAC Memory

4 MEM_CRC_ERR_STATUS Memory Map Background CRC

cleared right after initialization. This register controls the individual power-down of the DAC channels. Table 37. Bit Descriptions for POWERDOWN_CONFIG 0 Channel 0 DAC in normal operating mode. 1 Channel 0 DAC is in power-down mode. 0 Channel 0 output amplifier is powered on. 1 Channel 0 output amplifier is in power-down mode. the corresponding RFBx_0 resistor must be connected to obtain the expected result. Table 38. Bit Descriptions for CH0_OUTPUT_RANGE

000 0 V to 2.5 V range. Requires RFB1_0 connection. 001 0 V to 5 V range. Requires RFB1_0 connection. 010 0 V to 10 V range. Requires RFB2_0 connection. 011 −5 V to +5 V range. Requires RFB2_0 connection. 100 −2.5 V to +7.5 V range. Requires RFB2_0 connection. This register controls the masking of the external LDAC signal to latch data into the DAC register. Table 39. Bit Descriptions for HW_LDAC_16B into the DAC register when the LDAC signal is asserted. 0 Data is latched in DAC Register 0 when the LDAC pin is asserted. This register contains the data currently played on DAC Channel 0. Table 40. Bit Descriptions for CH0_DAC_16B This register is provided for compatibility with multichannel chips of this family.

Table 41. Bit Descriptions for DAC_PAGE_16B copied into the DAC register if the SEL_CH0 bit is set in the CH_SELECT_16B register. This register is provided for compatibility with multichannel chips of this family. Table 42. Bit Descriptions for CH_SELECT_16B copied to the CH0_DAC_16B register. 1 Copy to corresponding register in Channel 0. This register is provided for compatibility with multichannel chips of this family. Table 43. Bit Descriptions for INPUT_PAGE_16B

Table 44. Bit Descriptions for SW_LDAC_16B Table 45. Bit Descriptions for CH0_INPUT_16B This register controls the masking of the external LDAC signal to latch data into the DAC register. Table 46. Bit Descriptions for HW_LDAC_24B into the DAC register when the LDAC signal is asserted. 0 Data is latched in DAC Register 0 when the LDAC pin is asserted.

This register contains the data currently played on DAC Channel 0. Table 47. Bit Descriptions for CH0_DAC_24B This register is provided for compatibility with multichannel chips of this family. Table 48. Bit Descriptions for DAC_PAGE_24B copied into the DAC register if the SEL_CH0 bit is set in the CH_SELECT_24B register. This register is provided for compatibility with multichannel chips of this family. Table 49. Bit Descriptions for CH_SELECT_24B copied to the CH0_DAC_24B register. 1 Copy to corresponding register in Channel 0.

This register is provided for compatibility with multichannel chips of this family. Table 50. Bit Descriptions for INPUT_PAGE_24B Table 51. Bit Descriptions for SW_LDAC_24B Table 52. Bit Descriptions for CH0_INPUT_24B

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 91. 28-Lead Lead Frame Chip Package [LFCSP] 2 The EVAL-AD3542RFMCZ can be used to evaluate AD3541R.