AD3421QRWERQ1

ADC3421-Q1 TI1 | Alldatasheet

Document overview

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Technical content

Frequency (MHz) Amplitude (dBFS) 0 2.5 5 7.5 10 12.5 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 D802 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC3421-Q1 SBAS958 – DECEMBER 2019 ADC3421-Q1Automotive,Quad-Channel,12-Bit,25-MSPSAnalog-to-DigitalConverter

1 Features

1• AEC-Q100 Qualified for automotive applications – Temperature grade 1: –40°C to 125°C TA

• Quad channel
• 12-Bit resolution
• Single supply: 1.8 V
• Serial LVDS interface
• Flexible input clock buffer with divide-by-1, -2, -4
• SNR = 71.1 dBFS, SFDR = 90 dBc at fIN = 10 MHz
• Ultra-low power consumption: – 44 mW/Ch at 25 MSPS
• Channel isolation: 105 dB
• Internal dither and chopper
• Support for multichip synchronization

2 Applications

• Solid state LiDAR
• Motor control feedback
• Nondestructive testing
• Radar and smart antenna arrays
• Munitions guidance

3 Description

The ADC3421-Q1 is an automotive-grade, high- linearity, ultra-low power, quad-channel, 12-bit, 25- MSPS analog-to-digital converter (ADC). The device is designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider gives more flexibility for system clock architecture design, and the SYSREF input enables complete system synchronization. The ADC3421-Q1 supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) ADC3421-Q1 VQFNP (56) 8.00 mm × 8.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Spectrum at 10-MHz IF SFDR = 90 dBc, SNR = 71.2 dBFS, SINAD = 71.1 dBFS, THD = 89 dBc

SBAS958 – DECEMBER 2019 www.ti.com Product Folder Links: ADC3421-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Table of Contents

12.1 Receiving Notification of Documentation Updates 58

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES December 2019 * Initial release.

56 DB0M15AVDD

55 DB0P16SCLK

54 DB1M17SDATA

53 DB1P18SEN

52 DVDD19SDOUT

51 DCLKM20AVDD

50 DCLKP21CLKM

49 FCLKM22CLKP

48 FCLKP23AVDD

47 DVDD24RESET

46 DC0M25SYSREFP

45 DC0P26SYSREFM

44 DC1M27VCM

43 DC1P28AVDD

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5 Pin Configuration and Functions

SBAS958 – DECEMBER 2019 www.ti.com Product Folder Links: ADC3421-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Pin Functions PIN I/O DESCRIPTION NAME NO. AVDD 6, 7, 10, 11, 14, 32, 33, 36 I Analog 1.8-V power supply CLKM 21 I Negative differential clock input for the ADC CLKP 22 I Positive differential clock input for the ADC DA0M 4 O Negative serial LVDS output for wire-0 of channel A DA0P 3 O Positive serial LVDS output for wire-0 of channel A DA1M 2 O Negative serial LVDS output for wire-1 of channel A DA1P 1 O Positive serial LVDS output for wire-1 of channel A DB0M 56 O Negative serial LVDS output for wire-0 of channel B DB0P 55 O Positive serial LVDS output for wire-0 of channel B DB1M 54 O Negative serial LVDS output for wire-1 of channel B DB1P 53 O Positive serial LVDS output for wire-1 of channel B DC0M 46 O Negative serial LVDS output for wire-0 of channel C DC0P 45 O Positive serial LVDS output for wire-0 of channel C DC1M 44 O Negative serial LVDS output for wire-1 of channel C DC1P 43 O Positive serial LVDS output for wire-1 of channel C DD0M 42 O Negative serial LVDS output for wire-0 of channel D DD0P 41 O Positive serial LVDS output for wire-0 of channel D DD1M 40 O Negative serial LVDS output for wire-1 of channel D DD1P 39 O Positive serial LVDS output for wire-1 of channel D DCLKM 51 O Negative bit clock output DCLKP 50 O Positive bit clock output DVDD 5, 38, 47, 52 I Digital 1.8-V power supply FCLKM 49 O Negative frame clock output FCLKP 48 O Positive frame clock output INAM 8 I Negative differential analog input for channel A INAP 9 I Positive differential analog input for channel A INBM 13 I Negative differential analog input for channel B INBP 12 I Positive differential analog input for channel B INCM 30 I Negative differential analog input for channel C INCP 31 I Positive differential analog input for channel C INDM 35 I Negative differential analog input for channel D INDP 34 I Positive differential analog input for channel D PDN 37 I Power-down control. This pin can be configured using the SPI. This pin has an internal 150-kΩ pulldown resistor. RESET 24 I Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor. SCLK 16 I Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor. SDATA 17 I Serial interface data input. This pin has an internal 150-kΩ pulldown resistor. SDOUT 19 O Serial interface data output SEN 18 I Serial interface enable; active low. This pin has an internal 150-kΩ pullup resistor to AVDD. SYSREFM 26 I Negative external SYSREF input SYSREFP 25 I Positive external SYSREF input VCM 27 O Common-mode voltage for analog inputs Thermal Pad — — Connect thermal pad to ground.

www.ti.com SBAS958 – DECEMBER 2019 Product Folder Links: ADC3421-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Analog supply voltage range, AVDD –0.3 2.1 V Digital supply voltage range, DVDD –0.3 2.1 V Voltage applied to input pins INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM –0.3 min (1.9, AVDD + 0.3) V CLKP, CLKM –0.3 AVDD + 0.3 SYSREFP, SYSREFM –0.3 AVDD + 0.3 SCLK, SEN, SDATA, RESET, PDN –0.3 3.9 Temperature Operating junction, TJ 150 ºC Storage, Tstg –65 150 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) HBM ESD Classification Level 2 ±2000 V Charged-device model (CDM), per AEC Q100-011 CDM ESD Classification Level C5 ±750 (1) After power-up, use only the RESET pin to reset the device for the first time; see the Register Initialization section for details. (2) See Table 1 for details.

6.3 Recommended Operating Conditions(1)

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supplies AVDD Analog supply voltage range 1.7 1.8 1.9 V DVDD Digital supply voltage range 1.7 1.8 1.9 V Analog Input VID Differential input voltage For input frequencies < 450 MHz 2 VPP For input frequencies < 600 MHz 1 VIC Input common-mode voltage VCM ± 0.025 V Clock Input Input clock frequency Sampling clock frequency 15(2) 25 MSPS Input clock amplitude (differential) Sine wave, ac-coupled 0.2 1.5 VPPLPECL, ac-coupled 1.6 LVDS, ac-coupled 0.7 Input clock duty cycle 35% 50% 65% Input clock common-mode voltage 0.95 V Digital Outputs CLOAD Maximum external load capacitance from each output pin to GND 3.3 pF RLOAD Single-ended load resistance 100 Ω Temperature TJ Operating Junction Temperature –40 125 °C

SBAS958 – DECEMBER 2019 www.ti.com Product Folder Links: ADC3421-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) ADC3421-Q1 UNITRWE (VQFNP)

56 PINS

RθJA Junction-to-ambient thermal resistance 20.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 8.8 °C/W RθJB Junction-to-board thermal resistance 5.6 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 5.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 °C/W (1) Crosstalk is measured with a –1-dBFS input signal on the aggressor channel and no input on the victim channel.

6.5 Electrical Characteristics: General

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 125°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC clock frequency 25 MSPS Resolution 12 Bits 1.8-V analog supply current 54 71 mA 1.8-V digital supply current 45 71 mA Total power dissipation 177 240 mW Global power-down dissipation 5 17 mW Standby power-down dissipation 34 75 mW Analog Input Differential input full-scale 2.0 VPP ri Input resistance Differential at dc 6.6 kΩ ci Input capacitance Differential at dc 3.7 pF VOC(VCM) VCM common-mode voltage output 0.95 V VCM output current capability 10 mA Input common-mode current Per analog input pin 1.5 µA/MSPS Analog input bandwidth (3 dB) 50-Ω differential source driving 50-Ω termination across INP and INM 540 MHz DC accuracy EO Offset error –25 25 mV αEO Temperature coefficient of offset error ± 0.024 mV/°C EG(REF) Gain error as a result of internal reference inaccuracy alone –2 2 %FS EG(CHAN) Gain error of channel alone –2 %FS α(EGCHAN) Temperature coefficient of EG(CHAN) ±0.008 Δ%FS/Ch Channel-to-channel Isolation Crosstalk(1) fIN = 10 MHz Near channel 105 dB Far channel 105 fIN = 100 MHz Near channel 95 Far channel 105 fIN = 200 MHz Near channel 94 Far channel 105 fIN = 230 MHz Near channel 92 Far channel 105 fIN = 300 MHz Near channel 85 Far channel 105

www.ti.com SBAS958 – DECEMBER 2019 Product Folder Links: ADC3421-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Reported from a 1-MHz offset.

6.6 Electrical Characteristics: AC Performance

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 125°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS DITHER ON DITHER OFF UNIT MIN TYP MAX MIN TYP MAX SNR Signal-to-noise ratio (from 1-MHz offset) fIN = 10 MHz 70.9 71.1 dBFS fIN = 20 MHz 68.9 70.7 70.9 fIN = 70 MHz 70.4 70.6 fIN = 100 MHz 70.3 70.5 fIN = 170 MHz 69.7 69.9 fIN = 230 MHz 68.9 69.1 Signal-to-noise ratio (full Nyquist band) fIN = 10 MHz 70.2 70.5 dBFS fIN = 20 MHz 70.1 70.3 fIN = 70 MHz 69.8 70.0 fIN = 100 MHz 69.6 69.8 fIN = 170 MHz 69.2 69.3 fIN = 230 MHz 68.3 68.5 NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –141.5 –141.7 dBFS/Hz fIN = 20 MHz –141.3 –139.5 –141.5 fIN = 70 MHz –141.0 –141.2 fIN = 100 MHz –140.9 –141.1 fIN = 170 MHz –140.3 –140.5 fIN = 230 MHz –139.5 –139.7 SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 71 71.1 dBFS fIN = 20 MHz 67.9 70.8 70.9 fIN = 70 MHz 69.5 70 fIN = 100 MHz 70.5 70.7 fIN = 170 MHz 69.6 69.8 fIN = 230 MHz 68.7 68.7 ENOB(1) Effective number of bits fIN = 10 MHz 11.5 11.5 Bits fIN = 20 MHz 11 11.4 11.4 fIN = 70 MHz 11.4 11.4 fIN = 100 MHz 11.4 11.4 fIN = 170 MHz 11.3 11.3 fIN = 230 MHz 11.1 11.1 SFDR Spurious-free dynamic range fIN = 10 MHz 93 90 dBc fIN = 20 MHz 84 91 85 fIN = 70 MHz 93 88 fIN = 100 MHz 85 82 fIN = 170 MHz 86 85 fIN = 230 MHz 82 82

SBAS958 – DECEMBER 2019 www.ti.com Product Folder Links: ADC3421-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Electrical Characteristics: AC Performance (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 125°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS DITHER ON DITHER OFF UNIT MIN TYP MAX MIN TYP MAX HD2 Second-order harmonic distortion fIN = 10 MHz 93 92 dBc fIN = 20 MHz 83 100 94 fIN = 70 MHz 93 92 fIN = 100 MHz 94 93 fIN = 170 MHz 86 85 fIN = 230 MHz 86 82 HD3 Third-order harmonic distortion fIN = 10 MHz 96 90 dBc fIN = 20 MHz 82 91 85 fIN = 70 MHz 93 88 fIN = 100 MHz 85 82 fIN = 170 MHz 89 89 fIN = 230 MHz 82 82 Non HD2, HD3 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 92 dBc fIN = 20 MHz 86 98 91 fIN = 70 MHz 96 92 fIN = 100 MHz 95 93 fIN = 170 MHz 92 90 fIN = 230 MHz 97 91 THD Total harmonic distortion fIN = 10 MHz 90 86 dBc fIN = 20 MHz 78 90 83 fIN = 70 MHz 89 85 fIN = 100 MHz 84 80 fIN = 170 MHz 84 83 fIN = 230 MHz 80 79 IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz, fIN2 = 50 MHz –98 –98 dBFS fIN1 = 185 MHz, fIN2 = 190 MHz –91 –91

www.ti.com SBAS958 – DECEMBER 2019 Product Folder Links: ADC3421-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) SEN has an internal 150-kΩ pullup resistor to AVDD. SPI pins (SEN, SCLK, SDATA) can be driven by 1.8 V or 3.3 V CMOS buffers.

6.7 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital Inputs (RESET, SCLK, SDATA, SEN, PDN) VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels 1.3 V VIL Low-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels 0.4 V IIH High-level input current RESET, SDATA, SCLK, PDN VHIGH = 1.8 V 10 µA SEN(1) VHIGH = 1.8 V 0 µA IIL Low-level input current RESET, SDATA, SCLK, PDN VLOW = 0 V 0 µA SEN VLOW = 0 V 10 µA DigitaL Inputs (SYSREFP, SYSREFM) VIH High-level input voltage 1.3 V VIL Low-level input voltage 0.5 V Common-mode voltage for SYSREF 0.9 V Digital Outputs (CMOS Interface, SDOUT) VOH High-level output voltage DVDD – 0.1 DVDD V VOL Low-level output voltage 0 0.1 V Digital Outputs (LVDS Interface) VODH High-level output differential voltage With an external 100-Ω termination 280 350 460 mV VODL Low-level output differential voltage With an external 100-Ω termination –460 –350 –280 mV VOCM Output common-mode voltage 1.05 V (1) Overall latency = ADC latency + tPDI.

6.8 Timing Requirements: General

Typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 125°C. MIN TYP MAX UNIT tA Aperture delay 1.24 1.44 1.64 ns Aperture delay matching between two channels of the same device ±70 ps Aperture delay variation between two devices at same temperature and supply voltage ±150 ps tJ Aperture jitter 130 fS rms Wake-up time: Time to valid data after exiting standby power-down mode 35 200 µs Time to valid data after exiting global power-down mode (in this mode, both channels power down) 85 450 µs ADC latency(1): 2-wire mode (default) 9 Clock cycles 1-wire mode 8 Clock cycles tSU_SYSREF SYSREF reference time: Setup time for SYSREF referenced to input clock rising edge 1000 ps tH_SYSREF Hold time for SYSREF referenced to input clock rising edge 100 ps

SBAS958 – DECEMBER 2019 www.ti.com Product Folder Links: ADC3421-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. (2) Timing parameters are ensured by design and characterization and are not tested in production. (3) CLOAD is the effective external single-ended load capacitance between each output pin and ground. (4) RLOAD is the differential load resistance between the LVDS output pair. (5) Data valid refers to a logic high of 100 mV and a logic low of –100 mV. (6) Write relevant register settings as mentioned in Table 22.

6.9 Timing Requirements: LVDS Output(1)(2)

Typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, 6x Serialization (2-Wire Mode), CLOAD = 3.3 pF(3), and RLOAD = 100 Ω(4), unless otherwise noted.. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 125°C. MIN TYP MAX UNIT tSU Data setup time: data valid to zero-crossing of differential output clock (CLKOUTP – CLKOUTM)(5)(6) 1-wire mode 1.3 1.48 ns 2-wire mode 2.61 3.06 tHO Data hold time: zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data becoming invalid(5)(6) 1-wire mode 1.32 1.57 ns 2-wire mode 2.75 3.12 tPDI Clock propagation delay: input clock falling edge cross-over to frame clock rising edge cross-over (15 MSPS < sampling frequency < 25 MSPS) 1-wire mode 0.1 × tS + tDELAY ns 2-wire mode 0.61 × tS + tDELAY ns tDELAY Delay time 3 4.5 5.9 ns LVDS bit clock duty cycle: duty cycle of differential clock (CLKOUTP – CLKOUTM) 49% tFALL, tRISE Data fall time, data rise time: rise time measured from –100 mV to 100 mV, 15 MSPS ≤ Sampling frequency ≤ 25 MSPS 0.11 ns tCLKRISE, tCLKFALL Output clock rise time, output clock fall time: rise time measured from –100 mV to 100 mV, 15 MSPS ≤ Sampling frequency ≤ 25 MSPS 0.11 ns

6.10 Typical Characteristics

when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted). Figure 1. FFT for 10-MHz Input Signal (Dither On) Figure 2. FFT for 10-MHz Input Signal (Dither Off) Figure 3. FFT for 70-MHz Input Signal (Dither On) Figure 4. FFT for 70-MHz Input Signal (Dither Off) Figure 5. FFT for 170-MHz Input Signal (Dither On) Figure 6. FFT for 170-MHz Input Signal (Dither Off)

when chopper is disabled and from fS / 2 when chopper is enabled (unless otherwise noted). Figure 31. Integral Nonlinearity for a 20-MHz Input Figure 32. Differential Nonlinearity for a 20-MHz Input

7 Parameter Measurement Information

7.1 Timing Diagrams

(1) With an external 100-Ω termination. Figure 33. Serial LVDS Output Voltage Levels

by 1,2,4 INAP INAM 12-Bit ADC Digital Encoder and Serializer INDP INDM 12-Bit ADC INCP INCM 12-Bit ADC PLL 12-Bit ADC FCLKP FCLKM DCLKP DCLKM Bit Clock Frame Clock DC1P DC1M DD1P DD1M DC0P DC0M DD0P DD0M Digital Encoder and Serializer Digital Encoder and Serializer ADC3421-Q1 SBAS958 – DECEMBER 2019 www.ti.com Product Folder Links: ADC3421-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The ADC3421-Q1 is an automotive-grade, high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS analog- to-digital converter (ADC). The device is designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider gives more flexibility for system clock architecture design, and the SYSREF input enables complete system synchronization. The ADC3421-Q1 supports a serial low-voltage differential signaling (LVDS) interface in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Analog Inputs

termination between INP and INM).

8.3.2 Clock Input

in Figure 36, Figure 37, and Figure 38. See Figure 39 for details regarding the internal clock buffer. NOTE: RT = termination resistor, if necessary. Figure 36. Differential Sine-Wave Clock Driving Figure 37. LVDS Clock Driving Circuit Figure 38. LVPECL Clock Driving Circuit

NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer. Figure 39. Internal Clock Buffer a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. Figure 40. Single-Ended Clock Driving Circuit

8.3.2.1 SNR and Clock Jitter

sets SNR for higher input frequencies. The SNR limitation resulting from sample clock jitter can be calculated with Equation 2.

(1) Use the LOW SPEED ENABLE register bits for low speed operation; see . the noise of the clock input buffer and the external clock. TJitter can be calculated with Equation 3. jitter for different input frequencies, is shown in Figure 41. Figure 41. SNR vs Frequency for Different Clock Jitter

8.3.3 Digital Output Interface

• One-wire, 1x frame clock, 12x serialization with the DDR bit clock and
• Two-wire, 1x frame clock, 6x serialization with the DDR bit clock.

Table 1. Interface Rates

8.3.3.1 One-Wire Interface: 12x Serialization

8.3.3.2 Two-Wire Interface: 6x Serialization

and the six LSBs on Dx0P, Dx0M, as shown in Figure 42. Figure 42. Output Timing Diagram

8.4 Device Functional Modes

8.4.1 Input Clock Divider

system clock distribution design.

8.4.2 Chopper Functionality

creates a spur at fS / 2 that must be filtered out digitally. Figure 43. Chopper Off Figure 44. Chopper On

8.4.3 Power-Down Control

down or standby functionality, as shown in Table 2. Table 2. Power-Down Modes

8.4.4 Internal Dither Algorithm

Figure 45. FFT for 10-MHz Input Signal Figure 46. FFT for 10-MHz Input Signal

8.4.5 Summary of Performance Mode Registers

Table 3 lists the location, value, and functions of performance mode registers in the device. Table 3. Performance Modes

8.4.6 Device Diagnostic Modes

be enabled using the SPI. Outputs of these modes are stored in diagnostic read-only registers.

8.4.6.1 Internal Reference and Clock Status Check

1. First enable reference status check by setting register bit EN REF STATUS CHECK to ‘1’.
2. Read back register bits REF STATUS CHx on SDATA pin for desired channel (x = A, B, C or D).

8=NE=J?A = Í |5:J; F T§| J=1 /A=J = T§ = Í 5(J) J=1 ADC3421-Q1 www.ti.com SBAS958 – DECEMBER 2019 Product Folder Links: ADC3421-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

8.4.6.2 DC Input check

In this mode, an internally generated DC voltage can be forced by device to its analog inputs. Before forcing internal DC voltage, analog inputs must float. To enable forcing internal DC voltage, register bit EN DC FORCE must be set HIGH. Forced voltage is programmable by register bits DC FORCE[2:0], applied to all four channels together. In terms of output code, typical value of programmed DC voltage is given by equation mentioned below: Output code= 368 × DC FORCE[2:0] + 745. Output code is available on LVDS data outputs.

8.4.6.3 Mean and Variance Measurement

Mean and variance values of the ADC output can be analyzed using the on-chip statistical module available for individual channel for a programmable length of samples. These values are stored in register bits MEAN[11:0] and VAR[11:0] in 2s complement format. Equation for computing mean and variance values respectively are given below: Where S(n) is nth sample, N is total number of samples used for computation, programmed by register bits SAMPLES FOR STATS[1:0]. Follow steps mentioned below to read the mean and variance: 1. Enable Statistical Module by setting bit EN STATS to ‘1’. 2. Select desired channel through bits STATS CH SEL[1:0]. 3. Program number of samples, N, using register bits SAMPLES FOR STATS[1:0]. 4. Wait for at least 4N samples for module to compute and update the results. 5. Disable Statistical Module by resetting EN STATS bit to ‘0’. 6. Read back mean and variance values from register bits MEAN[11:0] and VAR[11:0]. These values are in 2s complement format.

8.4.6.4 Temperature Sensor

The device is equipped with a temperature sensor to measure internal junction temperature. The temperature sensor output is a 9-bit digital data available in 2s complement format directly representing temperature in degree Celsius units. Temperature data is internally updated every 1024×TCLK× 16 seconds where TCLK period of sampling clock in seconds. Follow the steps mentioned below to read temperature sensor’s output: 1. Enable temperature sensor by setting bits EN TEMP SENSE and EN TEMP SENSE CONV to ‘1’. 2. Wait for at least 1024 × TCLK× 16 seconds for temperature sensor to update the data. 3. Disable temperature sensor by resetting the bit EN TEMP SENSE to ‘0’. 4. Load temperature sensor's data to register bits TEMPDATA[8:0] by setting register bit EN TEMP DATA READOUT to '1'. 5. Readout 9-bit temperature data from register bits TEMPDATA[8:0] located in register addresses 10h and 11h.

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8.5 Programming

The ADC3421-Q1 can be configured using a serial programming interface, as described in this section.

8.5.1 Serial Interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

8.5.1.1 Register Initialization

1. Through a hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

8.5.1.1.1 Serial Register Write

1. Set the R/W bit to 0 (bit A15 of the 16-bit address),
2. Set bit A14 in the address field to 1,
3. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be
4. Write the 8-bit data that are latched in on the SCLK rising edge.

Figure 47 and Table 4 show the timing requirements for the serial register write operation. Figure 47. Serial Register Write Timing Diagram

Table 4. Serial Interface Timing(1)

8.5.1.1.2 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin.

1. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.
2. Set bit A14 in the address field to 1.
3. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.
4. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.
5. The external controller can latch the contents at the SCLK rising edge.
6. To enable register writes, reset the R/W register bit to 0.

the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 49. Figure 48. Serial Register Read Timing Diagram Figure 49. SDOUT Timing Diagram

8.5.2 Register Initialization

applying a high pulse on the RESET pin, as shown in Figure 50 and Table 5. Figure 50. Initialization of Serial Registers after Power-Up Table 5. Power-Up Timing

1. Through hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

8.6 Register Maps

Table 6. Register Map Summary

Table 6. Register Map Summary (continued)

8.6.1 Serial Register Description

8.6.1.1 Register 01h (address = 01h)

Figure 51. Register 01h Table 7. Register 01h Field Descriptions along with bits 5 and 3 of register 134h. improves by 0.2 dB at 70 MHz. along with bits 5 and 3 of register 434h. improves by 0.2 dB at 70 MHz. along with bits 5 and 3 of register 534h. improves by 0.2 dB at 70 MHz. along with bits 5 and 3 of register 234h. improves by 0.2 dB at 70 MHz.

8.6.1.2 Register 02h (address = 02h)

Figure 52. Register 02h Table 8. Register 02h Field Descriptions

8.6.1.3 Register 03h (address = 03h)

Figure 53. Register 03h Table 9. Register 03h Field Descriptions

0 ODD EVEN R/W 0h This bit selects the bit sequence on the output wires (in 2-wire

8.6.1.4 Register 04h (address = 04h)

Figure 54. Register 04h Table 10. Register 04h Field Descriptions

8.6.1.5 Register 05h (address = 05h)

Figure 55. Register 05h Table 11. Register 05h Field Descriptions 0 1W-2W R/W 0h This bit transmits output data on either one or two wires. 1 = Output data are transmitted on one wire (Dx0P, Dx0M).

8.6.1.6 Register 06h (address = 06h)

Figure 56. Register 06h Table 12. Register 06h Field Descriptions 1 TEST PATTERN EN R/W 0h This bit enables test pattern selection for the digital outputs. 0 RESET R/W 0h This bit applies a software reset.

8.6.1.7 Register 07h (address = 07h)

Figure 57. Register 07h Table 13. Register 07h Field Descriptions 0 OVR ON LSB R/W 0h This bit provides OVR information on the LSB bits.

8.6.1.8 Register 09h (address = 09h)

Figure 58. Register 09h Table 14. Register 09h Field Descriptions

1 ALIGN TEST PATTERN R/W 0h This bit aligns the test patterns across the outputs of both

0 DATA FORMAT R/W 0h This bit selects th digital output data format.

8.6.1.9 Register 0Ah (address = 0Ah)

Figure 59. Register 0Ah Table 15. Register 0Ah Field Descriptions

8.6.1.10 Register 0Bh (address = 0Bh)

Figure 60. Register 0Bh Table 16. Register 0Bh Field Descriptions programmed by the CUSTOM PATTERN register bits. 1000 = Deskew pattern: data are AAAh. programmed by the CUSTOM PATTERN register bits. 1000 = Deskew pattern: data are AAAh.

8.6.1.11 Register 0Eh (address = 0Eh)

Figure 61. Register 0Eh Table 17. Register 0Eh Field Descriptions

8.6.1.12 Register 0Fh (address = 0Fh)

Figure 62. Register 0Fh Table 18. Register 0Fh Field Descriptions

8.6.1.13 Register 10h (address = 10h)

Figure 63. Register 10h Table 19. Register 10h Field Descriptions internal reference for corresponding channel. See Internal Reference and Clock Status Check for details.

4 CLK STATUS Read

LSBs are available on address 11h bit 5:4. See Temperature Sensor for details of operation.

8.6.1.14 Register 11h (address = 11h)

Figure 64. Register 11h Table 20. Register 11h Field Descriptions

8.6.1.15 Register 13h (address = 13h)

Figure 65. Register 13h Table 21. Register 13h Field Descriptions

5 EN DC FORCE R/W 0h This Bit Enables internal DC voltage force diagnostic check

internal DC voltage through DC FORCE[2:0] bits.

4 EN STATS R/W 0h This bit enables inter Statistics Module for mean and variance

1-0 LOW SPEED ENABLE R/W 0h Enables low speed operation in 1-wire and 2-wire mode. Table 22. LOW SPEED ENABLE Register Settings across fS

8.6.1.16 Register 14h (address = 14h)

Figure 66. Register 14h

0 EN TEMP

Table 23. Register 14h Field Descriptions

6 EN TEMP SENS CONV R/W 0h This bit enables the temperature-to-digital conversion process of

sensor is enabled by setting EN TEMP SENSE bit to '1'.

5 EN TEMP SENSE R/W 0h This bit enables temperature sensor present inside device

2 EN TEMP DATA READOUT R/W 0h This bit places the 9-bit digital equivalent of temperature on

register bits TEMPDATA[8:0].

8.6.1.17 Register 15h (address = 15h)

Figure 67. Register 15h Table 24. Register 15h Field Descriptions

7 CHA PDN W 0h 0 = Normal operation

6 CHB PDN R/W 0h 0 = Normal operation

5 CHC PDN R/W 0h 0 = Normal operation

4 CHD PDN W 0h 0 = Normal operation

3 STANDBY R/W 0h The ADCs of both channels enter standby.

2 GLOBAL PDN R/W 0h 0 = Normal operation

0 CONFIG PDN PIN R/W 0h This bit configures the PDN pin as either a global power-down or

8.6.1.18 Register 16h (address = 16h)

Figure 68. Register 16h Table 25. Register 16h Field Descriptions

8.6.1.19 Register 17h (address = 17h)

Figure 69. Register 17h

Table 26. Register 17h Field Descriptions

8.6.1.20 Register 18h (address = 18h)

Figure 70. Register 18h Table 27. Register 18h Field Descriptions

8.6.1.21 Register 19h (address = 19h)

Figure 71. Register 19h Table 28. Register 19h Field Descriptions

8.6.1.22 Register 25h (address = 25h)

Figure 72. Register 25h Table 29. Register 25h Field Descriptions data output, bit clock, and frame clock).

8.6.1.23 Register 27h (address = 27h)

Figure 73. Register 27h Table 30. Register 27h Field Descriptions

8.6.1.24 Register 4Bh (address = 4Bh)

Figure 74. Register 4Bh Table 31. Register 4Bh Field Descriptions module for computation of mean and variance.

8.6.1.25 Register 11Dh (address = 11Dh)

Figure 75. Register 11Dh Table 32. Register 11Dh Field Descriptions

1 HIGH IF MODE0 Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

8.6.1.26 Register 122h (address = 122h)

Figure 76. Register 122h Table 33. Register 122h Field Descriptions 1 DIS CHOP CHA R/W 0h This bit disables the chopper. Set this bit to shift the 1/f noise floor at dc.

8.6.1.27 Register 134h (address = 134h)

Figure 77. Register 134h Table 34. Register 134h Field Descriptions 5 DIS DITH CHA R/W 0h Set this bit along with bits 7 and 6 of register 01h. improves by 0.2 dB at 70 MHz. 3 DIS DITH CHA R/W 0h Set this bit along with bits 7 and 6 of register 01h. improves by 0.2 dB at 70 MHz.

8.6.1.28 Register 139h (address = 139h)

Figure 78. Register 139h Table 35. Register 139h Field Descriptions

3 SP1 CHA R/W 0h This bit sets the special mode for best performance on channel

8.6.1.29 Register 21Dh (address = 21Dh)

Figure 79. Register 21Dh Table 36. Register 21Dh Field Descriptions

1 HIGH IF MODE1 R/W 0h Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

8.6.1.30 Register 222h (address = 222h)

Figure 80. Register 222h Table 37. Register 222h Field Descriptions 1 DIS CHOP CHD R/W 0h This bit disables the chopper. Set this bit to shift the 1/f noise floor at dc.

8.6.1.31 Register 234h (address = 234h)

Figure 81. Register 234h Table 38. Register 234h Field Descriptions 5 DIS DITH CHD R/W 0h Set this bit with bits 1 and 0 of register 01h. typically improves by 0.2 dB at 70 MHz. 3 DIS DITH CHD R/W 0h Set this bit with bits 1 and 0 of register 01h. typically improves by 0.2 dB at 70 MHz.

8.6.1.32 Register 239h (address = 239h)

Figure 82. Register 239h Table 39. Register 239h Field Descriptions

3 SP1 CHD R/W 0h This bit sets the special mode for best performance on channel

8.6.1.33 Register 308h (address = 308h)

Figure 83. Register 308h Table 40. Register 308h Field Descriptions to improve HD3 by a couple of dB for IF > 100 MHz.

8.6.1.34 Register 31Dh (address = 31Dh)

Figure 84. Register 31Dh Table 41. Register 31Dh Field Descriptions

7 HIGH IF MODE4 R/W 0h Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

1 HIGH IF MODE4 R/W 0h Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

8.6.1.35 Register 41Dh (address = 41Dh)

Figure 85. Register 41Dh Table 42. Register 41Dh Field Descriptions

1 HIGH IF MODE2 R/W 0h Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

8.6.1.36 Register 422h (address = 422h)

Figure 86. Register 422h Table 43. Register 422h Field Descriptions 1 DIS CHOP CHB R/W 0h This bit disables the chopper. Set this bit to shift the 1/f noise floor at dc.

8.6.1.37 Register 434h (address = 434h)

Figure 87. Register 434h Table 44. Register 434h Field Descriptions 5 DIS DITH CHB R/W 0h Set this bit with bits 5 and 4 of register 01h. improves by 0.2 dB at 70 MHz. 3 DIS DITH CHB R/W 0h Set this bit with bits 5 and 4 of register 01h. improves by 0.2 dB at 70 MHz.

8.6.1.38 Register 439h (address = 439h)

Figure 88. Register 439h Table 45. Register 439h Field Descriptions

3 SP1 CHB R/W 0h This bit sets the special mode for best performance on channel

8.6.1.39 Register 51Dh (address = 51Dh)

Figure 89. Register 51Dh Table 46. Register 51Dh Field Descriptions

1 HIGH IF MODE3 R/W 0h Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

8.6.1.40 Register 522h (address = 522h)

Figure 90. Register 522h Table 47. Register 522h Field Descriptions 1 DIS CHOP CHC R/W 0h This bit disables the chopper. Set this bit to shift the 1/f noise floor at dc.

8.6.1.41 Register 534h (address = 534h)

Figure 91. Register 534h Table 48. Register 534h Field Descriptions 5 DIS DITH CHC R/W 0h Set this bit with bits 3 and 2 of register 01h. typically improves by 0.2 dB at 70 MHz. 3 DIS DITH CHC R/W 0h Set this bit with bits 3 and 2 of register 01h. typically improves by 0.2 dB at 70 MHz.

8.6.1.42 Register 539h (address = 539h)

Figure 92. Register 539h Table 49. Register 539h Field Descriptions

3 SP1 CHC R/W 0h This bit sets the special mode for best performance on channel

8.6.1.43 Register 608h (address = 608h)

Figure 93. Register 608h Table 50. Register 608h Field Descriptions to improve HD3 by a couple of dB for IF > 100 MHz.

8.6.1.44 Register 61Dh (address = 61Dh)

Figure 94. Register 61Dh Table 51. Register 61Dh Field Descriptions

7 HIGH IF MODE5 R/W 0h Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

1 HIGH IF MODE5 R/W 0h Set all register bits belonging to HIGH IF MODE as logic HIGH

to improve HD3 by a couple of dB for IF > 100 MHz.

8.6.1.45 Register 70Ah (address = 70Ah)

Figure 95. Register 70Ah Table 52. Register 70Ah Field Descriptions

0 PDN SYSREF R/W 0h If the SYSREF pins are not used in the system, the SYSREF

buffer must be powered down by setting this bit.

8.6.1.46 Register 71Ah (address = 71Ah)

Figure 96. Register 71Ah Table 53. Register 71Ah Field Descriptions

9 Applications and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

Figure 98 show the impedance (Zin = Rin || Cin) across the ADC input pins. Figure 97. Differential Input Resistance, RIN Figure 98. Differential Input Capacitance, CIN

9.2 Typical Applications

9.2.1 Driving Circuit Design: Low Input Frequencies

Figure 99. Driving Circuit for Low Input Frequencies

9.2.1.1 Design Requirements

9.2.1.2 Detailed Design Procedure

with the series inductor (39 nH), this combination helps absorb the sampling glitches.

9.2.1.3 Application Curve

Figure 100 shows the performance obtained by using the circuit shown in Figure 99. Figure 100. Performance FFT at 10 MHz (Low Input Frequency)

9.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz

Figure 101. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz)

9.2.2.1 Design Requirements

See the Design Requirements section for further details.

9.2.2.2 Detailed Design Procedure

performance, as shown in Figure 101.

9.2.2.3 Application Curve

Figure 102 shows the performance obtained by using the circuit shown in Figure 101. Figure 102. Performance FFT at 170 MHz (Mid Input Frequency)

9.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz

Figure 103. Driving Circuit for High Input Frequencies (fIN > 230 MHz)

9.2.3.1 Design Requirements

See the Design Requirements section for further details.

9.2.3.2 Detailed Design Procedure

improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 103.

9.2.3.3 Application Curve

Figure 104 shows the performance obtained by using the circuit shown in Figure 103. Figure 104. Performance FFT at 450 MHz (High Input Frequency)

10 Power Supply Recommendations

requirements during device power-up. AVDD and DVDD can power up in any order.

11 Layout

11.1 Layout Guidelines

1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the

as shown in the reference layout of Figure 105 as much as possible.

1. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to
2. Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, the digital

must be matched in length to avoid skew among outputs.

1. At each power-supply pin (AVDD and DVDD), keep a 0.1-µF decoupling capacitor close to the device. A

capacitors can be kept close to the supply source.

11.2 Layout Example

Figure 105. Typical Layout of the ADC3421-Q1 Board

SBAS958 – DECEMBER 2019 www.ti.com Product Folder Links: ADC3421-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 20-Dec-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples AD3421QRWERQ1 PREVIEW VQFNP RWE 56 2000 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-3-260C-168 HR -40 to 125 AZ3421Q AD3421QRWETQ1 PREVIEW VQFNP RWE 56 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-3-260C-168 HR -40 to 125 AZ3421Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 20-Dec-2019 Addendum-Page 2 OTHER QUALIFIED VERSIONS OF ADC3421-Q1 :

• Catalog: ADC3421 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2019 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AD3421QRWERQ1 VQFNP RWE 56 2000 350.0 350.0 43.0 AD3421QRWETQ1 VQFNP RWE 56 250 213.0 191.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2019 Pack Materials-Page 2

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