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Low Cost, 14-Bit, Dual Channel Synchro/Resolver-to-Digital Converter Data Sheet AD2S44 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1989–2011 Analog Devices, Inc. All rights reserved.

FEATURES

32-lead DIL hybrid package 2.6 arc minute accuracy 14-bit resolution Built-in test Independent reference inputs High tracking rate

APPLICATIONS

Gimbal/gyro control systems Robotics Engine controllers Coordinate conversion Military servo control systems Fire control systems Avionic systems Antenna monitoring CNC machine tooling GENERAL DESCRIPTION The AD2S44 is a 14-bit dual channel, continuous tracking synchro/ resolver-to-digital converter. It has been designed specifically for applications where space, weight, and cost are at a premium. Each 32-lead hybrid device contains two independent Type II servo loop tracking converters. The ratiometric conversion technique employed provides excellent noise immunity and tolerance of long lead lengths. The core of each conversion is performed by state-of-the-art mono- lithic, integrated circuits manufactured by the Analog Devices, Inc., proprietary BiMOS II process, which combines the advantages of low power CMOS digital logic with bipolar linear circuits. The use of these ICs keeps the internal component count low and ensures high reliability. The built-in test (BIT) facility can be used in failsafe systems to provide an indication of whether the converter is tracking accurately. Each channel incorporates a high accuracy differential condi- tioning circuit for signal inputs providing more than 74 dB of common-mode rejection. Options are available for both synchro and resolver format inputs. The converter output is via a three-state transparent latch allowing data to be read without interruption of the converter operation. The A/B and OE control lines select the channel and present the digital position to the common data outputs. The AD2S44 also features independent reference inputs where different reference frequencies can be used for each channel. All components are 100% tested at −55°C, +25°C, and +125°C. Devices are processed to high reliability screening standards and receive further levels of testing and screening to ensure high levels of reliability. FUNCTIONAL BLOCK DIAGRAM AD2S44 REFERENCE CONDITIONER SYNCHRO/ RESOLVER CONDITIONER PHASE- SENSITIVE DETECTOR THREE- STATE OUTPUT LATCHES DB1 (MSB) TO DB14 (LSB) PHASE- SENSITIVE DETECTOR HIGH SPEED SIN/COS MULTIPLIER BUILT-IN TEST DETECTION ERROR AMP UP-DOWN COUNTER UP-DOWN COUNTER INTEGRATOR VCO VCOINTEGRATORERROR AMP HIGH SPEED SIN/COS MULTIPLIER SYNCHRO/ RESOLVER CONDITIONER REFERENCE CONDITIONER S3 (A) RHI (A) RLO (A) RHI (B) RLO (B) +VS –VS GND S4 (A) S1 (A) S2 (A) S3 (B) S4 (B) S1 (B) S2 (B) OE A/B BIT 02947-001 Figure 1.

AD2S44* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Application Notes

  • AN-214: Ground Rules for High Speed Circuits
  • AN-263: Resolver to Digital Conversion; Simple Alternative to Optical Shaft Encoders
  • AN-264: Dynamic Characteristics of Tracking Converter Data Sheet
  • AD2S44: Low Cost, 14-Bit, Dual Channel Synchro/ Resolver-to-Digital Converter Data Sheet REFERENCE MATERIALS Technical Articles
  • DSP Motor Control in Domestic Appliance Applications
  • Single Chip DSP Motor Control Systems Catching on in Home Appliances DESIGN RESOURCES
  • AD2S44 Material Declaration
  • PCN-PDN Information
  • Quality And Reliability
  • Symbols and Footprints DISCUSSIONS View all AD2S44 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. B | Page 2 of 12 TABLE OF CONTENTS

REVISION HISTORY

10/11—Rev. A to Rev. B 08/08—Rev. 0 to Rev. A Changes to Processing for High Reliability Section and 10/89—Revision 0: Initial Version

Rev. B | Page 3 of 12 SPECIFICATIONS VS = ±15 V at TA = 25°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments PERFORMANCE Accuracy1 AD2S44-UMB2 −4.0 +4.0 Arc minutes −55°C to +125°C −2.6 +2.6 Arc minutes −25°C to +85°C AD2S44-TMB2 −4.0 +4.0 Arc minutes −55°C to +125°C Tracking Rate 20 Rev/sec Resolution (1 LSB = 1.3 Arc Minutes) 14 Bits Output coding parallel natural binary Repeatability 1 LSB Signal/Reference Frequency 400 2600 Hz Bandwidth 100 Hz SIGNAL INPUTS Signal Voltage 11.8 or 90 V rms See the Ordering Information section Input Impedance

90 V Signal 200 kΩ Resistive tolerance ±2%

11.8 V Signal 26 kΩ

Common-Mode Rejection 74 dB Common-Mode Range

90 V Signal ±250 V dc

11.8 V Signal ±60 V dc

Reference Voltage 26 or 115 V rms See the Ordering Information section Input Impedance

115 V 270 kΩ Resistive tolerance ±5%

26 V 270 kΩ

115 V ±210 V dc

26 V ±210 V dc

ACCELERATION CONSTANT 62,000 sec–2 STEP RESPONSE Large Step1, 2 63 75 ms 179° to 1 LSB of error Small Step1, 2 25 30 ms 2° to 1 LSB of error POWER LINES +VS = +15 V1, 2 75 80 mA Quiescent condition –VS = −15 V1, 2 40 45 mA Quiescent condition Power Dissipation 1.7 1.9 W Quiescent condition DIGITAL INPUTS OE VIL 0.7 V dc IIL = 5 µA VIH 2.0 V dc IIH = 5 µA A/B VIL 0.7 V dc IIL = 1.2 mA VIH 2.0 V dc IIH = –60 µA DIGITAL OUTPUTS (DB1 to DB14) VOL1, 2 0.4 V dc IIL = 1.2 mA VOH1, 2 2.4 V dc IOH = 60 µA Three-State Leakage Current ±40 µA Drive Capability 3 LSTTL loads

Rev. B | Page 4 of 12 Parameter Min Typ Max Unit Test Conditions/Comments DATA TRANSFER See Figure 6 Time to Data Stable (After Negative Edge of OE or Change of Level of A/B) 640 ns tS Time to Data in High Impedance State (After Positive Edge of OE) 200 ns tR Time for Repetitive Strobing of Selected Channel 200 ns tP BUILT-IN TEST OUTPUT (BIT) Sense Active low Low = error condition VOL 0.4 V dc IOL = 3.2 mA VOH 2.4 V dc IOH = −160 µA Drive Capability 8 LSTTL loads Error Condition Set 55 LSB Error Condition Cleared 45 LSB 1 Specified overtemperature range, −55°C to +125°C, and for: (a) ±10% signal and reference amplitude variation; (b) ±10% signal and reference harmonic distortion; (c) ±5% power supply variation; and (d) ±10% variation in reference frequency. 2 These parameters are 100% tested at nominal values of power supplies, input signal voltages, and operating frequency. All other parameters are guaranteed by design, not tested.

Rev. B | Page 5 of 12 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating +VS to GND +17.25 V dc –VS to GND −17.25 V dc Any Logic Input to GND +6.0 V dc (maximum) Any Logic Input to GND −0.4 V dc (minimum) Maximum Junction Temperature 150°C S1, S2, S3, S4 Pins (Line-to-Line)1

90 V Option ±600 V dc

11.8 V Option ±80 V dc

S1, S2, S3, S4 Pins to GND

26 V, 115 V Options ±600 V dc

RHI Pins to RLO Pins to GND Storage Temperature Range −65°C to +150°C Operating Temperature Range −55°C to +125°C

1 On synchro input options, line-to-line voltage refers to the differential voltages

of S2 (A)/S2 (B) to S1 (A)/S1 (B), S1 (A)/S1 (B) to S3 (A)/S3 (B), and S3 (A)/S3 (B) to S2 (A)/S2 (B). On resolver input options, line-to-line levels refer to the S1 (A)/ S1 (B) to S3 (A)/S3 (B) and S2 (A)/S2 (B) to S4 (A)/S4 (B) voltages. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 2. Pin Configuration Table 3. Pin Function Descriptions 1 to 7 DB8 to DB14 (LSB) Parallel Output Data Bits. 9 A/B Channel A or Channel B Select Input. 10 BIT Built-In Test Error Output. 11 RLO (A) Input Pin for Channel A Reference Low. 12 RHI (A) Input Pin for Channel A Reference High. 13 to 16 S4 (A) to S1 (A) Channel A Input Signal. 17 to 20 S1 (B) to S4 (B) Channel B Input Signal. 21 RHI (B) Input Pin for Channel B Reference High. 22 RLO (B) Input Pin for Channel B Reference Low. 23 GND Power Supply Ground. This pin is electrically connected to the case. 24 –VS Negative Power Supply. 25 +VS Positive Power Supply. 26 to 32 DB1 (MSB) to DB7 Parallel Output Data Bits.

θ is the angle of the synchro shaft. E0 sin ωt is the reference signal. K is the transformation ratio of the input signal conditioner. the rated accuracy of the converter. ±15 V and cannot be reversed. is to be taken to 0 V potential in the system. to Pin 7. Pin 26 is the MSB, and Pin 7 is the LSB. is toggled. Timing information is shown in Figure 4 and Figure 5. Figure 3. Functional Block Diagram

Rev. B | Page 12 of 12 ©1989–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02947-0-10/11(B) NOTES