AD2S1205YSTZ

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Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.

FEATURES

Complete monolithic resolver-to-digital converter (RDC) Parallel and serial 12-bit data ports System fault detection ±11 arc minutes of accuracy Input signal range: 3.15 V p-p ± 27% Absolute position and velocity outputs 1250 rps maximum tracking rate, 12-bit resolution Incremental encoder emulation (1024 pulses/rev) Programmable sinusoidal oscillator on board Single-supply operation (5.00 V ± 5%) −40°C to +125°C temperature rating 44-lead LQFP 4 kV ESD protection Qualified for automotive applications

APPLICATIONS

Automotive motion sensing and control Hybrid-electric vehicles Electric power steering Integrated starter generator/alternator Industrial motor control Process control FUNCTIONAL BLOCK DIAGRAM 06339-001 REFERENCE OSCILLATOR (DAC) TYPE II TRACKING LOOP FAULT DETECTION POSITION REGISTER RESET AD2S1205 DATA BUS OUTPUT VELOCITY REGISTER ENCODER EMULATION SYNTHETIC REFERENCE INTERNAL CLOCK GENERATOR VOLTAGE REFERENCE REFERENCE PINS CRYSTAL DATA I/O ADC ADC MULTIPLEXER EXCITATION OUTPUTS INPUTS FROM RESOLVER FAULT DETECTION OUTPUTS ENCODER EMULATION OUTPUTS Figure 1. GENERAL DESCRIPTION The AD2S1205 is a complete 12-bit resolution tracking resolver-to-digital converter that contains an on-board programmable sinusoidal oscillator providing sine wave excitation for resolvers. The converter accepts 3.15 V p-p ± 27% input signals on the Sin and Cos inputs. A Type II tracking loop is employed to track the inputs and convert the input Sin and Cos information into a digital representation of the input angle and velocity. The maximum tracking rate is a function of the external clock frequency. The performance of the AD2S105 is specified across a frequency range of 8.192 MHz ± 25%, allowing a maximum tracking rate of 1250 rps. PRODUCT HIGHLIGHTS 1. Ratiometric Tracking Conversion. The Type II tracking loop provides continuous output position data without conversion delay. It also provides noise immunity and tolerance of harmonic distortion on the reference and input signals. 2. System Fault Detection. A fault detection circuit can sense loss of resolver signals, out-of-range input signals, input signal mismatch, or loss of position tracking. 3. Input Signal Range. The Sin and Cos inputs can accept differential input voltages of 3.15 V p-p ± 27%. 4. Programmable Excitation Frequency. Excitation frequency is easily programmable to 10 kHz, 12 kHz, 15 kHz, or 20 kHz by using the frequency select pins (the FS1 and FS2 pins). 5. Triple Format Position Data. Absolute 12-bit angular position data is accessed via either a 12-bit parallel port or a 3-wire serial interface. Incremental encoder emulation is in standard A-quad-B format with direction output available. 6. Digital Velocity Output. 12-bit signed digital velocity accessed via either a 12-bit parallel port or a 3-wire serial interface.

Rev. A | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

5/10—Rev. 0 to Rev. A Changes to Input Bias Current Parameter and Input Changes to Connecting the Converter Section and Figure 5 ... 11 Change to t 1/07—Revision 0: Initial Version

Rev. A | Page 3 of 20 SPECIFICATIONS AVDD = DVDD = 5.0 V ± 5% at −40°C to +125°C, CLKIN = 8.192 MHz ± 25%, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Conditions/Comments Sin, Cos INPUTS1 Voltage 2.3 3.15 4.0 V p-p Sinusoidal waveforms, Sin − SinLO and Cos − CosLO, differential inputs Input Bias Current 12 μA VIN = 4.5 VDC, CLKIN = 10.24 MHz Input Impedance 0.35 MΩ VIN = 4.5 VDC Common-Mode Voltage 100 mV peak CMV with respect to REFOUT/2 at 10 kHz Phase-Lock Range −44 +44 Degrees Sin/Cos vs. EXC output ANGULAR ACCURACY Angular Accuracy ±11 Arc minutes Zero acceleration, Y grade ±22 Arc minutes Zero acceleration, W grade Resolution 12 Bits Guaranteed no missing codes Linearity INL 2 LSB Zero acceleration, 0 rps to 1250 rps, CLKIN = 10.24 MHz Linearity DNL 0.3 LSB Guaranteed monotonic Repeatability 1 LSB Hysteresis 1 LSB VELOCITY OUTPUT Velocity Accuracy 2 LSB Zero acceleration Resolution 11 Bits Linearity 1 LSB Guaranteed by design, 2 LSB maximum Offset 0 1 LSB Zero acceleration Dynamic Ripple 1 LSB Zero acceleration DYNAMIC PERFORMANCE Bandwidth 1000 2400 Hz Tracking Rate 750 rps CLKIN = 6.144 MHz , guaranteed by design 1000 rps CLKIN = 8.192 MHz , guaranteed by design 1250 rps CLKIN = 10.24 MHz , guaranteed by design Acceleration Error 30 Arc minutes At 10,000 rps, CLKIN = 8.192 MHz Settling Time 179° Step Input 5.2 ms To within ±11 arc minutes, Y grade, CLKIN = 10.24 MHz 4.0 ms To within 1 degree, Y grade, CLKIN = 10.24 MHz EXC, EXC OUTPUTS Voltage 3.34 3.6 3.83 V p-p Load ±100 μA Center Voltage 2.39 2.47 2.52 V Frequency 10 kHz FS1 = high, FS2 = high, CLKIN = 8.192 MHz 12 kHz FS1 = high, FS2 = low, CLKIN = 8.192 MHz 15 kHz FS1 = low, FS2 = high, CLKIN = 8.192 MHz 20 kHz FS1 = low, FS2 = low, CLKIN = 8.192 MHz EXC/EXC DC Mismatch 35 mV THD −58 dB First five harmonics FAULT DETEC TION BLOCK Loss of Signal (LOS) Sin/Cos Threshold 2.18 2.24 2.3 V p-p DOS and LOT go low when Sin or Cos fall below threshold Angular Accuracy (Worst Case) 57 Degrees LOS indicated before angular output error exceeds limit (4.0 V p-p input signal and 2.18 V LOS threshold) Angular Latency (Worst Case) 114 Degrees Maximum electrical rotation before LOS is indicated (4.0 V p-p input signal and 2.18 V LOS threshold) Time Latency 125 μs

Rev. A | Page 4 of 20 Parameter Min Typ Max Unit Conditions/Comments Degradation of Signal (DOS) Sin/Cos Threshold 4.0 4.09 4.2 V p-p DOS goes low when Sin or Cos exceeds threshold Angular Accuracy (Worst Case) 33 Degrees DOS indicated before angular output error exceeds limit Angular Latency (Worst Case) 66 Degrees Maximum electrical rotation before DOS is indicated Time Latency 125 μs Sin/Cos Mismatch 385 420 mV DOS latched low when Sin/Cos amplitude mismatch exceeds threshold Loss of Tracking (LOT) Tracking Threshold 5 Degrees LOT goes low when internal error signal exceeds threshold; guaranteed by design Time Latency 1.1 ms Hysteresis 4 Degrees Guaranteed by design VOLTAGE REFERENCE REFOUT 2.39 2.47 2.52 V ±IOUT = 100 μA Drift 70 ppm/°C PSRR −60 dB CHARGE-PUMP OUTPUT (CPO) Frequency 204.8 kHz Square wave output, CLKIN = 8.192 MHz Duty Cycle 50 % POWER SUPPLY IDD Dynamic 20 mA

ELECTRICAL CHARACTERISTICS

VIL, Voltage Input Low 0.8 V VIH, Voltage Input High 2.0 V VOL, Voltage Output Low 0.4 V +1 mA load VOH, Voltage Output High 4.0 V −1 mA load IIL, Low Level Input Current (Non-Pull-Up) −10 +10 μA SAMPLE, CS, RDVEL, CLKIN, SOE pins IIL, Low Level Input Current (Pull-Up) −80 +80 μA RD, FS1, FS2, RESET pins IIH, High Level Input Current −10 +10 μA IOZH, High Level Three-State Leakage −10 +10 μA IOZL, Low Level Three-State Leakage −10 +10 μA 1 The voltages for Sin, SinLO, Cos, and CosLO relative to AGND must be between 0.2 V and AVDD.

Rev. A | Page 5 of 20 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage (VDD) −0.3 V to +7.0 V Supply Voltage (AVDD) −0.3 V to +7.0 V Input Voltage −0.3 V to VDD + 0.3 V Output Voltage Swing −0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies1 ±10 mA Operating Temperature Range (Ambient) −40°C to +125°C Storage Temperature Range −65°C to +150°C 1 Transient currents of up to 100 mA do not cause latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 2. Pin Configuration Table 3. Pin Function Descriptions enabled when CS and RD are held low. 3 CS Chip Select. Active low logic input. The device is enabled when CS is held low. velocity registers, respectively, after a high-to-low transition on the SAMPLE signal. selected by holding the SOE pin low, and the parallel interface is selected by holding the SOE pin high. and RD. The bits are clocked out on the rising edge of SCLK. 8 DB10/SCLK Data Bit 10/Serial Clock. In parallel mode this pin acts as DB10, a three-state data output pin controlled by CS and RD. In serial mode this pin acts as the serial clock input. 9 to 15 DB9 to DB3 Data Bit 9 to Data Bit 3. Three-state data output pins controlled by CS and RD. apart, even on a transient basis. 18 to 20 DB2 to DB0 Data Bit 2 to Data Bit 0. Three-state data output pins controlled by CS and RD. XTALOUT pins. The position and velocity accuracy are guaranteed for a frequency range of 8.192 MHz ± 25%. XTALOUT pins. The position and velocity accuracy are guaranteed for a frequency range of 8.192 MHz ± 25%. CPO output pin. This square wave output can be used for negative rail voltage generation or to create a VCC rail. input signals applied to the converter are valid.

Rev. A | Page 7 of 20 Pin No. Mnemonic Description 26 B Incremental Encoder Emulation Output B. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. 27 NM North Marker Incremental Encoder Emulation Output. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. 28 DIR Direction. Logic output. This output is used in conjunction with the incremental encoder emulation outputs. The DIR output indicates the direction of the input rotation and is high for increasing angular rotation. 29 DOS Degradation of Signal. Logic output. Degradation of signal (DOS) is detected when either resolver input (Sin or Cos) exceeds the specified DOS Sin/Cos threshold. See the Signal Degradation Detection section. DOS is indicated by a logic low on the DOS pin and is not latched when the input signals exceed the maximum input level. 30 LOT Loss of Tracking. Logic output. LOT is indicated by a logic low on the LOT pin and is not latched. See the Loss of Signal Detection section. 31 FS1 Frequency Select 1. Logic input. FSI in conjunction with FS2 allows the frequency of EXC/EXC to be programmed. 32 FS2 Frequency Select 2. Logic input. FS2 in conjunction with FS1 allows the frequency of EXC/EXC to be programmed. 33 RESET Reset. Logic input. The AD2S1205 requires an external reset signal to hold the RESET input low until VDD is within the specified operating range of 4.5 V to 5.5 V. See the section. Supply Sequencing and Reset 34 EXC Excitiation Frequency. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the FS1 and FS2 pins. 35 EXC Excitation Frequency Complement. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the FS1 and FS2 pins. 36, 42 AGND Analog Ground. These pins are ground reference points for analog circuitry on the AD2S1205. All analog input signals and any external reference signal should be referred to this AGND voltage. Both of these pins should be connected to the AGND plane of a system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 37 Sin Positive Analog Input of Differential Sin/SinLO Pair. The input range is 2.3 V p-p to 4.0 V p-p. 38 SinLO Negative Analog Input of Differential Sin/SinLO Pair. The input range is 2.3 V p-p to 4.0 V p-p. 39 AVDD Analog Supply Voltage, 4.75 V to 5.25 V. This pin is the supply voltage for all analog circuitry on the AD2S1205. The AVDD and DVDD voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 40 CosLO Negative Analog Input of Differential Cos/CosLO Pair. 41 Cos Positive Analog Input of Differential Cos/CosLO Pair. 43 REFBYP Reference Bypass. Reference decoupling capacitors should be connected here. Typical recommended values are 10 μF and 0.01 μF. 44 REFOUT Voltage Reference Output, 2.39 V to 2.52 V.

Rev. A | Page 9 of 20 THEORY OF OPERATION The AD2S1205’s operation is based on a Type II tracking closed- loop principle. The digitally implemented tracking loop continually tracks the position and velocity of the resolver without the need for external convert and wait states. As the resolver moves through a position equivalent to the least significant bit weighting, the tracking loop output is updated by 1 LSB. The converter tracks the shaft angle (θ) by producing an output angle (ϕ) that is fed back and compared with the input angle (θ); the difference between the two angles is the error, which is driven towards 0 when the converter is correctly tracking the input angle. To measure the error, S3 − S1 is multiplied by Cosϕ and S2 − S4 is multiplied by Sinϕ to give S4 S2 for) ( S1 S3 for) ( SinφCosθωt Sin E Cosφ Sinθ ωt Sin E (2) The difference is taken, giving )( ) (0 SinφCosθCos Sinθ ωt Sin E−φ× (3) This signal is demodulated using the internally generated synthetic reference, yielding )(0 φ−φ Sin Cosθ Cos Sinθ E (4) Equation 4 is equivalent to E0Sin(θ − ϕ), which is approximately equal to E0(θ − ϕ) for small values of θ − ϕ, where θ − ϕ is the angular error. The value E0(θ − ϕ) is the difference between the angular error of the rotor and the digital angle output of the converter. A phase-sensitive demodulator, some integrators, and a compen- sation filter form a closed-loop system that seeks to null the error signal. If this is accomplished, ϕ equals the resolver angle, θ, within the rated accuracy of the converter. A Type II tracking loop is used so that constant velocity inputs can be tracked without inherent error. For more information about the operation of the converter, see the Circuit Dynamics section. FAULT DETECTION CIRCUIT The AD2S1205 fault detection circuit can sense loss of resolver signals, out-of-range input signals, input signal mismatch, or loss of position tracking; however, the position indicated by the AD2S1205 may differ significantly from the actual shaft position of the resolver. MONITOR SIGNAL The AD2S1205 generates a monitor signal by comparing the angle in the position register to the incoming Sin and Cos signals from the resolver. The monitor signal is created in a similar fashion to the error signal (described in the Theory of Operation section). The incoming Sinθ and Cosθ signals are multiplied by the Sin and Cos of the output angle, respectively, and then these values are added together: )( )( CosφCosθA2 Sinφ Sinθ A1Monitor ×× + ××= (5) where: A1 is the amplitude of the incoming Sin signal (A1 × Sinθ). A2 is the amplitude of the incoming Cos signal (A2 × Cosθ). θ is the resolver angle. ϕ is the angle stored in the position register. Note that Equation 5 is shown after demodulation with the carrier signal Sin(ωt) removed. Also note that for a matched input signal (that is, a no fault condition), A1 is equal to A2. When A1 is equal to A2 and the converter is tracking (therefore, θ is equal to ϕ), the monitor signal output has a constant magnitude of A1 (Monitor = A1 × (Sin 2θ + Cos2θ) = A1), which is independent of the shaft angle. When A1 does not equal A2, the monitor signal magnitude alternates between A1 and A2 at twice the rate of the shaft rotation. The monitor signal is used to detect degradation or loss of input signals. LOSS OF SIGNAL DETECTION Loss of signal (LOS) is detected when either resolver input (Sin or Cos) falls below the specified LOS Sin/Cos threshold. The AD2S1205 detects this by comparing the monitor signal to a fixed minimum value. Without the use of external circuitry, the AD2S1205 can detect the loss of up to three of the four connections from the resolver. The addition of two external 68 kΩ resistors, as outlined in Figure 5, ensures that the loss of all 4 connections, that is, complete removal of the resolver, may also be detected. LOS is indicated by both DOS and LOT latching as logic low outputs. The DOS and LOT pins are reset to the no fault state by a rising edge of SAMPLE . The LOS condition has priority over both the DOS and LOT conditions, as shown in . LOS is indicated within 57° of the angular output error (worst case). Table 4

indicated within 33° of the angular output error (worst case).

• The internal error signal of the AD2S1205 exceeds 5°.
• The input signal exceeds the maximum tracking rate.
• The internal position (at the position integrator) differs from the external position (at the position register) by more than 5°. LOT is indicated by a logic low on the LOT pin and is not latched. LOT has a 4° hysteresis and is not cleared until the internal error signal or internal/external position mismatch is less than 1°. When the maximum tracking rate is exceeded, LOT is cleared only if the velocity is less than the maximum tracking rate and the internal/external position mismatch is less than 1°. LOT can be indicated for step changes in position (such as after a RESET signal is applied to the AD2S1205), or for accelerations of >~65,000 rps2. It is also useful as a built-in test to indicate that the tracking converter is functioning properly. The LOT condition has lower priority than both the DOS and LOS conditions, as shown in . The LOT and DOS conditions cannot be indicated at the same time. Table 4

Table 4. Fault Detection Decoding before the fault condition is reindicated. force the parallel, serial, or encoder outputs to a known state. Response to specific fault conditions is a system-level requirement. data provided by the AD2S1205. specified in the Dynamic Performance section of Table 1). after the start-up sequence if the resolver signals are valid.

is centered on 2.5 V and has an amplitude of 3.6 V p-p. Table 5. Excitation Frequency Selection resolver. See Figure 6 for a suggested buffer circuit. need for an external preset phase-compensation circuit. than 10° and can operate for phase shifts of ±45°. be used for negative rail voltage generation or to create a VCC rail. Ground is connected to the AGND and DGND pins (see Figure 5). REF/2 offset in the Sin and Cos signal outputs from the resolver. outputs are differential, there is an inherent gain of 2×. ω is the radian frequency of the applied signal. eliminating the need for a negative supply.

RD is released before reapplying it. The device is enabled when CS is held low. be set (stable) at least t4 before the RD pin is pulled low. Figure 7. Parallel Port Read Timing Table 6. Parallel Port Timing

Rev. A | Page 14 of 20 SERIAL INTERFACE The angular position and velocity are available on the AD2S1205 in two 12-bit registers. These registers can be accessed via a 3-wire serial interface (SO, RD, and SCLK) that operates at clock rates of up to 25 MHz and is compatible with SPI and DSP interface standards. The serial interface is selected by holding the SOE pin low. Data from the position and velocity integrators are first trans- ferred to the position and velocity registers using the SAMPLE pin. The RDVEL pin selects whether data is transferred from the position or velocity register to the output register, and the CS pin must be held low to transfer data from the selected register to the output register. Finally, the RD input is used to read the data that is clocked out of the output register and is available on the serial output pin (SO). When the serial interface is selected, DB11 is used as the serial output pin (SO), DB10 is used as the serial clock input (SCLK), and Pin DB0 to Pin DB9 are placed into the high imped- ance state. The timing requirements for the read cycle are described in . Figure 8 SO Output The output shift register is 16 bits wide. Data is clocked out of the device as a 16-bit word by the serial clock input (SCLK). The timing diagram for this operation is shown in Figure 8. The 16-bit word consists of 12 bits of angular data (position or velocity, depending on RDVEL input), one RDVEL status bit, and three status bits (a parity bit, a degradation of signal bit, and a loss of tracking bit). Data is clocked out MSB first from the SO pin, beginning with DB15. DB15 through DB4 correspond to the angular information. The angular position data format is unsigned binary, with all 0s corresponding to 0° and all 1s cor- responding to 360° − l LSB. The angular velocity data format is twos complement, with the MSB representing the rotation direction. DB3 is the RDVEL status bit, with a 1 indicating position and a 0 indicating velocity. DB2 is DOS, the degradation of signal flag (refer to the section). Bit 1 is LOT, the loss of tracking flag (refer to the section). Bit 0 is PAR, the parity bit. The position and velocity data are in odd parity format, and the data readback always contains an odd number of logic highs (1s). Fault Detection Circuit Fault Detection Circuit SAMPLE Input Data is transferred from the position and velocity integrators to the position and velocity registers, respectively, after a high-to- low transition on the SAMPLE signal. This pin must be held low for at least t1 to guarantee correct latching of the data. RD should not be pulled low before this time because data will not be ready. The converter continues to operate during the read process. CS Input The device is enabled when CS is held low. RD Input The 12-bit data bus lines are normally in a high impedance state. The output buffer is enabled when CS and RD are held low. The RD input is an edge-triggered input that acts as a frame synchronization signal and an output enable. On a falling edge of the RD signal, data is transferred to the output buffer. Data is then available on the serial output pin (SO); however, it is only valid after RD is held low for t9. The serial data is clocked out of the SO pin on the rising edges of SCLK, and each data bit is available at the SO pin on the falling edge of SCLK. However, as the MSB is clocked out by the falling edge of RD, the MSB is available at the SO pin on the first falling edge of SCLK. Each subsequent bit of the data-word is shifted out on the rising edge of SCLK and is available at the SO pin on the falling edge of SCLK for the next 15 clock pulses. The high-to-low transition of RD must occur during the high time of the SCLK to avoid DB14 being shifted on the first rising edge of the SCLK, which would result in the MSB being lost. RD may rise high after the last falling edge of SCLK. If RD is held low and additional SCLKs are applied after DB0 has been read, then 0s will be clocked from the data output. When reading data continuously, wait a minimum of t 5 after RD is released before reapplying it. RDVEL Input RDVEL input is used to select between the angular position register and the angular velocity register. RDVEL is held high to select the angular position register and low to select the angular velocity register. The RDVEL pin must be set (stable) at least t4 before the RD pin is pulled low.

Figure 8. Serial Port Read Timing Table 7. Serial Port Timing1 1 t1 to t7 are as defined in Table 6.

Figure 11. RDC System Response Block Diagram to convert these to digital position and velocity words. inputs and the gain of the error signal into the first integrator. The first integrator generates a signal proportional to velocity. to provide phase margin and reduce high frequency noise gain. second-order low-pass filter (see Figure 12 and Figure 13). where t is the sampling period (1/4.096 MHz ≈ 244 ns). Substitution yields the open-loop transfer function G(s).

• Alternate framing transmit mode with internal framing (internally inverted)
• Normal framing receive mode with external framing (internally inverted)
• Internal serial clock generation In this configuration, the internal TFS signal of ADMC401 is used as an external RFS to fully control the timing of data received, and the same TFS is connected to RD of the AD2S1205. In addition, the ADMC401 provides an internal continuous serial clock to the AD2S1205. The SAMPLE signal on the AD2S1205 can be provided either by using a PIO or by inverting the PWMSYNC signal to synchronize the position and velocity readings with the PWM switching frequency. CS and RDVEL can be obtained using two PIO outputs of the ADMC401. The 12 bits of significant data and the status bits are available on each consecutive negative edge of the clock after the RD signal goes low. Data is clocked from the AD2S1205 into the data receive register of the ADMC401. This is internally set to 16 bits (12 data bits, 4 status bits) because 16 bits are received overall. The serial port automatically generates an internal processor interrupt. This allows the ADMC401 to read all 16 bits and then continue to process data. All ADMC401 products can interface to the AD2S1205 by using similar interface circuitry. 06339-016 SCLK DR TFS RFS PWMSYNC PIO PIO SCLK SOE SO RD SAMPLE CS RDVEL ADMC401 AD2S1205

Figure 16. Connecting to the ADMC401

Figure 17. 44-Lead Low Profile Quad Flat Package [LQFP] 2 W = Qualified for Automotive Applications. 3 This can be used either as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes. designator. For a complete evaluation kit, order the ADC evaluation board (that is, the EVAL-AD2S1205CBZ), the EVAL-CONTROL BRD2, and a 12 V ac transformer. Automotive Reliability reports for these models. registered trademarks are the prop erty of their respective owners.