AD2S100 AD | Alldatasheet
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Tel: 617/329-4700 Fax: 617/326-8703 REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD2S100 FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The AD2S100 performs the vector rotation of three-phase 120 degree or two-phase 90 degree sine and cosine signals by trans- ferring these inputs into a new reference frame which is controlled by the digital input angle φ. Two transforms are included in the AD2S100. The first is the Clarke transform which computes the sine and cosine orthogonal components of a three-phase input. These signals represent real and imaginary components which then form the input to the Park transform. The Park transform relates the angle of the input signals to a reference frame controlled by the digital input port. The digital input port is a 12-bit parallel binary representation. If the input signals are represented by Vds and Vqs, respectively, where Vds and Vqs are the real and imaginary components, then the transformation can be described as follows: Vds' = Vds Cosφ – Vqs Sinφ Vqs' = Vds Sinφ + Vqs Cosφ Where Vds' and Vqs' are the output of the Park transform and Sinφ, and Cosφ are the values internally derived by the AD2S100 from the binary digital data. The input section of the device can be configured to accept either three-phase inputs, two-phase inputs of a three-phase system, or two 90 degree input signals. The homopolar output detects the imbalance of a three-phase input only. Under nor- mal conditions, this output will be zero. The digital input section will accept a resolution of up to 12 bits (AD2S100). An input data strobe signal is required to synchro- nize the position data and load this information into the device counters. A busy output is provided to identify the conversion status of the AD2S100. The busy period represents the conver- sion time of the vector rotation. Two analog output formats are available. A two-phase rotated output facilitates multiple rotation blocks. Three phase format signals are available for use with a PWM inverter. PRODUCT HIGHLIGHTS Hardware Peripheral for Standard Microcontrollers and DSP Systems The AD2S100 removes the time consuming cartesian transfor- mations from digital processors and benchmarks a speed im- provement of 30:1 on standard 20 MHz processors. AD2S100 transformation time = 2 µs (typ). Field Oriented Control of AC and DC Brushless Motors The AD2S100 accommodates all the necessary functions to provide a hardware solution for ac vector control of induction motors and dc brushless motors. Three-Phase Imbalance Detection The AD2S100 can be used to sense overcurrent situations or imbalances in a three-phase system via the homopolar output. Resolver-to-Digital Converter Interface The AD2S100 provides general purpose interface for position sensors used in the application of dc brushless and ac induction motor control. Ia Ib Ic Vds Vqs SECTOR MULTIPLIER SINE AND COSINE MULTIPLIER INPUT DATA STROBE HOMOPOLAR OUTPUT HOMOPOLAR REFERENCE +5V GND –5V φ POSITION PARALLEL DATA
12 BITS
Cos (θ + 120° + φ) Cos (θ + 240° + φ) Va Vb Vc 30-20 SinθCos θ Cos θ Sinθ Cos θ + φ CONV1 CONV2 DECODE BUSY Vds' Vqs' Sin θ + φ SECTOR MULTIPLIER SINE AND COSINE MULTIPLIER Ia + Ib + Ic 2φ -3φCos (θ + 120°) Cos (θ + 240°) AC Vector Processor
FEATURES
Complete Vector Coordinate Transformation on Silicon Mixed Signal Data Acquisition Three-Phase 120 8 and Orthogonal 90 8 Signal Transformation Three-Phase Balance Diagnostic–Homopolar Output
APPLICATIONS
AC Induction and DC Permanent Magnet Motor Control HVAC, Pump, Fan Control Material Handling Robotics Spindle Drives Gyroscopes Dryers Washing Machines Electric Cars Actuator Three-Phase Power Measurement Digital-to-Resolver & Synchro Conversion OBSOLETE
AD2S100–SPECIFICATIONS Parameter Min Typ Max Units Conditions SIGNAL INPUTS PH/IP1, 2, 3, 4 Voltage Level ± 2.8 63.3 V p-p DC to 50 kHz PH/IPH1, 2, 3 Voltage Level ± 4.25 V p-p DC to 50 kHz Input Impedance PH/IP1, 2, 3 7.5 10 k Ω PH/IPH1, 2, 3 13.5 18 k Ω PH/IP1, 4 1 M Ω Mode 1 Only (2 Phase) Sin & Cos Gain PH/IP1, 2, 3, 4 0.98 1 1.02 PH/IPH1, 2, 3 0.56 VECTOR PERFORMANCE 3θ Input-Output Radius Error (Any Phase) 0.35 0.7 % DC to 600 Hz Angular Error1, 2 (PH/IP) 9 18 arc min DC to 600 Hz (PH/IPH) 24 arc min DC to 600 Hz Monotonicity Guaranteed Monotonic Full Power Bandwidth 50 kHz Small Signal Bandwidth 200 kHz ANALOG SIGNAL OUTPUTS PH/OP1, 2, 3, 4 PH/IP, PH/IPH INPUTS Output Voltage3 ± 2.8 ± 3.3 V p-p DC to 50 kHz Offset Voltage 2 5 mV Inputs = 0 V Slew Rate 2 V/ µs Small Signal Step Response 1 µs1 ° Input to Settle to ± 1 LSB (Input to Output) Output Resistance 15 Ω Output Drive Current 3.0 4.0 mA Outputs to AGND Resistive Load 2 kΩ Capacitive Load 50 pF STROBE Write 100 ns Positive Pulse Max Update Rate 366 kHz BUSY Pulse Width 1.7 2.5 µs Conversion in Process VOH 4V dc IOH = 0.5 mA VOL 1V dc I OL = 0.5 mA DIGITAL INPUTS DB1–DB12 VIH 3.5 V dc VIL 1.5 V dc Input Current, IIN 610 µA Input Capacitance, CIN 10 pF CONVERT MODE (CONV1, CONV2) VIH 3.5 V dc Internal 50 k Ω Pull-Up Resistor VIL 1.5 V dc Input Current 100 µA Input Capacitance 10 pF CONVERT LOGIC CONV1 CONV2 NO CONNECT DGND 2-Phase Orthogonal with 2 Inputs Nominal Input Level DGND V DD 3-Phase (0°, 120°, 240°) with 3 Inputs Nominal Input Level VDD VDD 3-Phase (0°, 120°, 240°) with 2 Inputs Nominal Input Level REV. A–2– (VDD = +5 V 6 5%; VSS = –5 V 6 5% AGND = DGND = O V; TA = –40 8C to +85°C, unless otherwise noted) OBSOLETE
Parameter Min Typ Max Units Conditions HOMOPOLAR OUTPUT HPOP–Output VOH 4 V dc I OH = 0.5 mA VOL 1 V dc I OL = 0.5 mA HPREF–REFERENCE 0.5 V dc Homopolar Output-Internal ISOURCE = 25 µA and 20 kΩ to AGND HPFILT-FILTER 100 k Ω Internal Resistor with External Capacitor = 220 nF POWER SUPPLY VDD 4.75 5 5.25 V dc VSS –5.25 –5 –4.75 V dc IDD 4 10 mA Quiescent Current ISS 4 10 mA Quiescent Current NOTES 1Angular accuracy includes offset and gain errors. Stationary digital input and maximum analog frequency inputs. 2Included in the angular error is an allowance for the additional error caused by the phase delay as a function of input frequency. For example, if fINPUT = 600 Hz, the contribution to the error due to phase delay is: 650 ns × fINPUT × 60 × 360 = 8.4 arc minutes. 3Output subject to input voltage and gain. Specifications in boldface are production tested. Specifications subject to change without notice. AD2S100 REV. A –3– RECOMMENDED OPERATING CONDITIONS Ambient Operating Temperature Range ORDERING GUIDE Model Temperature Range Accuracy Option* AD2S100AP –40 °C to +85°C 18 arc min P-44A *P = Plastic Leaded Chip Carrier. ABSOLUTE MAXIMUM RATINGS (TA = +25°C) Analog Output Voltage to AGND Analog Output Load Condition (PH/OP1, 2, 3, 4 Operating Temperature CAUTION 1. Absolute Maximum Ratings are those values beyond which damage to the device may occur. 2. Correct polarity voltages must be maintained on the +V DD and –VSS pins. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD2S100 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. OBSOLETE
REV. A–4– PIN DESIGNATIONS1, 2, 3 Pin Mnemonic Description
3 STROBE Begin Conversion
4V DD Positive Power Supply 5V SS Negative Power Supply
6 PH/OP4 Sin ( θ + φ)
7 PH/OP1 Cos ( θ + φ)
8 PH/OP3 Cos ( θ + 240° + φ)
9 PH/OP2 Cos ( θ + 120° + φ)
10 AGND Analog Ground
11 PH/IP4 Sin θ Input
12 PH/IPH3 High Level Cos ( θ + 240°) Input
13 PH/IP3 Cos ( θ + 240°) Input
14 PH/IPH2 High Level Cos ( θ + 120°) Input
15 PH/IP2 Cos ( θ + 120°) Input
16 PH/IPH1 High Level Cos θ Input
17 PH/IP1 Cos (θ) Input
19 V SS Negative Power Supply
20 HPREF Homopolar Reference
21 HPOP Homopolar Output
22 HPFILT Homopolar Filter
23 CONV1 Select Input Format (3 Phase/3 Wire, Sin θ
24 CONV2 Cos θ/Input, 3 Phase/2 Wire)
25 COS Cos Output
26 SIN Sin Output
27 DB12 (DB1 = MSB, DB12 = LSB
38 DB1 Parallel Input Data)
42 DGND Digital Ground
44 BUSY Conversion in Progress
Signal Inputs Ph/IP and PH/IPH on Pin Nos 11 through 17. 190° orthogonal signals = Sin θ, Cos θ (Resolver) = PH/IP4 and PH/IP1. 2Three phase, 120 °, three-wire signals = Cos θ, Cos (θ + 120°), Cos (θ + 240°). = PH/IP1, PH/IP2, PH/IP3 High Level = PH/IPH1, PH/IPH2, PH/IPH3. 3Three Phase, 120 °, two-wire signals = Cos ( θ + 120°), Cos (θ + 240°) = PH/IP2, PH/IP3. In all cases where any of the input Pins 11 through 17 are not used, they must be left unconnected. PIN CONFIGURATION 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 VSS VDD STROBE NC NC BUSY DGND VDD NC NC VSS HPREF HPOP CONV1CONV2 COS DB12 HPFILT DB11 NC = NO CONNECT TOP VIEW (NOT TO SCALE) AD2S100 PH/OP4 NC SIN NC DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 PH/OP1 PH/OP3 PH/OP2 AGND PH/IP4 PH/IPH3 PH/IP3 PH/IPH2 PH/IP2 PH/IPH1 PH/IP1 OBSOLETE
*The high level input mode can only be selected with MODE2. 12 through 16 must be left unconnected. In this mode, either nominal or high level inputs can be used. there should be no connections to PH/IP1, PH/IP2 and PH/IP3. level signal input operation, select MODE2 only. PH/IPH2, PH/IP4 and PH/IPH3 should be left unconnected. tates the stator coordinates to the rotor reference frame. neous setting of φ in both the Sin and Cos registers. Figure 4. AD2S100 Power Supply Connection
REV. A–8– TIMING DIAGRAMS Busy Output The state of converter is indicated by the state of the BUSY out- put (Pin 44). The BUSY output will go HI at the negative edge of the STROBE input. This is used to synchronize digital input data and load the digital angular rotation information into the device counter. The BUSY output will remain HI for 2 µs, and go LO until the next strobe negative edge occurs. Strobe Input The width of the positive STROBE pulse should be at least 100 ns, in order to successfully start the conversion. The maxi- mum frequency of STROBE input is 366 kHz, i.e., there should be at least 2.73 µs from the negative edge of one STROBE pulse to the next rising edge. This is illustrated by the following tim- ing diagram and table. STROBE BUSY tf tr Figure 7. AD2S100 Timing Diagram in a three phase, nominal level input mode (MODE2). Figure 8. Typical Circuit Configuration Forward and ReverseTransformation The AD2S100 can perform both forward and reverse transfor- mations. The section “Theory of Operation” explains how the chip operates with the core operator e +jφ, which performs a for- ward transformation. The reverse transformation, e –jφ, is not mentioned in the above sections of the data sheet simply to avoid the confusion in the functionality and pinout. However, the reverse transformation is very useful in many different appli- cations, and the AD2S100 can be easily configured in a reverse transformation configuration. Figure 9 shows four different phase input/output connections for AD2S100 reverse transfor- mation operation. –1
3 PHASE – 3 PHASE e–jφ
e+jφ e+jφ e+jφ e+jφ
2 PHASE – 2 PHASE
2 PHASE – 3 PHASE
3 PHASE – 2 PHASE
Cosθ Sinθ Cos(θ +φ) Cos(θ + φ + 120°) Cos(θ + φ + 240°) Cos(θ + 120°) Cos(θ + 240°) Cosθ Sinθ Cosθ Cosθ Cos(θ + 120°) Cos(θ + 240°) Cos(θ + φ) Sin(θ + φ) Cos(θ + φ) Cos(θ + φ + 120°) Cos(θ + φ + 240°) Cos(θ + φ) Sin(θ + φ) Cosθ Cos(θ + 120°) Cos(θ + 240°) Cos(θ – φ) Cos(θ – φ + 120°) Cos(θ – φ + 240°) Cos(θ – φ) Cos(θ – φ + 120°) Cos(θ – φ + 240°) Cosθ Sinθ Cos(θ – φ) Sin(θ – φ) Cosθ Sinθ Cosθ Cos(θ + 120°) Cos(θ + 240°) Cos(θ – φ) Sin(θ – φ) e–jφ e–jφ e–jφ Figure 9. Reverse Transformation Connections