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A2B and the A2B logo are registered trademarks of Analog Devices, Inc. Automotive Audio Bus A2B Transceiver AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without no tice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com A2B BUS FEATURES Line topology Single master, multiple slave Up to 15 m between nodes and up to 40 m overall cable length (see Table 9) Communication over distance Synchronous data Multichannel I2S/TDM to I2S/TDM Synchronous clock, phase aligned in all nodes Low latency slave to slave communication Control and status information I 2C to I2C GPIO and interrupt Bus power or local power slave nodes Configurable with SigmaStudio graphical software tool AEC-Q100 qualified for automotive applications A2B TRANSCEIVER FEATURES Configurable A2B bus master or slave operation I2C interface 8-bit to 32-bit multichannel I2S/TDM interface Programmable I2S/TDM data rate Up to 32 upstream and 32 downstream channels PDM interface Programmable PDM clock rate Up to 4 high dynamic range microphone inputs Simultaneous reception of I 2S data with up to 4 PDM microphones Unique ID register for each transceiver Crossover or straight-through cabling Programmable settings to optimize EMC performance

APPLICATIONS

Hands free and in car communication Active and road noise cancellation Audio/video conferencing systems Figure 1. Functional Block Diagram

Rev. B | Page 2 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) TABLE OF CONTENTS Programmable Settings to Optimize EMC  A Voltage Regulator Current in Master Node or Local  Power Dissipation of A

REVISION HISTORY

1/2020—Rev. A to Rev. B

sume time division multiplexed (TDM) channel content. transceivers as well as I2C to I2C communication over distance. as used for the communication link. Table 1. Product Comparison Guide 2 PDM microphones must be connected to the DRX0/IO5 pin.

Rev. B | Page 6 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) I2S Reduced Rate Slave transceivers can run the I2S/TDM/PDM interface at a reduced rate frequency, with respect to the superframe rate. The reduced rate frequency is derived by dividing the superframe rate from a programmable set of values. Different slave nodes can be configured to run at different reduced I 2S/TDM rates. The transceiver provides an option for a processor to track the full rate audio frame, which contains new reduced rate samples. The IO7 pin can be used as a strobe, and the direction can be configured as an input or output. PULSE DENSITY MODULATION (PDM) INTERFACE The PDM block on the transceiver converts a PDM input stream into pulse code modulated (PCM) data to be sent over the A 2B bus and/or out to the local node through the I2S/TDM port. It supports high dynamic range microphones with high signal-to-noise ratio (SNR) and extended maximum sound pressure level. The PDM interface supports 12 kHz and 24 kHz frame rates in addition to a 48 kHz frame rate and can be used on both master and slave transceivers. Even lower PDM sampling rates (for example, down to 375 Hz) are possible in combination with the reduced rate feature of the transceiver. The cutoff frequency of the high-pass filter in the transceiver PDM block is fixed to 1 Hz. BCLK can be used to clock PDM microphones on a slave, but if PDMCLK/IO7 is used instead, the BCLK frequency can be set to a different frequency using the I 2S/TDM registers. In this case, PDMCLK/IO7 is used as the PDM clock (PDMCLK) to capture PDM input on DRX0/DRX1. The clock rate from PDMCLK is 64× the SYNC frequency. On a master node, BCLK is always an input, so the clock to PDM microphones that are attached to a master typically comes from PDMCLK/IO7. It is possible to use BCLK to drive the PDM clock inputs on a master node, but this restricts the possi- ble TDM settings because BCLK is required to fall within the fBCLK specification in Table 4. BCLK and PDMCLK/IO7 can also be used concurrently to clock PDM microphones at the same frequency and phase alignment, but with opposite polarity. Additionally, a register setting selects whether rising edge data or falling edge data is sampled first. GPIO OVER DISTANCE The transceiver supports general-purpose input/output (GPIO) between multiple nodes without host intervention after initial programming. The host is required only for initial setup of the GPIO bus ports. I/O pins of different nodes can be logically OR or AND gate combined. MAILBOXES The transceiver supports interrupt driven, bidirectional mes- sage exchange between I 2C master devices (microcontrollers) at different slave nodes and the host connected to the master node transceiver in two dedicated mailboxes. The mailboxes can be used to customize handshaking among numerous nodes in a system to coordinate system events, such as synchronizing audio. DATA SLOT EXCHANGE BETWEEN SLAVES Using the DTX0 and DTX1 pins, slave transceivers can selec- tively output upstream or downstream data that originates from other nodes without the need for data slots to be routed through the master node. Receive data channels can be skipped based on a programmable offset, when the data is presented as upstream or downstream slots to the A 2B bus. CLOCK SUSTAIN STATE In the clock sustain state, audio signals of locally powered slave nodes are attenuated in the event of lost bus communication. When the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node transceiver enters the sustain state and, if enabled, signals this event to a GPIO pin. In the clock sustain state, the phase-locked loop (PLL) of the slave node transceiver continues to run for 1024 SYNC periods, while attenuating the I 2S DTX0 to DTX1 data from the current value to 0. After the 1024 SYNC periods, the slave node trans- ceiver resets and reenters the power-up state. PROGRAMMABLE SETTINGS TO OPTIMIZE EMC PERFORMANCE The following programmable features can be used to improve electromagnetic compatibility (EMC) performance. Programmable LVDS Transmit Levels The low voltage differential signal (LVDS) transmitter can be set to transmit the signal at high, medium, or low levels. Higher transmit levels yield greater immunity to EMI, whereas lower transmit levels can reduce emissions from the twisted-pair cables that link A 2B bus nodes together. The improved LVDS receiver (compared to other members of the AD242xW family) maintains robust operation when transmit levels are lowered. Spread-Spectrum Clocking Spread-spectrum clocking can be used to reduce narrow-band emissions on a printed circuit board (PCB). Spread-spectrum clocking is disabled on the transceiver by default, but spread- spectrum clocking for all internal clocks can be enabled during discovery by a register write. If spread-spectrum clocking support is enabled for the internal clocks, spread-spectrum clocking can also be enabled for both the I 2S interface and the programmed CLKOUTs. Enabling spread-spectrum clocking for internal clocks, CLKOUTs, and the I 2S interface may reduce narrow-band emissions by several dB on a particular node. When spread-spectrum clocking is enabled on a clock output, the time interval error (TIE) jitter on that clock increases. Unique ID Each transceiver contains a unique ID, which can be read from registers using software. If a read of the unique ID fails, an inter- rupt can be generated.

AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Rev. B | Page 7 of 38 | January 2020 Support for Crossover or Straight Through Cabling Straight through cables can be supported by swapping the dc coupling at the B-side connector. See the Designer Reference section for details about the reference schematics. Data Only and Power Only Bus Operation The A2B bus can be operated without closing the PMOS switch to send a dc bias downstream. Conversely, a dc bias can also be sent downstream without the presence of data. These features are available for debug purposes only.

Rev. B | Page 8 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) SPECIFICATIONS For information about product specifications, contact your Analog Devices, Inc. representative. OPERATING CONDITIONS Parameter Conditions Min Nominal Max Unit Power Supplies VDVDD Digital Core Logic Supply Voltage 1.70 1.90 1.98 V VIOVDD Digital Input/Output (I/O) Supply Voltage 3.3 V I/O 3.0 3.3 3.63 V 1.8 V I/O 1.7 1.9 1.98 V VPLLVDD Phased-Locked Loops (PLL) Supply Voltage 1.7 1.9 1.98 V VTRXVDD Transceiver Supply Voltage Applies to the ATRXVDD and BTRXVDD pins 3.0 3.3 3.63 V Voltage Regulator (VREG1, VREG2) VVIN Regulator Input Supply Voltage Specific ation must be met at the VIN pin of each A2B bus transceiver 3.7 9.0 V VRST VVIN Chip Reset Assertion Voltage Threshold VVIN dropping 2.65 2.97 V VRSTN VVIN Chip Reset Deassertion Voltage Threshold VVIN rising 3.11 3.25 V Digital I/O V IH 1 Applies to PDMCLK/IO7, BCLK, SYNC, DTX0/IO3, DTX1/IO4, DRX0/IO5, DRX1/IO6 , ADR1/IO1, ADR2/IO2, IRQ/IO0 pins. High Level Input Voltage V IOVDD = 1.98 V 0.7 × VIOVDD V VIOVDD = 3.63 V 2.2 V VIL 1 Low Level Input Voltage V IOVDD = 1.70 V 0.3 × VIOVDD V VIOVDD = 3.00 V 0.8 V VIH_I2C 2 Applies to SDA and SCL pins. VIOVDD = 3.63 V, 1.98 V 0.7 × VIOVDD V VIL_I2C VIOVDD = 3.00 V, 1.70 V 0.3 × VIOVDD V Temperature T J Junction Temperature TAMBIENT = 0°C to 70°C 0 105 °C TJ Junction Temperature TAMBIENT = –40°C to +85°C –40 +105 °C AUTOMOTIVE USE ONLY T J Junction Temperature (Automotive Grade) TAMBIENT = –40°C to +105°C –40 +1253 3 Automotive application use profile only. Not supported for nonautomotive use. Co ntact Analog Devices, Inc. for more information .

AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Rev. B | Page 9 of 38 | January 2020

ELECTRICAL CHARACTERISTICS

Parameter Conditions Min Typ Max Unit Current IDVDD Digital Core Logic Supply Current V DVDD = 1.98 V 9.0 10.5 12.0 mA IPLLVDD PLL Supply Current VPLLVDD = 1.98 V 0.5 1.1 1.5 mA ITRXVDD 1 Master and last slave only consume half the transceiver current because only one of the two TRX blocks is used. Transceiver Supply Current TX enabled, RX disabled, 100% duty cycle (ITXVDD), VTRXVDD = 3.63 V 9.5 12.0 13.0 mA TX disabled, RX enabled, 100% duty cycle (IRXVDD), VTRXVDD = 3.63 V 2 . 22 . 8 3 . 5m A TX disabled, RX disabled, 0% activity level, VTRXVDD = 3.63 V 1 . 01 . 7 2 . 5m A Voltage Regulator (VREG1, VREG2) VVOUT1 VREG1 Output Voltage 1.80 1.90 1.98 V VVOUT2 VREG2 Output Voltage 3.15 3.30 3.45 V IVOUT1 2 In a bus powered system, IVOUT has a direct impact on IVSSN and VVIN in other nodes. For more information, see the Power Analysis section. VREG1 Output Current 40.0 mA IVOUT2 2 VREG2 Output Current 50.0 mA IVEXT1 3, 4 3 Consider the package thermal limits when dissipating c urrent above typical limits. For more information, see the Thermal Characteristics section. 4 Must comply with IVOUT1 and IVOUT2 maximum. VREG1 External Device Current I VOUT1 – IPLLVDD – IDVDD – IIOVDD current available to external device 20 mA IVEXT2 3, 4 VREG2 External Device Current I VOUT2 – ITRXVDD current available to external device 20 mA VOUT1/VIN Line Regulation VVIN = 3.7 V to VIN 0 0.017 0.055 %/V VOUT2/VIN Line Regulation VVIN = 3.7 V to VIN 0.013 0.030 0.060 %/V VVIN = 5.0 V to 8 V –0.025 +0.005 +0.055 %/V VOUT1/IOUT1 Load Regulation VVIN = 5.0 V, IVOUT1 = 1 mA to 40 mA 0.009 0.017 %/mA VOUT2/IOUT2 Load Regulation VVIN = 5.0 V, IVOUT2 = 1 mA to 50 mA 0.008 0.015 %/mA IVINQ Quiescent Current VVIN =VIN, IVOUT1 = 0 mA, IVOUT2 = 0 mA 530 600 750 μA IVIN Operational Current VVIN = VIN, IVOUT1 = 8 mA, IVOUT2 = 20 mA 29 mA CLoad1 VREG1 Load Capacitance 1.0 25 μF CLoad2 VREG2 Load Capacitance 2.2 25 μF Digital I/O I IH Input Leakage, High VIOVDD = 3.63 V, VIN = 3.63 V 10.0 μA IIL Input Leakage, Low VIOVDD = 3.63 V, VIN = 0 V 10.0 μA IOZH_I2C 5 Applies to SDA and SCL pins. Three-State Leakage Current V IOVDD = 1.9 V, VIN = 3.63 V 10.0 μA VOH1.9 High Level Output Voltage V IOVDD = 1.70 V, IOH = 1 mA 1.35 V VOH3.3 High Level Output Voltage V IOVDD = 3.00 V, IOH = 1 mA 2.40 V VOL 6 Applies to BCLK, SYNC, DTX0/IO3, DTX1/IO4, DRX0/IO5, DRX1/IO6, ADR1/IO1, ADR2/IO2, IRQ/IO0, PDMCLK/IO7 pins. Low Level Output Voltage V IOVDD = 3.00 V, IOL = 1 mA 0.40 V VOL 6 Low Level Output Voltage V IOVDD = 1.70 V, IOL = 1 mA 0.40 V VOL_I2C 5, 7 7 The minimum IOL current is lower than the I2C specification because the SDA and SCL pins are designed for a limited number of I2C attached slave devices. I2C Low Level Output Voltage V IOVDD = 3.00 V, IOL = 1.5 mA 0.40 V VOL_I2C 5, 7 I2C Low Level Output Voltage V IOVDD = 1.70 V, IOL = 1.5 mA 0.40 V CPD Pin Capacitance 4.8 5 pF Negative Bias Switch IVSSN Internal VSSN Switch Current AD2426(W)/AD2427(W)/AD2428(W) 300 mA IVSSN Internal VSSN Switch Current AD2420(W)/AD2429W 100 mA RVSSN Internal VSSN On Resistance 1.2 Ω

Table 2. Differential Input/Output

Table 3. Clock and Reset Timing (A 2B Master) 1 Only consecutive missed SYNC or SCF transitions for the specified duration result in a reset. Table 4. Pulse Density Modulation Microphone Input Timing Table 5. GPIO Timing

Table 6. I 2C Port Timing Figure 9. I 2C Port Timing

Table 7. I 2S Timing 1 Referenced to sample edge. when the A2B slave node is receiving and A2B master node is transmitting. In these modes, the maximum BCLK frequency of 50 MHz cannot be achieved.

tion before input signals are driven by external devices. Table 8. Power-Up Timing Figure 13. Power-Up Se quencing Timing with Externally Supplied VDVDD and VIOVDD

Table 9. A 2B System Specifications AD2428(W)Mastered System 40 m total, 15 m between nodes. AD2429(W) Mastered System 10 m total, 5 m between nodes. AD2428(W) Mastered System 11 nodes (1 master node and 10 slave nodes). AD2429(W) Mastered System Three nodes (1 master node and 2 slave nodes). AD2426(W)/AD2427(W)/AD2428(W) 1 64 total, up to 32 upstream and 32 downstream slots, depending upon system design. AD2420(W): 2 upstream slots, depending upon system design. Number of Audio Channels per Slave Node Individually programmable 0 to 32 upstream channels and 0 to 32 downstream channels. Synchronous A2B Data Slot Size 8, 12, 16, 20, 24, 28, or 32 bits to match I2S/TDM data-word lengths. Same slot size for all nodes. compressed data over the A2B bus for 16-, 20-, or 24-bit I2S/TDM word lengths. (fS) of 1× (48 kHz), 2× (96 kHz) or 4× (192 kHz), individually configured per slave. I2S/TDM data channels as the 1× sampling frequency (f SYNCM) interface to the host. 2 kHz, 1.71 kHz, or 1.5 kHz at a low latency 48 kHz superframe rate. Discovery Time Less than 35 ms per node. Much less than 350 ms for total system startup in a system with 10 nodes. Includes register initialization. Bit Error Detection Robust error detection for control data and status data with 16-bit cyclic redundancy check (CRC). synchronous data slots is possible. ISO 7637-3) and emissions (CISPR25). System ESD See IEC ESD ratings in Table 12 for terminals. 1 See the AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A2B Transceiver Technical Reference for more information.

Figure 18. PDM Out of Band Frequency Response (48 kHz Output) Table 11. PDM Interface Pe rformance Specifications 1 The PDM start-up time is the time for the filters to settle after the PDM block is enabled. It is the time to wait before data is guaranteed to meet the specified performance.

where TA = ambient temperature (°C). design considerations when an external heat sink is required. Table 14. See JESD51-13 for detailed parameter definitions. The junction to board measurement complies with JESD51-8. Table 12. Absolute Maximum Ratings

1 Applies to BCLK, SYNC, DTX0/IO3, DTX1/DRX1/IO4, DRX0/IO5, DRX1/IO6,

IRQ/IO0, ADR1/IO1, ADR2/IO2, PDMCLK/IO7. 3 Applies when nominal VIOVDD is 3.3 V. 4 Applies when nominal VIOVDD is 1.8 V. 6 CON1-A and CON1-B are connectors. 7 For more information, see the following description and Table 13. Table 13. Total Current Pin Groups

1 IRQ/IO0, ADR1/IO1, ADR2/IO2

2 BCLK, SYNC, DTX0/IO3, DTX1/DRX1/IO4, DRX0/IO5,

Table 14. Thermal Characteristics

input/output (GPIO) pin with interrupt request capability. as a master clock for connected ADCs and DACs or to synchronize switching voltage regulators. supplied by the VOUT1 pin or VOUT2 pin, source IOVDD with an external supply. 10 BCLK D_IO PDMCLK Bit Clock. Digital input in master mode. Digital output in slave mode. for PDM microphones (the PDMCLK/IO7 pin can also be used). 11 SYNC D_IO None Synchronization Signal. Digital input in master mode. Digital output in slave mode. all clocking information for itself and for the A 2B bus from this input. When this pin stops toggling, the A2B bus resets after a delay. For more information, see Table 3. chip resets due to a missing synchronization signal or low supply voltage. For the ADW2420W, AD2426W, and AD2427W, this pin is GPIO only (IO3). DRX1/IO6 pins are used to receive PDM microphone data. This pin serves as the IO4 general-purpose I/O pin when DTX1 and DRX1 functions are disabled. impedance when the chip resets due to a missing synchronization signal or low supply voltage. For the AD2420W, AD2426W, and AD2427W, this pin is GPIO only (IO4). when the chip resets due to a missing synchronization signal or low supply voltage. For the AD2420W, AD2426W, and AD2427W, the DRX0 function is not supported. Table 15. AD2420(W)/AD2426(W)/AD2427 (W)/AD2428(W)/AD2429(W) Pin Function Descriptions (Continued) D_IO = digital input/output, N/A = not applicable.

when the chip resets due to a missing synchronization signal or low supply voltage. For the AD2420W, AD2426W, and AD2427W, the DRX1 function is not supported. 162 PDMCLK/IO7 D_IO RRSTRB PDM Microphone Clock Output. runs at 64× the SYNC frequency regardless of the BCLK rate used by the host. PDM microphones (PDMCLK), but BCLK can also be used. impedance when the chip resets due to a missing synchronization signal or low supply voltage. 17 ACM A_IN None Common-Mode Input for Bidirectional, Differential A 2B Line Transceiver A. towards the master. Pin 18 is self biased. towards the master. Pin 19 is self biased. by VOUT2. Supply the ATRXVDD pin for a master, last slave, or daisy-chained slave. ential A2B l ine dr iver and R eceiver B, which is d irec ted towards the last slave. This pin is self biased. A2B line driver and Receiver B, which is directed towards the last slave. This pin is self biased.

24 BCM A_IN None For the AD2427W, AD2428W, and AD2429W, this is the common-mode input for bidirectional,

differential A2B Line Transceiver B. automatically opens (SWP goes high) under critical fault conditions. D_IO = digital input/output, N/A = not applicable.

Operating Conditions section) for an on-chip low dropout voltage regulator. VOUT1 to VSS with a 4.7 μF capacitor. exposed pad on the bottom of the package and must be connected to GND. 1 See the AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A2B Transceiver Technical Reference for more information about configuring pins for alternate functions. 2 If the listed functions for this pin are not required, do not connect this pin. D_IO = digital input/output, N/A = not applicable.

AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Rev. B | Page 29 of 38 | January 2020 Peripheral Supply Current Peripheral components that are external to the transceiver also can be supplied through the voltage regulator outputs of VVOUT1 and VVOUT2. VVOUT1 can supply the current specified as IVEXT1 to external devices. VVOUT2 can supply the current specified as IVEXT2 to external devices. When bus powered, peripheral supply current draw has a direct impact on other nodes in the system. It is important to stay within the thermal package limits and not exceed the specifica- tion limits of IVSSN and VVIN in any of the A2B bus nodes. Digital Logic Supply Current The digital logic supply current I DVDD is a combination of static current consumption and digital TX/RX current. A2B Bus TX/RX Current The level of A2B bus activity directly influences current con- sumption on both the LVDS transceivers related to A2B transmitter and receiver processing. LVDS Transmitter and Receiver Supply Currents The current ITRXVDD depends on ITXVDD and IRXVDD at 100% activ- ity level and A2B bus activity:

  • Downstream LVDS transceiver current
  • B t r a n s c e i v e r IBTXVDD LVDS TX current results from downstream TX activity level of the current node.
  • A t r a n s c e i v e r IARXVDD LVDS RX current results from downstream activity level of the previous node.
  • Upstream LVDS transceiver current
  • A t r a n s c e i v e r IATXVDD LVDS TX current results from  A side upstream activity level of the current node.
  • B t r a n s c e i v e r IBRXVDD LVDS RX current results from upstream activity level of the next in line node. Downstream/Upstream Activity Level The activity level for downstream data of TRX B is determined by the following:
  • Header bits for downstream. A 2B systems use 64 down- stream header bits referred to as a synchronization control frame (SCF).
  • The number of downstream data bits transmitted in  a node = the number of downstream transmitted slots × (bits per slot + parity bit) where the parity bit = 1. The number of downstream transmitted slots does not include the locally consumed slots.
  • B side downstream transmitte r activity level of a node. (SCF bits + number of downstream transmitted data bits) ÷ 1024. The activity level for upstream data of TRX A is determined by the following:
  • Header bits for upstream. (SRF bits + total number of received downstream data bits) ÷ 1024.
  • The number of upstream data bits transmitted in a node = number of upstream transmitted slots × (bits per slot + parity bit) where the parity bit = 1. The number of upstream transmitted slots is the sum of received upstream slots and locally contributed slots.
  • A side upstream transmitte r activity level of a node.  (SRF bits + number of transmitted upstream data bits) ÷ 1024. LVDS Transmitter and Receiver Idle Current The idle current, I TRXVDD_IDLE, depends on ITXVDD and IRXVDD at 0% activity level and A2B bus idle time.
  • B transceiver idle current. B Transceiver I BTRXVDD_IDLE LVDS current results from B transceiver idle time.
  • A t r a n s c e i v e r i d l e c urrent. A Transceiver IATRXVDD_IDLE LVDS current results from A transceiver idle time.
  • B transceiver idle time. B transceiver idle time is the time when both the TX and RX of the B transceiver are idle. The idle time of the B transceiver is derived by eliminating the following activity levels from the B transceiver frame cycle:
  • B transceiver downstream activity level of the current node.
  • A transceiver upstream activity level of the next in line node.
  • A transceiver idle time is the time when both the TX and RX of the A transceiver are idle. The idle time of the A transceiver is derived by eliminating the following activity from the A transceiver frame cycle:
  • A transceiver upstream activity level of the current node.
  • B transceiver downstream activity level of previous node. The sum of the LVDS transceiver currents is ITRXVDD = IBRXVDD + IBTXVDD + IARXVDD + IATXVDD +  IBTRXVDD_IDLE + IATRXVDD_IDLE VREG1 AND VREG2 OUTPUT CURRENTS Voltage regulator output currents are governed by the following equations: I VOUT2 is the current from VVOUT2 which is the sum of the LVDS transmitter and receiver supply currents, peripheral supply cur- rents, and I/O current. I VOUT2 = ITRXVDD + IIOVDD+ IVEXT2 IVOUT1 is the current from the VOUT1 pin which is the sum of PLL supply current, IPLLVDD, digital logic supply current IDVDD, peripheral supply current, IVEXT1, and I2S/TDM/PDM I/O cur- rent IIOVDD. IVOUT1 = IPLLVDD + IVEXT1 + IDVDD + IIOVDD IIOVDD in a slave node can be sourced by either IVOUT1 or IVOUT2 but not both, depending on whether IIOVDD is supplied from VVOUT1 or VVOUT2.

state while maintaining clock synchronization between nodes.

  • Downstream activity level = 19 ÷ 1024 = 1.9% Upstream activity level = 0% The digital transceiver current, including the LVDS TX and RX current, are subject to the activity levels. The LVDS TX and RX current also are subject to idle current during the bus idle time. Control Mode In control mode, there are no data channels in a superframe. The superframe only has the 64-bit SCF and SRF in the frame with the control data embedded in the header bits. Therefore, the A 2B bus power is less when compared to normal mode, which has data channels in the superframe. Using the equations in the Downstream/Upstream Activity Level section, the bus activity level in control mode is,
  • Bus activity level downstream = 64 ÷ 1024 = 6.3%
  • Bus activity level upstream = 64 ÷ 1024 = 6.3% The LVDS TX and RX current also are subject to idle current during the bus idle time. THERMAL POWER When calculating power, system designers must consider ther- mal power. Thermal power calculations are based on the package thermal characteristics, shown in the following equation: JA = thermal resistance (TJ – TA) ÷ power [°C/W] with airflow = 0 m/s Table 17 provides the thermal power allowance example. These values are derived from a JEDEC standard 2S2P test board. JA values vary significantly and depend on system design and con- ditions. For the example calculation in Table 17, the JA value provided is determined using the JEDEC standard conditions. In this example (Table 17), a slave node with 292 mW of power dissipation is used to provide the maximum estimated power. The margin is calculated by subtracting the maximum estimated power from the thermal power allowance.

Table 17. Thermal Power Allowance Example

typical node configurations. environment and support full line diagnostics functionality. across power and communication wires. bias, which is supplied through ac signal blocking inductors. damage prevention under line fault conditions. diagnostics to function correctly. by diode voltage drops and the on resistance of the PMOS. resistor to ground (R12), and the power switch enable circuit. Table 18. V Table 19. V VIN to VSENSEVoltage Dependencies Figure 37. Optional Power Supply Enable Circuit with Optocoupler

Rev. B | Page 34 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) LAYOUT GUIDELINES The transceivers are highly integrated devices, comprising both digital sections for audio data, clocks, PLL, and analog A2B transceiver sections. Use the following design rules to maximize performance and signal integrity:

  • Solder the exposed paddle underneath the transceiver effectiv ely to the PCB where it is locally connected to the ground plane. Figure 38 shows transceiver foot print, rec- ommended solder mask (matching exposed paddle), paste mask (dividing exposed paddle), and stitching of the ground plane. The solder paste under the exposed paddle is split into four square areas, which minimizes solder wicking through uncovered thermal vias and prevents sliding or tilting of the chip during solder reflow. See Soldering Considerations for Exposed-Pad Packages (EE-352), on the Analog Devices web site. The exposed paddle is used for a thermal pathway as well as for electrical connection.
  • Place power supply decoupling capacitors as close as possi- ble to the transceiver chip with the smallest value capacitor being closest to the pin.
  • Route all traces as short as possible , especially the AP/AN and BP/BN signals. Symmetrically route the AP/AN and BP/BN signals to sup- press EMC. Match routing parasitic capacitance and inductance.
  • Symmetrically shield the AP /AN and BP/BN signals with groun d. Use shields that are at least 0.5 mm wide and stitched generously with vias to the GND plane. Symmetry is best achieved with flooded plane areas.
  • Do not route switching signals or power supply traces next to or underne ath the AP/AN and BP/BN signals.
  • Avoid using trace stubs, especially if they create an asym- metry on the AP/AN and BP/BN signals. Symmetrically route into and out of pads rather than branch out.
  • Differential impedance trace of the AP/AN and BP/BN sig- nals should be 100 Ω ± 10% (10 MHz to 100 MHz) on both sides of the common-mode choke.
  • Avoid unnecessary layer tr ansitions for the AP/AN and BP/BN signals. Match ne cessary layer transitions for differ- ential signals.
  • Use an impedance of 50 Ω ± 10% to ground on all traces.
  • Magnetically separate comm on-mode chokes from each other by at least 2 mm.
  • Do not route ground or other signals on any layer under- neath the common-mode chokes. Extend this exclusion at leas t 2 mm from between the pads. For shielded wires, connect the shield to the local ground.
  • Place one side of the inductors in the signal path and bridge dc signals to the power and ground nets.
  • Place termination resistors sy mmetrically and close to the common-mode chokes. Where possible, flood unused PCB areas with connected ground planes on all layers.
  • Stitch ground planes at least every 5 mm.
  • Do not obstruct power supply and ground return paths by vias.
  • Use series resistors (≥33 Ω) near the source of clock and fast data signals. Also consider footprints for small filter capacitors f or such signal traces.
  • Avoid using right angle bends in signal routing. Use rounded or 45 degree mitered bends instead.
  • Use shortest possible signal pa th on connectors (inner row of multirow, right angled connectors).
  • On multipin connectors, provide at least 3 mm spacin g ar ound differential A2B pin pairs to ensure that A2B signal pai rs are closer to each other than to adjacent signals. The spa cing improves EMC performance. Use low impedance static signals (ground) symmetrically o n connector pins adjacent to the A2B bus pairs when tight spa cing is required.

Figure 38. Transceiver Footprint

Figure 39. 32-Lead Lead Frame Chip Scale Package [LFCSP_SS] Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP]

0.05 MAX

0.02 NOM

0.203 REF

0.20 MIN

3.50 REF

0.20 REF

cific Automotive Reliability reports for these models. Table 20. Automotive Products 2 W = Qualified for Automotive Applications. 3 RL = Supplied on Tape and Reel. 4 For model numbers ending in xx or xx-RL, xx denotes the die revision. specification which is the only temperature specification.

Rev. B | Page 38 of 38 | January 2020 ©2020 Analog Devices, Inc. All rights reserved. Trademarks and registered tradema rks are the property of thei r respective owners. D16813-0-1/20(B) AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ORDERING GUIDE Model1 1 Z = RoHS Compliant Part. Temperature Range2 2 Referenced temperature is ambient temperature. The am bient temperature is not a specification. See the Operating Conditions section for junction temperature (TJ) specification which is the only temperature specification. Description Package Option AD2420KCPZ 0°C to +70°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12 AD2420BCPZ –40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12 AD2426KCPZ 0°C to +70°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12 AD2426BCPZ –40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12 AD2427KCPZ 0°C to +70°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12 AD2427BCPZ –40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12 AD2428KCPZ 0°C to +70°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12 AD2428BCPZ –40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12 AD2429KCPZ 0°C to +70°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12 AD2429BCPZ –40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12