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SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. SHARC Processor ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without no tice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip ROM Up to 450 MHz operating frequency Code compatible with all other members of the SHARC family The ADSP-2148x processors are available with unique audio- centric peripherals, such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more For complete ordering information, see Ordering Guide on Page 70 AEC-Q100 qualified for automotive applications Figure 1. Function al Block Diagram

5 Stage

Rev. H | Page 2 of 71 | February 2020 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 TABLE OF CONTENTS

REVISION HISTORY

2/2020—Rev. G to Rev. H

innovative digital applications interface (DAI). Table 1. Processor Benchmarks

1024 Point Complex FFT

1 Assumes two files in multichannel SIMD mode

Table 2. ADSP-2148x Family Features

2 Yes No

3 Yes (16-bit) AMI Only Yes (16-bit)

1 See Ordering Guide on Page 70. combination support varies depending upon the ch ip version and the system configurations. Visit www.analog.com for complete information. 4 Some models have –140 dB performance. For more information, see Ordering Guide on page 70. 5 Only available up to 400 MHz. See Ordering Guide on Page 70 for details.

Rev. H | Page 4 of 71 | February 2020 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 The diagram on Page 1 shows the two clock domains that make up the ADSP-2148x processors. The core clock domain contains the following features:

• Two processing elements (P Ex, PEy), each of which com- prises an ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting 2x64-bit data transfers between memory and the core at every core pro- cessor cycle
• One periodic interval timer with pinout
• On-chip SRAM (5 Mbit) and mask-programmable ROM (4 Mbit)
• JTAG test access port for em ulation and boundary scan. The JTAG provides software debug through user break- points which allows flexible exception handling. The block diagram of the ADSP-2148x on Page 1 also shows the peripheral clock domain (also known as the I/O processor) which contains the following features:
• I O D 0 ( p e r i p h e r a l D M A ) a n d IOD1 (external port DMA) buses for 32-bit data transfers
• Peripheral and external port buses for core connection
• External port with an AMI and SDRAM controller
• 4 u n i t s f o r P W M c o n t r o l
• 1 memory-to-memory (MTM) unit for internal-to-internal memory transfers
• Digital applications interface that includes four precision clock generators (PCG), an input data port (IDP/PDAP) for serial and parallel interconnects, an S/PDIF receiver/transmitter, four asynchronous sample rate con- verters, eight serial ports, and a flexible signal routing unit (DAI SRU).
• Digital peripheral interface that includes two timers, a 2-wire interface (TWI), one UART, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG), pulse width modulation (PWM), and a flexible signal routing unit (DPI SRU2). As shown in the SHARC core block diagram on Page 5, the processor uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. With its SIMD computational hard- ware, the processors can perform 2.7 GFLOPS running at 450 MHz. FAMILY CORE ARCHITECTURE The ADSP-2148x is code compatible at the assembly level with the ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2148x shares architectural features with the ADSP-2126x, ADSP- 2136x, ADSP-2137x, ADSP-2146x and ADSP-2116x SIMD SHARC processors, as shown in Figure 2 and detailed in the fol- lowing sections. SIMD Computational Engine The ADSP-2148x contains two computational processing ele- ments that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and reg- ister file. PEx is always active, and PEy may be enabled by setting the PEYEN mode bit in the MODE1 register. SIMD mode allows the processor to execute the same instruction in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms. SIMD mode also affects the way data is transferred between memory and the processing elements because twice the data bandwidth is required to sustain computational operation in the processing elements. Therefore, entering SIMD mode also dou- bles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each memory or reg- ister file access. Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all opera- tions in a single cycle and are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both pro- cessing elements. These computation units support IEEE 32-bit single-precision floating-point, 40-bit extended precision float- ing-point, and 32-bit fixed-point data formats. Timer The processor contains a core timer that can generate periodic software interrupts. The core timer can be configured to use FLAG3 as a timer expired signal. Data Register File Each processing element contains a general-purpose data regis- ter file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the processor’s enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. Context Switch Many of the processor’s registers have secondary registers that can be activated during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result registers all have secondary registers. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register.

Toggle, Test, XOR) for all peripheral registers (control/status). registers contain hardware to handle the data width difference. gram memory (PM) bus transfers both instructions and data. (from the cache), all in a single cycle. addressing and implementing circular data buffers in hardware. are commonly used in digital filters and Fourier transforms. Figure 2. SHARC Co re Block Diagram

tion tools to create these more efficient opcodes.

3 Mbits of internal RAM (Table 3) and the ADSP-21486,

Table 3. Internal Memory Spac e (3 MBits—ADSP-21483/ADSP-21488) sales representative for additional details.

that retrieves 32-bit memory. after the correct key is scanned. the IOD0/1 buses (2 × 32-bit, PCLK speed). external ports are comprised of the following modules.

• An Asynchronous Memory Interface which communicates with SRAM, FLASH, and other devices that meet the stan- dard asynchronous SRAM access protocol. The AMI supports 6M words of external memory in bank 0 and 8M words of external memory in bank 1, bank 2, and bank 3.
• A SDRAM controller that suppo rts a glueless interface with any of the standard SDRAMs. The SDC supports 62M words of external memory in bank 0, and 64M words of external memory in bank 1, bank 2, and bank 3. NOTE: This feature is not available on the ADSP-21486 product.

Table 4. Internal Memory Space (5 MBits—ADSP-21486/ADSP-21487/ADSP-21489)

• Arbitration logic to coordinate core and DMA transfers between internal and external memory over the external port. Non-SDRAM external memory address space is shown in Table 5. External Port The external port provides a high performance, glueless inter- face to a wide variety of industry-standard memory devices. The external port, available on the 176-lead LQFP, may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. The first is an SDRAM controller for connection of industry-stan- dard synchronous DRAM devices while the second is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired com- bination of synchronous and asynchronous device types. Asynchronous Memory Controller The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with dif- ferent timing parameters, enabling connection to a wide variety of memory devices including SRAM, flash, and EPROM, as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 6M word window and banks 1, 2, and 3 occupy a 8M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. SDRAM Controller The SDRAM controller provides an interface of up to four sepa- rate banks of industry-standard SDRAM devices at speeds up to f SDCLK. Fully compliant with the SDRAM standard, each bank has its own memory select line (MS0–MS3), and can be configured to contain between 4M bytes and 256M bytes of memory. SDRAM external memory address space is shown in Table 6. NOTE: this feature is not available on the ADSP-21486 model. A set of programmable timing parameters is available to config- ure the SDRAM banks to support slower memory devices. Note that 32-bit wide devices are not supported on the SDRAM and AMI interfaces. The SDRAM controller address, data, clock, and control pins can drive loads up to distributed 30 pF. For larger memory sys- tems, the SDRAM controller external buffer timing should be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF. Note that the external memory bank addresses shown are for normal-word (32-bit) accesses. If 48-bit instructions as well as 32-bit data are both placed in the same external memory bank, care must be taken while mapping them to avoid overlap. SIMD Access to External Memory The SDRAM controller on the processor supports SIMD access on the 64-bit EPD (external port data bus) which allows access to the complementary registers on the PEy unit in the normal word space (NW). This removes the need to explicitly access the complimentary registers when the data is in external SDRAM memory. VISA and ISA Access to External Memory The SDRAM controller on the ADSP-2148x processors sup- ports VISA code operation which reduces the memory load since the VISA instructions are compressed. Moreover, bus fetching is reduced because, in the best case, one 48-bit fetch contains three valid instructions. Code execution from the tra- ditional ISA operation is also supported. Note that code execution is only supported from bank 0 regardless of VISA/ISA. Table 7 shows the address ranges for instruction fetch in each mode. Pulse-Width Modulation The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM wave- forms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four PWM waveforms). The entire PWM module has four groups of four PWM outputs generating 16 PWM outputs in total. Each PWM group pro- duces two pairs of PWM signals on the four PWM outputs.

Table 5. External Memory for Non-SDRAM Addresses Table 6. External Memory for SDRAM Addresses Table 7. External Bank 0 Instruction Fetch

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Rev. H | Page 9 of 71 | February 2020 The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single-update mode or double-update mode. In single-update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetri- cal about the midpoint of the PWM period. In double-update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. PWM signals can be mapped to the external port address lines or to the DPI pins. MediaLB The automotive models of the ADSP-2148x processors have an MLB interface which allows the processor to function as a media local bus device. It includes support for both 3-pin as well as 5-pin media local bus protocols. It supports speeds up to 1024 FS (49.25 Mbits/sec, FS = 48.1 kHz) and up to 31 logical channels, with up to 124 bytes of data per media local bus frame. For a list of automotive models, see Automotive Products on Page 69. Digital Applications Interface (DAI) The digital applications interface (DAI) allows the connection of various peripherals to any of the DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU). The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be intercon- nected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with noncon- figurable signal paths. The DAI includes eight serial ports, four precision clock genera- tors (PCG), a S/PDIF transceiver, four ASRCs, and an input data port (IDP). The IDP provides an additional input path to the SHARC core, configurable as either eight channels of serial data, or a single 20-bit wide synchronous parallel data acquisi- tion port. Each data channel has its own DMA channel that is independent from the processor’s serial ports. Serial Ports (SPORT s) The ADSP-2148x features eight synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports can support up to 16 transmit or 16 receive DMA channels of audio data when all eight SPORTs are enabled, or four full duplex TDM streams of 128 channels per frame. Serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated DMA chan- nels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT pro- vides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in five modes:

• Standard serial mode
• M u l t i c h a n n e l ( T D M ) m o d e 2S mode
• P a c k e d I2S mode
• Left-justified mode S/PDIF-Compatible Digital Audio Receiver/Transmitter The S/PDIF receiver/transmitter has no separate DMA chan- nels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/transmitter can be formatted as left-justified, I2S or right-justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources, such as the SPORTs, external pins, or the precision clock generators (PCGs), and are controlled by the SRU control registers. Asynchronous Sample Rate Converter (SRC) The asynchronous sample rate converter contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 128 dB SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Input Data Port The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive audio channels in I 2S, left-justified sample pair, or right-justified mode. The IDP also provides a parallel data acquisition port (PDAP), which can be used for receiving parallel data. The PDAP port has a clock input and a hold input. The data for the PDAP can be received from DAI pins or from the external port pins. The PDAP supports a maximum of 20-bit data and four different packing modes to receive the incoming data. Precision Clock Generators The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A B, C, and D, are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair.

DAI as well as the DPI pins. PWM modules (PWM3–1), and two general-purpose timers. nous serial interface, supporting both master and slave modes.

• PIO (programmed I/O)—The pr ocessor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.
• DMA (direct memory access)—The DMA controller trans- fers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. Timers The ADSP-2148x has a total of three timers: a core timer that can generate periodic software interrupts and two general- purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes:
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watchdog mode The core timer can be configured to use FLAG3 as a timer expired signal, and the general-purpose timers have one bidirec- tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A sin- gle control and status register enables or disables the general- purpose timer. 2-Wire Interface Port (TWI) The TWI is a bidirectional 2-wire, serial bus used to move 8-bit data while maintaining compliance with the I 2C bus protocol. The TWI master incorporates the following features:
• 7-bit addressing
• Simultaneous master and slave operation on multiple device systems with support for multi master data arbitration
• Digital filtering and timed event processing
• 100 kbps and 400 kbps data rates
• Low interrupt rate I/O PROCESSOR FEATURES The I/O processors provide up to 65 channels of DMA, as well as an extensive set of peripherals. DMA Controller The processor’s on-chip DMA controller allows data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously exe- cuting its program instructions. DMA transfers can occur between the ADSP-2148x’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the PDAP, or the UART. The DMA channel summary is shown in Table 8. Programs can be downloaded to the ADSP-2148x using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers and DMA chaining for automatic linked DMA transfers.

Table 8. DMA Channels

(and hence to external memory) with limited core interaction. erator runs at the peripheral clock frequency. data, and four MAC units. A controller manages the accelerator. The FIR accelerator runs at the peripheral clock frequency. erator runs at the peripheral clock frequency. that system software might be out of control. feature is available on the 176-lead package only. options and power supply issues. package and Table 10 for the 100-lead package. extended to also act as the input for initiating a Running Reset. For more information, see the hardware reference manual. nal supply pins must be connected to the same power supply. power and ground planes for VDD_INT and GND.

450 MHz core frequency operation without a significant

device to enable enhanced operating frequency up to 450 MHz. lator circuit design and initialization code. Table 9. Boot Mode Selection, 176-Lead Package

000 SPI Slave Boot

001 SPI Master Boot

010 AMI User Boot (for 8-bit Flash Boot)

011 No boot (processor executes from internal

Table 10. Boot Mode Selection, 100-Lead Package

00 SPI Slave Boot

01 SPI Master Boot

10 Reserved

11 No boot (processor executes from internal

Rev. H | Page 12 of 71 | February 2020 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Details on power consumption and Static and Dynamic current consumption can be found at Total Power Dissipation on Page 20. Also see Operating Conditions on Page 18 for more information. The following are SVS features.

• SVS is applicable only to 450 MHz models (not applicable to 400 MHz or lower frequency models).
• Each individual SVS device in cludes a register (SVS_DAT) containing the unique SVS voltage set at the factory, known as SVS NOM.
• T h e S V SNOM value is the intended set voltage for the VDD_INT voltage regulator.
• No dedicated pins are required for SVS. The TWI serial bus is used to communicate SVSNOM to the voltage regulator.
• Analog Devices recommends a specific voltage regulator design and initialization code sequence that optimizes the power-up sequence. The Engineer-to-Engineer Note Static Voltage Scaling for ADSP-2148x SHARC Processors (EE-357) contains the details of the regulator design and the initialization requirements.
• Any differences from the Analog Devices recommended programmable regulator design must be reviewed by Ana- log Devices to ensure that it meets the voltage accuracy and range requirements. Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-2148x pro- cessors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing. For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appro- priate emulator hardware user’s guide. DEVELOPMENT TOOLS Analog Devices supports its processors with a complete line of software and hardware development tools, including integrated development environments (which include CrossCore® Embed- ded Studio and/or VisualDSP++®), evaluation products, emulators, and a wide variety of software add-ins. Integrated Development Environments (IDEs) For C/C++ software writing and editing, code generation, and debug support, Analog Devices offers two IDEs. CrossCore Embedded Studio is based on the EclipseTM frame- work. Supporting most Analog Devices processor families, it is the IDE of choice for future processors, including multicore devices. CrossCore Embedded Studio seamlessly integrates available software add-ins to support real time operating systems, file systems, TCP/IP stacks, USB stacks, algorithmic software modules, and evaluation hardware board support packages. For more information visit www.analog.com/cces. The other Analog Devices IDE, VisualDSP++, supports proces- sor families introduced prior to the release of CrossCore Embedded Studio. This IDE includes the Analog Devices VDK real time operating system and an open source TCP/IP stack. For more information visit www.analog.com/visualdsp. Note that VisualDSP++ will not support future Analog Devices processors. EZ-KIT Lite Evaluation Board For processor evaluation, Analog Devices provides wide range of EZ-KIT Lite® evaluation boards. Including the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. Also available are various EZ-Extenders®, which are daughter cards delivering additional specialized functionality, including audio and video processing. For more information visit www.analog.com and search on “ezkit” or “ezextender”. EZ-KIT Lite Evaluation Kits For a cost-effective way to learn more about developing with Analog Devices processors, Analog Devices offer a range of EZ- KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT Lite evaluation board, directions for downloading an evaluation version of the available IDE(s), a USB cable, and a power supply. The USB controller on the EZ-KIT Lite board connects to the USB port of the user’s PC, enabling the chosen IDE evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also supports in-circuit programming of the on-board Flash device to store user-specific boot code, enabling standalone operation. With the full version of Cross- Core Embedded Studio or VisualDSP++ installed (sold separately), engineers can develop software for supported EZ- KITs or any custom system utilizing supported Analog Devices processors. Software Add-Ins for CrossCore Embedded Studio Analog Devices offers software add-ins which seamlessly inte- grate with CrossCore Embedded Studio to extend its capabilities and reduce development time. Add-ins include board support packages for evaluation hardware, various middleware pack- ages, and algorithmic modules. Documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through the CrossCore Embedded Studio IDE once the add-in is installed. Board Support Packages for Evaluation Hardware Software support for the EZ-KIT Lite evaluation boards and EZ- Extender daughter cards is provided by software add-ins called Board Support Packages (BSPs). The BSPs contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. A download link for a specific BSP is located on the web page for the associated EZ-KIT or EZ- Extender product. The link is found in the Product Download area of the product web page.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Rev. H | Page 13 of 71 | February 2020 Middleware Packages Analog Devices separately offers middleware add-ins such as real time operating systems, file systems, USB stacks, and TCP/IP stacks. For more information see the following web pages:

• www.analog.com/ucos3
• www.analog.com/ucfs
• www.analog.com/ucusbd
• www.analog.com/lwip Algorithmic Modules To speed development, Analog Devices offers add-ins that per- form popular audio and video processing algorithms. These are available for use with both CrossCore Embedded Studio and VisualDSP++. For more information visit www.analog.com and search on “Blackfin software modules” or “SHARC software modules”. Designing an Emulator-Compatible DSP Board (Target) For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices sup- plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit emulation is facilitated by use of this JTAG interface. The emu- lator accesses the processor’s internal features via the processor’s TAP, allowing the developer to load code, set break- points, and view variables, memory, and registers. The processor must be halted to send data and commands, but once an operation is completed by the emulator, the DSP system is set to run at full speed with no impact on system timing. The emu- lators require the target board to include a header that supports connection of the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see Analog Devices JTAG Emulation Technical Reference (EE-68). This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-2148x architecture and functionality. For detailed information on the ADSP-2148x family core architecture and instruction set, refer to the programming reference manual. RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The application signal chains page in the Circuits from the Lab® site (http:\\\\www.analog.com\\circuits) provides:
• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection guides and application information
• Reference designs applying be st practice design techniques

Table 11. Pin Descriptions external memory interface mode and FLAG(0 –3) pins are in FLAGS mode (default). interface data (I/O), and FLAGS7–0 (I/O). controllers, or other peripherals to hold off completion of an external memory access. tional memory access instruction is executed, when the condition evaluates as true. FLAG2/Interrupt Request2/Memory Select2. FLAG3/Timer Expired/Memory Select3. O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

SDRAM command pins, defines the operation for the SDRAM to perform. other SDRAM command pins, defines the operation for the SDRAM to perform. other SDRAM command pins, defines the operation for the SDRAM to perform. signal. For details, see the data sheet supplied with the SDRAM device. accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM accesses. for read accesses. Input data is masked when DQM is sampled high during a write cycle. register. For more information, see the hardware reference manual. centric peripheral inputs or outputs connected to the pin and to the pin’s output enable. 14–1 I/O/T (ipu) High-Z Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU. input or output signal present in the DPI SRU may be routed to any of these pins. WDT_CLKIN I Watchdog Timer Clock Input. This pin should be pulled low when not used. WDT_CLKO O Watchdog Resonator Pad Output. WDTRSTO O (ipu) Watchdog Timer Reset Out. THD_P I Thermal Diode Anode. When not used, this pin can be left floating. THD_M O Thermal Diode Cathode. When not used, this pin can be left floating. Table 11. Pin Descriptions (Continued) O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

controller is not used, this pin should be grounded.

1 I/O/T in 3

this pin should be grounded. 1 O/T High-Z Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB mode. this pin should be connected to ground. not used, this pin should be connected to ground. TDI I (ipu) Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDO O/T High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path. TMS I (ipu) Test Mode Select (JTAG). Used to control the test state machine. (pulsed low) after power-up or held low for proper operation of the device. after power-up or held low for proper operation of the processor. product line of JTAG emulators target board connector only. O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

CLK_CFG1–0 I Core to CLKIN Ratio Control. These pins set the start up clock frequency. the processors to use either its internal clock generator or an external clock source. register. For more information, see the hardware reference manual. 1 The MLB pins are only available on the automotive models. Table 12. Pin List, Power, Ground and Other VDD_THD P Thermal Diode Power Supply. When not used, this pin can be left floating. DNC DNC Do Not Connect. Do not make any electrical connection to this pin. O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

Rev. H | Page 18 of 71 | February 2020 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 SPECIFICATIONS OPERATING CONDITIONS

266 MHz / 300 MHz / 350 MHz / 400 MHz 450 MHz

1 Specifications subject to change without notice. Description Min Nominal Max Min Nominal Max VDD_INT2 2 SVSNOM refers to the nominal SVS voltage which is set between 1.0 V and 1.15 V at the factory for each individual device. Only the unique SVSNOM value in each chip may be used for 401 MHz to 450 MHz operation of that chip. This spec lists the possible range of the SVSNOM values for all devices. The initial VDD_INT voltage at power on is 1.1 V nominal and it transitions to SVS programmed voltage as outlined in Engineer-to-Engineer Note Static Voltage Scaling for ADSP-2148x SHARC Processors (EE-357). VDD_EXT External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V VDD_THD Thermal Diode Supply Voltage 3.13 3.47 3.13 3.47 V VIH3 3 Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST, AMI_ACK, MLBCLK, MLBDAT, MLBSIG. High Level Input Voltage at VDD_EXT = Max 2.0 3.6 2.0 3.6 V VIL3 Low Level Input Voltage at VDD_EXT = Min VIH_CLKIN4 4 Applies to input pins CLKIN, WDT_CLKIN. High Level Input Voltage at VDD_EXT = Max 2.2 V DD_EXT 2.2 V DD_EXT V VIL_CLKIN Low Level Input Voltage at VDD_EXT = Min CONSUMER GRADE TJ Junction Temperature 88-Lead LFCSP_VQ 01 1 5 N / A 5 5 N/A means not applicable. N/A5 °C TJ Junction Temperature 100-Lead LQFP_EP 01 1 0 N / A 5 N/A5 °C TJ Junction Temperature 176-Lead LQFP_EP 0 110 0 115 °C INDUSTRIAL GRADE TJ Junction Temperature 100-Lead LQFP_EP –40 +125 N/A 5 N/A5 °C TJ Junction Temperature 176-Lead LQFP_EP –40 +125 N/A 5 N/A5 °C AUTOMOTIVE GRADE6 6 Automotive application use profile only. No t supported for nonautomotive use. Cont act Analog Devices for more information. TJ Junction Temperature 88-Lead LFCSP_VQ –40 +125 N/A 5 N/A5 °C TJ Junction Temperature 100-Lead LQFP_EP –40 +125 N/A 5 N/A5 °C TJ Junction Temperature 176-Lead LQFP_EP –40 +125 N/A 5 N/A5 °C

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Rev. H | Page 19 of 71 | February 2020

ELECTRICAL CHARACTERISTICS

266 MHz / 300 MHz / 350 MHz / 400 MHz / 450 MHz

Parameter1 Description Conditions Min Typ Max Unit VOH2 High Level Output Voltage @ VDD_EXT = Min, IOH = –1.0 mA3 2.4 V VOL2 Low Level Output Voltage @ VDD_EXT = Min, IOL = 1.0 mA3 0.4 V IIH4, 5 High Level Input Current @ V DD_EXT = Max, VIN = VDD_EXT Max 10 μA IIL4 Low Level Input Current @ V DD_EXT = Max, VIN = 0 V 10 μA IILPU5 Low Level Input Current Pull-up @ VDD_EXT = Max, VIN = 0 V 200 μA IOZH6, 7 Three-State Leakage Current @ VDD_EXT = Max, VIN = VDD_EXT Max 10 μA IOZL6 Three-State Leakage Current @ VDD_EXT = Max, VIN = 0 V 10 μA IOZLPU7 Three-State Leakage Current Pull-up @ VDD_EXT = Max, VIN = 0 V 200 μA IOZHPD8 Three-State Leakage Current Pull-down @ VDD_EXT = Max, VIN = VDD_EXT Max 200 μA IDD_INT9 Supply Current (Internal) f CCLK > 0 MHz Table 14 + Table 15 × ASF mA IDD_INT Supply Current (Internal) V DDINT = 1.1 V, ASF = 1, TJ = 25°C 385 / 410 / 450 / 500 / 550 mA CIN10, 11 Input Capacitance T J = 25°C 5 pF 1 Specifications subject to change without notice. 2 Applies to output and bidirectional pins: ADDR23–0, DATA15–0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, RESETOUT MLBSIG, MLBDAT, MLBDO, MLBSO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, MS0-1. 3 See Output Drive Currents on Page 55 for typical drive current capabilities. 4 Applies to input pins: BOOT_CFGx, CLK_CFGx, TCK, RESET , CLKIN. 5 Applies to input pins with internal pull-ups: TRST , TMS, TDI. 6 Applies to three-statable pin: TDO. 7 Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU . 8 Applies to three-statable pin with pull-down: SDCLK. 9 See Engineer-to-Engineer Note Estimating Power for ADSP-214xx SHARC Processors (EE-348) for further information. 10Applies to all signal pins. 11Guaranteed, but not tested.

1. Internal power consumption is additionally comprised of

• Static current due to leakage. Table 14 shows the static current consumption (IDD_INT_STATIC) as a function of junction temperature (TJ) and core voltage (VDD_INT).
• Dynamic current (I DD_INT_DYNAMIC), due to transistor switching characteristics and activity level of the pro- cessor. The activity level is reflected by the Activity Scaling Factor (ASF), which represents the activity level of the application code running on the processor core and having various levels of peripheral and exter- nal port activity (Table 13). Dynamic current consumption is calculated by select- ing the ASF that corresponds most closely with the user application and then multiplying that with the dynamic current consumption (Table 15). 2. External power consumption is due to the switching activ- ity of the external pins.

Table 13. Activity Scaling Factors (ASF)

1 See the Engineer-to-Engineer Note Estimating Power for ADSP-214xx SHARC

vectors specific to the ASF table.

2 Ratio of continuous instruction loop (c ore) to SDRAM control code reads and

Table 14. Static Current—I DD_INT_STATIC (mA)1 1 Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 18.

Table 15. Dynamic Current in CCLK Domain—I DD_INT_DYNAMIC (mA, with ASF = 1.0)1, 2 1 The values are not guaranteed as standalone maximum specifications. They must be combin ed with static current per the equations of Electrical Characteristics on Page 19 . 2 Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 18. Table 16. Absolute Maximum Ratings ESD (electrostatic discharge) sensitive device. may occur on devices subjected to high energy ESD. avoid performance degradation or loss of functionality.

derive parameters from the addition or subtraction of others. Figure 42 on Page 55 for voltage reference levels. operates correctly with other devices. clock frequency with the CLK_CFG1–0 pins.

• The product of CLKIN and PLLM must never exceed 1/2 of fVCO (max) in Table 19 if the input divider is not enabled (INDIV = 0).
• The product of CLKIN and PLLM must never exceed f VCO (max) in Table 19 if the input divider is enabled (INDIV = 1). The VCO frequency is calculated as follows: fVCO = 2 × PLLM × fINPUT fCCLK = (2 × PLLM × fINPUT) ÷ PLLD where: fVCO = VCO output PLLM = Multiplier value programmed in the PMCTL register. During reset, the PLLM value is derived from the ratio selected using the CLK_CFG pins in hardware. PLLD = 2, 4, 8, or 16 based on the divider value programmed on the PMCTL register. During reset this value is 2. fINPUT = is the input frequency to the PLL. fINPUT = CLKIN when the input divider is disabled or fINPUT = CLKIN ÷ 2 when the input divider is enabled

Figure 3. Core Clock and System Clock Relationship to CLKIN

4096 CLKIN

*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS fINPUT. THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.

for each peripheral’s timing information. more information, see the hardware reference manual. Table 18. While no specific power-up sequencing is required that system designs should take into account.

• No power supply should be po wered up for an extended period of time (> 200 ms) before another supply starts to ramp up.
• I f t h e VDD_INT power supply comes up after VDD_EXT, any pin, such as RESETOUT and RESET, may actually drive momentarily until the VDD_INT rail has powered up. Systems sharing these signals on the board must determine if there are any issues that need to be addressed based on this behavior. Note that during power-up, when the V DD_INT power supply comes up after VDD_EXT, a leakage current of the order of three- state leakage current pull-up, pull-down may be observed on any pin, even if that is an input only (for example the RESET pin) until the VDD_INT rail has powered up.

Table 17. Clock Periods Table 18. Power Up Sequencing Timing Requirements (Processor Startup) from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem. a 25 ms maximum oscillator startup time if using the XTAL pin an d internal oscillator circuit in conjunction with an external c rystal. propagate default states at all I/O pins.

Figure 4. Power-Up Sequencing Table 19. Clock Input

266 MHz 300 MHz 350 MHz 400 MHz 450 MHz

1 Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL. 2 Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL. 3 Guaranteed by simulation but not tested on silicon. 4 Any changes to PLL control bits in the PMCTL regis ter must meet core clock timing specification tCCLK. 5 See Figure 3 on Page 22 for VCO diagram. 6 Actual input jitter should be combined with ac specifications for accurate timing analysis. 7 Jitter specification is maximum peak-to -peak time interval error (TIE) jitter. Figure 5. Clock Input

Table 28. Precision Clock Generator (Direct Pin Routing) D = FSxDIV, PH = FSxPHASE. For more information, see the “Precision Clock Generators” chapter in the hardware reference manual. Figure 15. Precision Clock Generator (Direct Pin Routing)

more information on flag use. Table 29. Flags 1 This is applicable when the Flags are connected to DPI_P14–1, ADDR7–0, ADDR23–8, DATA7–0 and FLAG3–0 pins. Figure 16. Flags

Table 30. SDRAM Interface Timing more information on hardware design guidelines for the SDRAM interface. 2 Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE. Figure 17. SDRAM Interface Timing

Table 31. AMI Read W = (number of wait states specified in AMICTLx register) × t SDCLK. 1 Data delay/setup: System must meet tDAD, tDRLD, or tSDS. 2 The falling edge of MSx, is referenced. 4 Note that timing for AMI_ACK, ADDR, DATA, AMI_RD , AMI_WR, and strobe timing parameters only apply to asynchronous access mode. 5 Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions on Page 55 for the calculation of hold times given capacitive and dc loads. 6 AMI_ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low).

Figure 18. AMI Read

Table 32. AMI Write 1 AMI_ACK delay/setup: System must meet t DAAK, or tDSAK, for deassertion of AMI_ACK (low). 2 The falling edge of MSx is referenced. 3 Note that timing for AMI_ACK, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode. 4 See Test Conditions on Page 55 for calculation of hold times given capacitive and dc loads. 5 For Write to Write: tSDCLK + H, for both same bank and different bank. For Write to Read: 3 × tSDCLK + H, for the same bank and different banks. Figure 19. AMI Write

Channel B) are routed to the DAI_P20–1 pins using the SRU. Table 33. Serial Ports—External Clock 1 Referenced to sample edge. Table 34. Serial Ports—Internal Clock 1 Referenced to the sample edge.

Figure 20. Serial Ports

Table 35. Serial Ports—External Late Frame Sync 1 The tDDTLFSE and tDDTENFS parameters apply to left-justified, as well as DSP serial mode, and MCE = 1, MFD = 0. Figure 21. External Late Frame Sync 1 1 This figure reflects changes made to support left-justified mode.

Table 36. Serial Ports—Enable and Three-State Figure 22. Serial Ports—Enable and Three-State

_TDV_O is asserted for communication with external devices. Table 37. Serial Ports—TD V (Transmit Data Valid) Figure 23. Serial Ports—TDM Internal and External Clock

Table 38. Input Data Port (IDP) be either CLKIN or any of the DAI pins. Figure 24. IDP Master Timing

Table 39. PDAP is the parallel mode operation of Channel 0 of ADDR23–4 pins or over the DAI pins. Table 39. Parallel Data Acquisition Port (PDAP) Figure 25. PDAP Timing

Table 40 are valid at the DAI_P20–1 pins. Table 40. ASRC, Serial Input Port can be either CLKIN or any of the DAI pins. Figure 26. ASRC Serial Input Port Timing

Table 41. ASRC, Serial Output Port can be either CLKIN or any of the DAI pins. Figure 27. ASRC Serial Output Port Timing

below are valid at the DAI_P20–1 pins. The S/PDIF transmitter requires an oversampling clock input. generate the internal biphase clock. Table 46. S/PDIF Transmitter Input Data Timing be either CLKIN or any of the DAI pins. Figure 32. S/PDIF Transmitter Input Timing Table 47. Oversampling Clock (TxC LK) Switching Characteristics

(digital PLL) generates the 512 × FS clock. Table 48. S/PDIF Receiver Inte rnal Digital PLL Mode Timing 1 SCLK frequency is 64 × FS where FS = the frequency of frame sync. Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing

Table 49 and Table 50 applies to both. Table 49. SPI Interface Protocol—Master Switching and Timing Specifications Figure 34. SPI Master Timing

Table 50. SPI Interface Protocol—Slave Switching and Timing Specifications the hardware reference manual. Figure 35. SPI Slave Timing

cation document revision 3.0 for more details. Table 51. MLB Interface, 3-Pin Specifications

512 FS/256 FS

512 FS/256

1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, mea sured in ns peak-to-peak (pp). minimized while meeting the maximum capacitive load listed.

Figure 36. MLB Timing (3-Pin Interface) Table 52. MLB Interface, 5-Pin Specifications 1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, mea sured in ns peak-to-peak (pp). 2 Gate Delays due to OR'ing logic on the pins must be accounted for. external pull-down resistors are required to keep the outputs fr om corrupting the MediaLB signal lines when not being driven.

Table 53. JTAG Test Access Port and Emulation 1 System Inputs = DATA15–0, CLK_CFG1–0, RESET , BOOT_CFG2–0, DAI_Px, DPI_Px, and FLAG3–0. 2 System Outputs = DAI_Px, DPI_Px ADDR23–0, AMI_RD , AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK and EMU. Figure 39. IEEE 1149.1 JTAG Test Access Port

Table 55, Table 56, and Table 57 are modeled values. LM86 or others) to read the die temperature of the chip. Table 55. Thermal Characteristics for 88-Lead LFCSP_VQ Table 56. Thermal Characteristics for 100-Lead LQFP_EP Table 57. Thermal Characteristics for 176-Lead LQFP_EP Table 58. Thermal Diode Parameters – Transistor Model 1 1 See Engineer-to-Engineer Note Using the On-Chip Thermal Diode on Analog Devices Processors (EE-346) . 2 Analog Devices does not recommend operation of the thermal diode under reverse bias. 3 Specified by design characterization. q = electronic charge, VBE = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5 The series resistance (RT) can be used for more accurate readings as needed.

Table 59 lists the 88-Lead LFCSP_VQ package lead names. Table 59. 88-Lead LFCSP_VQ Lead Assignments (Numerical by Lead Number) Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.

Table 60. 100-Lead LQFP_EP Lead Assign ments (Numerical by Lead Number) Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.

• Do not make any electrical connection to this pin.

** Pin no. 101 (exposed pad) is the GND supply (see Figure 49 and Figure 50) for the processor; this pad must be robustly connected to GND.

Table 61. ADSP-21486 176-Lead LQFP_EP Lead As signment (Numerical by Lead Number) Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.

131 DNC 175*

• Do not make any electrical connection to this pin.

** Lead no. 177 (exposed pad) is the GND supply (see Figure 51 and Figure 52) for the processor; this pad must be robustly connected to GND.

Table 62. ADSP-21483, ADSP-21487, ADSP-21488, and AD SP-21489 176-Lead LQFP_EP Lead Assignment Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.

131 SDCAS 175

• Do not make any electrical connection to this pin.

** Lead no. 177 (exposed pad) is the GND supply (see Figure 51 and Figure 52) for the processor; this pad must be robustly connected to GND.

Table 63. Automotive Models ADSP-21488, and ADSP-21489 176-Lead LQFP_EP Lead Assignment (Numerical by Lead Number) Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.

• Do not make any electrical connection to this pin.

** Lead no. 177 (exposed pad) is the GND supply (see Figure 51 and Figure 52) for the processor; this pad must be robustly connected to GND.

LQFP_EP RoHS compliant packages. Figure 53. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ 1] 1 For information relating to the exposed pad on the CP-88-5 package, see the table endnote on Page 58. EXCEPT FOR MINIMUM THICKNESS AND LEAD COUNT.

0.60 MAX

Figure 54. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] 1 1 For information relating to the exposed pad on the SW-100-2 package, see the table endnote on Page 60. Figure 55. 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] 1 1 For information relating to the exposed pad on the SW-176-2 package, see the table endnote on Page 62.

6.00 BSC

12.00 REF

1.00 REF

1.60 MAX

21.50 REF

Rev. H | Page 68 of 71 | February 2020 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 SURFACE-MOUNT DESIGN The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. No separate GND pins are provided in the package.

cific Automotive Reliability reports for these models. Table 64. Automotive Products 2 W = automotive applications. 3 xx denotes the current die revision. 5 Referenced temperature is junction temperature. See Operating Conditions on Page 18 for junction temperature (TJ) specification. 6 This product contains IP from Dolby, DTS and DTLA. Proper software licenses required . Contact Analog Devices, Inc. for informat ion.

Rev. H | Page 70 of 71 | February 2020 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 ORDERING GUIDE Model1, 2 Notes Temperature Range 3 RAM Processor Instruction Rate (Max) Package Description Package Option ADSP-21483KSWZ-2B 4 0°C to +110°C 3 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21483KSWZ-3B 4 0°C to +110°C 3 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21483KSWZ-3AB 4 0°C to +110°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21483KSWZ-4B 4 0°C to +110°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21483KSWZ-4AB 4 0°C to +110°C 3 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21486KSWZ-2A 4 0°C to +110°C 5 Mbit 300 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21486KSWZ-2B 4 0°C to +110°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21486KSWZ-2AB 4 0°C to +110°C 5 Mbit 300 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21486KSWZ-2BB 4 0°C to +110°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21486KSWZ-3A 4 0°C to +110°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21486KSWZ-3B 4 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21486KSWZ-3AB 4 0°C to +110°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2 ADSP21486KSWZ3ABRL 4 0°C to +110°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21486KSWZ-3BB 4 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21486KSWZ-4A 4 0°C to +110°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21486KSWZ-4AB 4 0°C to +110°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21487KCPZ-4 4 0°C to +115°C 5 Mbit 400 MHz 88-Lead LFCSP_VQ CP-88-5 ADSP-21487KSWZ-2B 4 0°C to +110°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21487KSWZ-2BB 4 0°C to +110°C 5 Mbit 300 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21487KSWZ-3B 4 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21487KSWZ-3BB 4 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21487KSWZ-4B 4 0°C to +110°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21487KSWZ-4BB 4 0°C to +110°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21487KSWZ-5B 4, 5 0°C to +115°C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21487KSWZ-5BB 4, 5 0°C to +115°C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2 ADSP21487KSWZ5BBRL 4, 5 0°C to +115C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21488BSWZ-3A –40°C to +125°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21488KSWZ-3A 0°C to +110°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21488KSWZ-3A1 6 0°C to +110°C 3 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21488KSWZ-3B 0°C to +110C 3 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21488BSWZ-3B –40°C to +125°C 3 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21488KSWZ-4A 0°C to +110°C 3 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21488BSWZ-4A –40°C to +125°C 3 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21488KSWZ-4B 0°C to +110°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21488BSWZ-4B –40°C to +125°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21488KSWZ-4B1 6 0°C to +110°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2

Rev. H | Page 71 of 71 | February 2020 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 ©2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09018-2/20(H) I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ADSP-21489KCPZ-4 0°C to +115°C 5 Mbit 400 MHz 88-Lead LFCSP_VQ CP-88-5 ADSP-21489KSWZ-3A 0°C to +110°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21489BSWZ-3A –40°C to +125°C 5 Mbit 350 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21489KSWZ-3B 0°C to +110°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21489BSWZ-3B –40°C to +125°C 5 Mbit 350 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21489KSWZ-4A 0°C to +110°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21489BSWZ-4A –40°C to +125°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21489KSWZ-4B 0°C to +110°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21489BSWZ-4B –40°C to +125°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2 ADSP-21489KSWZ-5B 5 0°C to +115°C 5 Mbit 450 MHz 176-Lead LQFP_EP SW-176-2 1 Z = RoHS compliant part. 2 RL = Tape and Reel. 3 Referenced temperature is junction temperature. See Operating Conditions on Page 18 for junction temperature (TJ) specification. 4 The ADSP-21483, ADSP-21486, and ADSP-21487 models are available with factory programmed ROM including the latest multichannel audio decoding and post-processing 5 See Engineer-to-Engineer Note Static Voltage Scaling for ADSP-2148x SHARC Processors (EE-357) for operating ADSP-2148x processors at 450 MHz. 6 This product contains a –140 dB sample rate converter. Model1, 2 Notes Temperature Range 3 RAM Processor Instruction Rate (Max) Package Description Package Option