AD21478WYCPZ1XX

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SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Information furnished by Analog Devices is believed to be accurate and reliable. infringements of patents or other rights of third parties that may result from its use. registered trademarks are the property of their respective companies. Fax: 781.326.3113 ©2012 Analog Devices, Inc. All rights reserved. Figure 1. Functional Block Diagram

5 Stage

Rev. B | Page 2 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 TABLE OF CONTENTS

REVISION HISTORY

3/12—Rev. A to Rev. B Revised Real Time Clock, SR_LDO and EMU Pin Descriptions Corrected tPLLRST, tCLKRST timing in Table 19, Power-Up Sequencing Timing Requirements (Processor Startup) .... 26 Revised note in Figure 8, 266 MHz Operation (Fundamental Added additional models to: Added the 88-lead LFCSP_VQ package and the ADSP-21477 model. General information, specifications, and ordering infor- mation for this package and model can be found in the following sections: 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] PRODUCT APPLICATION RESTRICTION Not for use in in-vivo applications for body fluid constituent monitoring, including monitoring one or more of the compo- nents that form, or may be a part of, or contaminate human blood or other body fluids, such as, but not limited to, car- boxyhemoglobin, methemoglobin total hemoglobin, oxygen saturation, oxygen content, fractional arterial oxygen satura- tion, bilirubin, glucose, drugs, lipids, water, protein, and pH.

digital applications interface (DAI). core clock domain contains the following features.

• Two processing elements (P Ex, PEy), each of which com- prises an ALU, multiplier, shifter, and data register file
• Two data address generators (DAG1, DAG2)
• A program sequencer wi th instruction cache
• PM and DM buses capable of supporting 2 × 64-bit data transfers between memory and the core at every core pro- cessor cycle
• One periodic interval timer with pinout
• On-chip SRAM (up to 5M bit)
• A JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user break- points, which allows flexible exception handling.

Table 1. Processor Benchmarks

1024 Point Complex FFT

1 Assumes two files in multichannel SIMD mode. Table 2. ADSP-2147x Family Features

4 Yes

1 The 100-lead and 88-lead packages of the processors do not contain an external

port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function Descriptions on Page 16. 2 Available on the 196-ball CSP_BGA package only.

3 Real Time Clock (RTC) is supported only for products with a temperature range

of 0°C to +70°C and not supported for all other temperature grades. 4 Available on the 88-lead and 100-lead packages only. Table 2. ADSP-2147x Family Features (Continued)

Rev. B | Page 4 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 The block diagram of the ADSP-2147x on Page 1 also shows the peripheral clock domain (also known as the I/O processor), which contains the following features:

• I O D 0 ( p e r i p h e r a l D M A ) a n d IOD1 (external port DMA) buses for 32-bit data transfers
• Peripheral and external port buses for core connection
• External port with an asynchronous memory interface (AMI) and SDRAM controller
• 4 u n i t s f o r p u l s e w i d t h modulation (PWM) control
• 1 memory-to-memory (MTM) unit for internal-to-internal memory transfers
• Digital applications interface that includes four precision clock generators (PCG), an input data port (IDP/PDAP) for serial and parallel interconnect, an S/PDIF receiver/transmitter, four asynchronous sample rate con- verters, eight serial ports, a shift register, and a flexible signal routing unit (DAI SRU).
• Digital peripheral interface that includes two timers, a 2- wire interface, one UART, two serial peripheral interfaces (SPI), two precision clock generators (PCG), three pulse width modulation (PWM) units, and a flexible signal rout- ing unit (DPI SRU). As shown in the SHARC core block diagram on Page 5, the pro- cessors use two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. With its SIMD computational hard- ware, the processors can perform 1.8 GFLOPS running at 300 MHz. FAMILY CORE ARCHITECTURE The processors are code compatible at the assembly level with the ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2147x share archi- tectural features with the ADSP-2126x, ADSP-2136x, ADSP- 2137x, ADSP-2146x, and ADSP-2116x SIMD SHARC proces- sors, as shown in Figure 2 and detailed in the following sections. SIMD Computational Engine The processors contain two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. SIMD mode allows the processor to execute the same instruction in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms. SIMD mode also affects the way data is transferred between memory and the processing elements because twice the data bandwidth is required to sustain computational operation in the processing elements. Therefore, entering SIMD mode also dou- bles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each memory or reg- ister file access. SIMD mode is supported from external SDRAM but is not sup- ported in the AMI. Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all opera- tions in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing ele- ments. These computation units support IEEE 32-bit single- precision floating-point, 40-bit extended precision floating- point, and 32-bit fixed-point data formats. Timer The processor contains a core timer that can generate periodic software interrupts. The core timer can be configured to use FLAG3 as a timer expired signal. Data Register File Each processing element contains a general-purpose data regis- ter file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the processor’s enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. Context Switch Many of the processor’s registers have secondary registers that can be activated during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result registers all have secondary registers. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. Universal Registers Universal registers can be used for general-purpose tasks. The USTAT (4) registers allow easy bit manipulations (Set, Clear, Toggle, Test, XOR) for all peripheral control and status registers. The data bus exchange register (PX) permits data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM/DM data bus. These registers contain hardware to handle the data width difference. Single-Cycle Fetch of Instruction and Four Operands The processors feature an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the pro- gram memory (PM) bus transfers both instructions and data (see Figure 2). With its separate program and data memory

instruction (from the cache), all in a single cycle. start and end at any memory location. Figure 2. SHARC Co re Block Diagram

to create these more efficient opcodes. pendent accesses by the core processor and I/O processor. that retrieves 32-bit memory. Table 3. ADSP-21477 Internal Memory Space, 2M bits

Table 4. ADSP-21478 Internal Memory Space (3M bits) 1 representative for additional details.

the IOD0/1 buses (2 × 32-bit at PCLK speed). scrambling system) is protected by this copy protection system. Table 5. ADSP-21479 Internal Memory Space (5M bits) 1 representative for additional details.

external ports are comprised of the following modules.

• An AMI which communicates with SRAM, FLASH, and other devices that meet the standard asynchronous SRAM access protocol. The AMI supports 6M words of external memory in Bank 0 and 8M words of external memory in Bank 1, Bank 2, and Bank 3.
• An SDRAM controller that supports a glueless interface with any of the standard SDRAMs. The SDC supports 62M words of external memory in Bank 0, and 64M words of external memory in Bank 1, Bank 2, and Bank 3.
• Arbitration logic to coordinate core and DMA transfers between internal and external memory over the external port. External Port The external port provides a high performance, glueless inter- face to a wide variety of industry-standard memory devices. The external port, available on the 196-ball CSP_BGA, may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory control- lers. The first is an SDRAM controller for connection of industry-standard synchronous DRAM devices while the sec- ond is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types. Non-SDRAM external memory address space is shown in Table 6. SIMD Access to External Memory The SDRAM controller supports SIMD access on the 64-bit external port data bus (EPD) which allows access to the comple- mentary registers on the PEy unit in the normal word space (NW). This improves performance since there is no need to explicitly load the complementary registers (as in SISD mode). VISA and ISA Access to External Memory The SDRAM controller supports VISA code operation which reduces the memory load since the VISA instructions are com- pressed. Moreover, bus fetching is reduced because, in the best case, one 48-bit fetch contains three valid instructions. Code execution from the traditional ISA operation is also supported. Note that code execution is only supported from Bank 0 regard- less of VISA/ISA. Table 7 shows the address ranges for instruction fetch in each mode. SDRAM Controller The SDRAM controller, available on the ADSP-2147x in the 196-ball CSP_BGA package, provides an interface of up to four separate banks of industry-standard SDRAM devices or DIMMs, at speeds up to fSDCLK. Fully compliant with the SDRAM standard, each bank has its own memory select line (MS0–MS3), and can be configured to contain between 4 Mbytes and 256 Mbytes of memory. SDRAM external mem- ory address space is shown in Table 8. A set of programmable timing parameters is available to config- ure the SDRAM banks to support slower memory devices. The SDRAM and the AMI interface do not support 32-bit wide devices. The SDRAM controller address, data, clock, and control pins can drive loads up to distributed 30 pF. For larger memory sys- tems, the SDRAM controller external buffer timing should be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF. Note that the external memory bank addresses shown are for normal-word (32-bit) accesses. If 48-bit instructions as well as 32-bit data are both placed in the same external memory bank, care must be taken while mapping them to avoid overlap. Asynchronous Memory Controller The asynchronous memory controller, available on the ADSP-2147x in the 196-ball CSP_BGA package, provides a con- figurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide vari- ety of memory devices including SRAM, flash, and EPROM, as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 6M word window and Banks 1, 2, and 3

Table 6. External Memory for Non-SDRAM Addresses Table 7. External Bank 0 Instruction Fetch Table 8. External Memory for SDRAM Addresses

Rev. B | Page 10 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 occupy a 8M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. External Port Throughput The throughput for the external port, based on 133 MHz clock and 16-bit data bus, is 88 Mbytes/sec for the AMI and 266 Mbytes/sec for SDRAM. MediaLB The automotive models of the processors have an MLB interface which allows the processor to function as a media local bus device. It includes support for both 3-pin and 5-pin MLB proto- cols. It supports speeds up to 1024 FS (49.25M bits/sec, FS = 48.1 kHz) and up to 31 logical channels, with up to 124 bytes of data per media local bus frame. For a list of auto- motive products, see Automotive Products on Page 74. Digital Applications Interface (DAI) The digital applications interface (DAI) provides the ability to connect various peripherals to any of the DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU), shown in Figure 1. The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be intercon- nected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with non con- figurable signal paths. The associated peripherals include eight serial ports, four preci- sion clock generators (PCG), a S/PDIF transceiver, four ASRCs, and an input data port (IDP). The IDP provides an additional input path to the SHARC core, configurable as either eight channels of serial data, or a single 20-bit wide synchronous par- allel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’s serial ports. Serial Ports (SPORT s) The processors feature eight synchronous serial ports that pro- vide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports can support up to 16 transmit or 16 receive DMA channels of audio data when all eight SPORTs are enabled, or four full duplex TDM streams of 128 channels per frame. Serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated DMA chan- nels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT pro- vides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in five modes:

• Standard serial mode
• M u l t i c h a n n e l ( T D M ) m o d e 2S mode
• P a c k e d I2S mode
• Left-justified mode S/PDIF-Compatible Digital Audio Receiver/Transmitter The S/PDIF receiver/transmitter has no separate DMA chan- nels. It receives audio data in serial format and converts it into a bi phase encoded signal. The serial data input to the receiver/transmitter can be formatted as left justified, I 2S or right-justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources, such as the SPORTs, external pins, the precision clock generators (PCGs), and are controlled by the SRU control registers. Asynchronous Sample Rate Converter (SRC) The sample rate converter contains four blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter. The SRC block provides up to 128 dB SNR and is used to perform synchronous or asynchronous sam- ple rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Input Data Port The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive audio channels in I 2S, left-justified sample pair, or right-justified mode. The IDP also provides a parallel data acquisition port (PDAP) which can be used for receiving parallel data. The PDAP port has a clock input and a hold input. The data for the PDAP can be received from DAI pins or from the external port pins. The PDAP supports a maximum of 20-bit data and four different packing modes to receive the incoming data. Precision Clock Generators The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A B, C, and D are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair. The outputs of PCG A and B can be routed through the DAI pins and the outputs of PCG C and D can be driven on to the DAI as well as the DPI pins.

ADSP-21477/ADSP-21478/ADSP-21479 Rev. B | Page 11 of 76 | March 2012 Digital Peripheral Interface (DPI) The digital peripheral interface provides connections to two serial peripheral interface ports (SPI), one universal asynchro- nous receiver-transmitter (UART), 12 flags, a 2-wire interface (TWI), three PWM modules (PWM3–1), and two general- purpose timers. Serial Peripheral (Compatible) Interface (SPI) The SPI is an industry-standard synchronous serial link, enabling the SPI-compatible port to communicate with other SPI compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchro- nous serial interface, supporting both master and slave modes. The SPI port can operate in a multi-master environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The SPI-compatible periph- eral implementation also features programmable baud rate and clock phase and polarities. The SPI-compatible port uses open drain drivers to support a multi-master configuration and to avoid data contention. UART Port The processors provide a full-duplex Universal Asynchronous Receiver/Transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simpli- fied UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART also has multiprocessor communication capa- bility using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface standard. The UART port also includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller trans- fers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The UART port's baud rate, serial data format, error code gen- eration and status, and interrupts are programmable:
• Support for bit rates ranging from (f PCLK/1,048,576) to (fPCLK/16) bits per second.
• Support for data formats fr om 7 to 12 bits per frame.
• Both transmit and receive oper ations can be configured to generate maskable interrupts to the processor. In conjunction with the general-purpose timer functions, auto- baud detection is supported. Pulse-Width Modulation The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM wave- forms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four PWM waveforms). The entire PWM module has four groups of four PWM outputs generating 16 PWM outputs in total. Each PWM group pro- duces two pairs of PWM signals on the four PWM outputs. The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic dis- tortion in three-phase PWM inverters. PWM signals can be mapped to the external port address lines or to the DPI pins. Timers The processors have a total of three timers: a core timer that can generate periodic software interrupts and two general-purpose timers that can generate periodic interrupts and be indepen- dently set to operate in one of three modes:
• P u l s e w a v e f o r m generation mode
• P u l s e w i d t h c ount/capture mode
• External event watch dog mode The core timer can be configured to use FLAG3 as a timer expired signal, and the general-purpose timers have one bidirec- tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A sin- gle control and status register enables or disables the general- purpose timer. 2-Wire Interface Port (TWI) The TWI is a bidirectional 2-wire serial bus used to move 8-bit data while maintaining compliance with the I 2C bus protocol. The TWI master incorporates the following features:
• 7-bit addressing
• Simultaneous master and slave operation on multiple device systems with support for multi-master data arbitration
• Digital filtering and timed event processing
• 100 kbps and 400 kbps data rates
• Low interrupt rate

transition of the shift register latch clock (SR_LAT) input. The shift register’s signals can be configured as follows.

• The SR_SCLK can come from any of the SPORT0–7 SCLK outputs, PCGA/B clock, any of the DAI pins (1–8), and one dedicated pin (SR_SCLK).
• The SR_LAT can come from any of SPORT0–7 frame sync outputs, PCGA/B frame sync, any of the DAI pins (1–8), and one dedicated pin (SR_LAT).
• The SR_SDI input can from any of SPORT0–7 serial data outputs, any of the DAI pins (1–8), and one dedicated pin (SR_SDI). Note that the SR_SCLK, SR_LAT, and SR_SDI inputs must come from same source except in the case of where SR_SCLK comes from PCGA/B or SR_SCLK and SR_LAT come from PCGA/B. If SR_SCLK comes from PCGA/B, then SPORT0–7 generates the SR_LAT and SR_SDI signals. If SR_SCLK and SR_LAT come from PCGA/B, then SPORT0–7 generates the SR_SDI signal. I/O PROCESSOR FEATURES The I/O processor provides up to 65 channels of DMA as well as an extensive set of peripherals. DMA Controller The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral inter- face) ports, the IDP (input data port), the parallel data acquisition port (PDAP) or the UART. Up to 65 channels of DMA are available on the processors as shown in Table 9. Programs can be downloaded using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers. Delay Line DMA The processor provides delay line DMA functionality. This allows processor reads and writes to external delay line buffers (and therefore to external memory) with limited core interaction. Scatter/Gather DMA The processor provides scatter/gather DMA functionality. This allows processor DMA reads/writes to/from noncontiguous memory blocks. FFT Accelerator The FFT accelerator implements radix-2 complex/real input, complex output FFTs with no core intervention. The FFT accel- erator runs at the peripheral clock frequency. FIR Accelerator The FIR (finite impulse response) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four MAC units. A controller manages the accelerator. The FIR accelerator runs at the peripheral clock frequency. IIR Accelerator The IIR (infinite impulse response) accelerator consists of a 1440 word coefficient memory for storage of biquad coeffi- cients, a data memory for storing the intermediate data and one MAC unit. A controller manages the accelerator. The IIR accel- erator runs at the peripheral clock frequency. Watchdog Timer (WDT) The processors include a 32-bit watchdog timer that can be used to implement a software watchdog function. A software watch- dog can improve system reliability by forcing the processor to a known state through generation of a system reset if the timer expires before being reloaded by software. Software initializes the count value of the timer, and then enables the timer. The WDT is used to supervise the stability of the system soft- ware. When used in this way, software reloads the WDT in a regular manner so that the downward counting timer never expires. An expiring timer then indicates that system software might be out of control. The WDT resets both the core and the internal peripherals. Software must be able to determine if the watch dog was the source of the hardware reset by interrogating a status bit in the watch dog timer control register.

Table 9. DMA Channels Table 9. DMA Channels (Continued)

components as shown in Figure 3. options and power supply issues. EPROM via the external port, an SPI master, or an SPI slave. (BOOT_CFG2–0) pins in Table 10. ADSP-214xx SHARC Processor Hardware Reference. tions. The external supply must meet the VDD_EXT specification. power and ground planes for VDD_INT and GND. itor and control the target board processor during emulation. affect target system loading or timing. priate emulator hardware user’s guide. development. Multiple daughter cards are available. Figure 3. External Components for RTC NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF. Table 10. Boot Mode Selection

000 SPI Slave Boot

001 SPI Master Boot (from Flash and Other Slaves)

010 AMI User Boot (for 8-bit Flash Boot)

011 No Boot (Processor Executes from Internal

100 Reserved

1 The BOOT_CFG2 pin is not available on the 100-lead or 88-lead packages.

Rev. B | Page 14 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 Designing an Emulator-Compatible DSP Board (Target) The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. Nonintrusive in- circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal fea- tures of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. Evaluation Kit Analog Devices offers a range of EZ-KIT Lite evaluation plat- forms to use as a cost effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product. The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board proces- sor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board Flash device to store user-specific boot code, enabling the board to run as a stand- alone unit without being connected to the PC. With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any cus- tom defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, non- intrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-2147x architecture and functionality. For detailed information on the family core architecture and instruction set, refer to the SHARC Processor Programming Reference. RELATED SIGNAL CHAINS A signal chain is a series of signal conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in the Glossary of EE Terms on the Analog Devices website. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The Circuits from the Lab TM site (www.analog.com/signal chains) provides:

• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection guides and application information
• Reference designs applying be st practice design techniques

Table 11. Pin Descriptions ADDR pins are in EMIF mode, and FLAG(0–3) pins are in FLAGS mode (default). pins for parallel input data. interface data (I/O) and FLAGS7–0 (I/O). processor booting, see the ADSP-214xx SHARC Processor Hardware Reference. FLAG0/IRQ0 I/O (ipu) FLAG[0] INPUT FLAG0/Interrupt Request0. FLAG1/IRQ1 I/O (ipu) FLAG[1] INPUT FLAG1/Interrupt Request1. in the 196-ball BGA package only. O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

other SDRAM command pins, defines the operation for the SDRAM to perform. SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin. signal. For details, see the data sheet supplied with the SDRAM device. whether any SDRAM accesses occur or not. SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers. Processor Hardware Reference. may be routed to any of these pins. peripheral inputs or outputs connected to the pin and to the pin's output enable. routed to any of these pins. WDT_CLKIN I Watch Dog Timer Clock Input. This pin should be pulled low when not used. WDT_CLKO O Watch Dog Resonator Pad Output. O (ipu) Watch Dog Timer Reset Out. Table 11. Pin Descriptions (Continued) O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

THD_P I Thermal Diode Anode. When not used, this pin can be left floating. THD_M O Thermal Diode Cathode. When not used, this pin can be left floating. MLBDAT line carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB controller is not used, this pin should be grounded. MLB controller is not used, this pin should be grounded. used, this pin should be grounded. SR_SDI I (ipu) Shift Register Serial Data Input. SR_SDO O (ipu) Driven Low Shift Register Serial Data Output. SR_LDO17–0 O/T (ipu) High-Z Shift Register Parallel Data Output. and the RTC_PDN and RTC_BUSDIS bits of RTC_INIT register must be set to 1. RTXO O RTC Crystal Output. If RTC is not used, then this pin needs to be NC (No Connect). used, then this pin needs to be NC (No Connect). O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

TDI I (ipu) Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDO O/T High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path. TMS I (ipu) Test Mode Select (JTAG). Used to control the test state machine. (pulsed low) after power-up or held low for proper operation of the device. low) after power-up or held low for proper operation of the processor. line of JTAG emulators target board connector only. CLK_CFG1–0 I Core to CLKIN Ratio Control. These pins set the startup clock frequency. operated below the specified frequency. be asserted (low) at power-up. BOOT_CFG2–0 I Boot Configuration Select. These pins select the boot mode for the processor. The BOOT_CFG2 pin is only available on the 196-lead package. O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

Table 12. Pin List, Power and Ground VDD_INT P Internal Power Supply. VDD_RTC P Real-Time Clock Power Supply. VDD_THD P Thermal Diode Power Supply. When not used, this pin can be left floating. Assignment on Page 67 and 100-LQFP_EP Lead Assignment on Page 69 .

Rev. B | Page 20 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 SPECIFICATIONS OPERATING CONDITIONS

200 MHz 266 MHz 300 MHz

1 Specifications subject to change without notice. Description Min Nom Max Min Nom Max Min Nom Max Unit VIH 2 Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST, SDA10, AMI_ACK, MLBCLK, MLBDAT, MLBSIG. High Level Input Voltage @ VDD_EXT = Max 2.0 2.0 2.0 V VIL 3 Applies to input pin CLKIN, WDT_CLKIN. Low Level Input Voltage @ VDD_EXT = Min 0.8 0.8 0.8 V VIH_CLKIN 3 High Level Input Voltage @ VDD_EXT = Max 2.2 V DD_EXT 2.2 V DD_EXT 2.2 V DD_EXT V TJ Junction Temperature 88-Lead LFCSP_VQ @ TAMBIENT 0°C to +70°C 0 105 N/A N/A N/A N/A °C TJ Junction Temperature 88-Lead LFCSP_VQ @ TAMBIENT –40°C to +85°C –40 +115 N/A N/A N/A N/A °C TJ 4 Applies to automotive models only. See Automotive Products on Page 74. Junction Temperature 88-Lead LFCSP_VQ @ TAMBIENT –40°C to +105°C –40 +125 N/A N/A N/A N/A °C TJ Junction Temperature 100-Lead LQFP_EP @ TAMBIENT 0°C to +70°C 0 105 0 105 N/A N/A °C TJ

4 Junction Temperature 100-Lead LQFP_EP @

TAMBIENT –40°C to +85°C N/A N/A –40 +125 N/A N/A °C TJ TAMBIENT –40°C to +105°C –40 +125 –40 +125 N/A N/A °C TJ 5 Real Time Clock (RTC) is supported only for products with a tem perature range of 0°C to +70°C and not supported for all other temperature grades. For the status of unused RTC pins please see Table 11 on Page 15. Junction Temperature 196-Ball CSP_BGA @ TAMBIENT 0°C to +70°C N/A N/A 0 105 0 100 °C TJ

5 Junction Temperature 196-Ball CSP_BGA @

TAMBIENT –40°C to +85°C N/A N/A –40 +125 N/A N/A °C

ADSP-21477/ADSP-21478/ADSP-21479 Rev. B | Page 21 of 76 | March 2012

ELECTRICAL CHARACTERISTICS

UnitParameter1 Description Test Conditions Min Max Min Max Min Max VOH

2 High Level Output Voltage @ V DD_EXT = Min,

IOH = –1.0 mA3 2.4 2.4 2.4 V VOL

2 Low Level Output Voltage @ V DD_EXT = Min,

IOL = 1.0 mA3 0.4 0.4 0.4 V IIH 4, 5 High Level Input Current @ V DD_EXT = Max, VIN = VDD_EXT Max 10 10 10 μA IIL

4 Low Level Input Current @ V DD_EXT = Max, VIN = 0 V –10 –10 –10 μA

5 Low Level Input Current

@ VDD_EXT = Max, VIN = 0 V 200 200 200 μA IOZH 6, 7 Three-State Leakage Current @ VDD_EXT = Max, VIN = VDD_EXT Max 10 10 10 μA IOZL

6 Three-State Leakage

@ VDD_EXT = Max, VIN = 0 V –10 –10 –10 μA IOZLPU

7 Three-State Leakage

@ VDD_EXT = Max, VIN = 0 V 200 200 200 μA IOZHPD

8 Three-State Leakage

@ VDD_EXT = Max, VIN = VDD_EXT Max 200 200 200 μA IDD_RTC VDD_RTC Current @ V DD_RTC = 3.0, TJ = 25°C 0.76 0.76 0.76 μA IDD-INTYP

9 Supply Current (Internal) f CCLK > 0 MHz Table 14

× ASF Table 14 Table 15 × ASF Table 14 Table 15 × ASF mA CIN 10, 11 Input Capacitance T CASE = 25°C 5 5 5 pF 1 Specifications subject to change without notice. 2 Applies to output and bidirectional pins: ADDR23-0, DATA15-0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, RESETOUT,MLBSIG, MLBDAT, MLBDO, MLBSO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, MS0-1. 3 See Output Drive Currents on Page 64 for typical drive current capabilities. 4 Applies to input pins: BOOT_CFGx, CLK_CFGx, TCK, RESET , CLKIN. 5 Applies to input pins with internal pull-ups: TRST , TMS, TDI. 6 Applies to three-statable pins: TDO, MLBDAT, MLBSIG, MLBDO, and MLBSO. 7 Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU . 8 Applies to three-statable pin with pull-down: SDCLK. 9 See Engineer-to-Engineer Note “Estimatin g Power Dissipation for ADSP-2147x SHARC Processors” for further information. 10Applies to all signal pins. 11Guaranteed, but not tested.

1. Internal power consumption
2. External power consumption
3. Static, due to leakage current. Table 14 shows the static cur-

temperature (TJ) and core voltage (VDD_INT).

1. Dynamic (IDD-DYNAMC), due to transistor switching charac-

dependent data in Table 15 to calculate this part. Table 13. Activity Scaling Factors (ASF) 1

1 See Estimating Power for ADSP-214xx SHARC Processors (EE-348) for more

information on the explanation of the po wer vectors specific to the ASF table.

2 Ratio of continuous instruction loop (c ore) to SDRAM control code reads and

Table 14. Static Current—I DD-STATIC (mA)1 1 Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 20.

ADSP-21477/ADSP-21478/ADSP-21479 Rev. B | Page 23 of 76 | March 2012 MAXIMUM POWER DISSIPATION See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2147x SHARC Processors” for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page 65.

PACKAGE INFORMATION

The information presented in Figure 4 provides details about the package branding. For a complete listing of product avail- ability, see Ordering Guide on Page 75. ESD SENSITIVITY ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 17 may cause perma- nent damage to the device. These are stress ratings only; functional operation of the device at these or any other condi- tions greater than those indicated in Operating Conditions on Page 20 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 15. Baseline Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1, 2

200 N/A N/A 162 170 178 186 194

266 N/A N/A 215 225 234 246 256

300 N/A N/A N/A N/A 264 279 291

1 The values are not guaranteed as standalone maximum specifications. They must be combin ed with static current per the equations of Electrical Characteristics on Page 21 . 2 Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 20. Figure 4. Typical Package Brand Table 16. Package Br and Information1 ESD (electrostatic discharge) sensitive device. may occur on devices subjected to high energy ESD. avoid performance degradation or loss of functionality.

Figure 5. Core Clock and System Clock Relationship to CLKIN

4096 CLKIN

*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS fINPUT. THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.

Table 19. While no specific power-up sequencing is required that the system designs should take into account.

• No power supply should be powered up for an extended period of time (>200 ms) before another supply starts to ramp up.
• I f t h e VDD_INT power supply comes up after VDD_EXT, any pin, such as RESETOUT and RESET, may actually drive momentarily until the VDD_INT rail has powered up. Systems sharing these signals on the board must determine if there are any issues that need to be addressed based on this behavior. Note that during power-up, when the VDD_INT power supply comes up after VDD_EXT, a leakage current of the order of three- state leakage current pull-up, pull-down, may be observed on any pin, even if that is an input only (for example, the RESET pin), until the VDD_INT rail has powered up.

Table 19. Power-Up Sequencing Timing Requirements (Processor Startup)

1 CLKIN Valid After VDD_INT and VDD_EXT Valid 0 200 ms

from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem. a 25 ms maximum oscillator startup time if using the XTAL pin an d internal oscillator circuit in conjunction with an external c rystal. propagate default states at all I/O pins. Figure 6. Power-Up Sequencing

Table 20. Clock Input 1 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL. 2 Any changes to PLL control bits in the PMCTL regis ter must meet core clock timing specification tcclk. 3 See Figure 5 on Page 25 for VCO diagram. 4 Actual input jitter should be combined with ac specifications for accurate timing analysis. 5 Jitter specification is maximum peak-to -peak time interval error (TIE) jitter. Figure 7. Clock Input

16.67 MHz crystal and a PLL multiplier ratio 16:1

plier bits in the PMCTL register. Figure 8. 266 MHz Operation (Fundamental Mode Crystal) CHOOSE C1 AND C2 BASED ON THE CRYSTAL Y1. CHOOSE R2 TO LIMIT CRYSTAL DRIVE POWER. Table 21. Reset

1 RESET Pulse Width Low 4 × t CK ns

Vdd and CLKIN (not including start-up time of external clock oscillator). Figure 9. Reset

Table 28. DAI/DPI Pin to Pin Routing Figure 16. DAI Pin to Pin Direct Routing

Table 29. Precision Clock Generator (Direct Pin Routing)

1 Output Clock Period 2 × t PCGIP – 1 2 × t PCGIP – 1 ns

Figure 17. Precision Clock Generator (Direct Pin Routing)

Page 15 for more information on flag use. Table 30. Flags 1 This is applicable when the Flags are connected to DPI_P14–1, ADDR23–0, DATA7–0 and FLAG3–0 pins. Figure 18. Flags

Table 31. SDRAM Interface Timing

133 MHz 150 MHz

more information on hardware design guidelines for the SDRAM interface. 2 Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDQM, SDCKE.

2 Command, ADDR, Data Hold After SDCLK 1 1 ns

Figure 19. SDRAM Interface Timing

Table 32. AMI Read

2 Address Selects to AMI_RD Low t SDCLK – 5 ns

W = (number of wait states specified in AMICTLx register) × t SDCLK. H = (number of hold cycles specified in AMICTLx register) × t SDCLK. 1 Data delay/setup: System must meet tDAD, tDRLD, or tSDS. 2 The falling edge of AMI_MSx, is referenced. 3 The maximum limit of timing requirement values for t DAD and tDRLD parameters are applicable for the case where AMI_ACK is always high. 4 Note that timing for AMI_ACK, ADDR, DATA, AMI_RD , AMI_WR, and strobe timing parameters only apply to asynchronous access mode. 5 Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions on Page 64 for the calculation of hold times given capacitive and dc loads. 6 AMI_ACK delay/setup: User must meet tdaak, or tdsak, for deassertion of AMI_ACK (low).

Figure 20. AMI Read

Table 33. AMI Write 1 AMI_ACK delay/setup: System must meet t DAAK, or tDSAK, for deassertion of AMI_ACK (low). 2 The falling edge of AMI_MSx is referenced. 3 Note that timing for AMI_ACK, ADDR, DATA, AMI_RD , AMI_WR, and strobe timing parameters only applies to asynchronous access mode. 4 See Test Conditions on Page 64 for calculation of hold times given capacitive and dc loads. 5 For Write to Write: tSDCLK + H, for both same bank and different bank. For Write to Read: 3 × tSDCLK + H, for the same bank and different banks.

Figure 21. AMI Write

2) data delay and data setup and hold, and 3) SCLK width. Table 34. Serial Ports—External Clock

1 Frame Sync Setup Before SCLK

1 Frame Sync Hold After SCLK

2 Frame Sync Delay After SCLK

2 Frame Sync Hold After SCLK

2 Transmit Data Delay After Transmit SCLK 15 15 ns

2 Transmit Data Hold After Transmit SCLK 2 2 ns

1 Referenced to sample edge.

Table 35. Serial Ports—Internal Clock

2 Frame Sync Delay After SCLK (Internally Generated

2 Frame Sync Hold After SCLK (Internally Generated

2 Transmit Data Delay After SCLK 4 4 ns

1 Referenced to the sample edge.

Figure 22. Serial Ports

Table 36. Serial Ports—External Late Frame Sync

1 Data Delay from Late External Transmit Frame Sync or

1 The tDDTLFSE and tDDTENFS parameters apply to left-justified as well as DSP serial mode, and MCE = 1, MFD = 0. Figure 23. External Late Frame Sync 1 1 This figure reflects changes made to support left-justified mode.

Table 37. Serial Ports—Enable and Three-State

1 Data Enable from External Transmit SCLK 2 2 ns

1 Data Disable from External Transmit SCLK 23 20 ns

1 Data Enable from Internal Transmit SCLK –1 –1 ns

Figure 24. Enable and Three-State

Table 38. Serial Ports—TD V (Transmit Data Valid) Figure 25. Serial Ports—TDM Internal and External Clock

Table 39. Input Data Port (IDP) can be either CLKIN or any of the DAI pins. Figure 26. IDP Master Timing

Table 40. PDAP is the parallel mode operation of Channel 0 of provided through the ADDR23–0 pins or over the DAI pins. Table 40. Parallel Data Acquisition Port (PDAP) 1 Source pins of DATA and control are ADDR23–0 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG. Figure 27. PDAP Timing

Table 41 are valid at the DAI_P20–1 pins. Table 41. ASRC, Serial Input Port

1 Frame Sync Setup Before Serial Clock Rising Edge 4 ns

1 Data Setup Before Serial Clock Rising Edge 4 ns

can be either CLKIN or any of the DAI pins. Figure 28. ASRC Serial Input Port Timing

Table 42. ASRC, Serial Output Port

1 Frame Sync Setup Before Serial Clock Rising Edge 4 4 ns

1 Transmit Data Delay After Serial Clock Falling Edge 2 × t PCLK 13 ns

1 Transmit Data Hold After Serial Clock Falling Edge 1 1 ns

be either CLKIN or any of the DAI pins. Figure 29. ASRC Serial Output Port Timing

ADDR23–8/DPI_14–1 pins are configured as PWM. Table 43. Pulse-Width Modulation (PWM) Timing Figure 30. PWM Timing

below are valid at the DAI_P20–1 pins. The S/PDIF transmitter requires an oversampling clock input. generate the internal biphase clock. Table 47. S/PDIF Transmitter Input Data Timing

1 Frame Sync Hold After Serial Clock Rising Edge 3 3 ns

1 Data Hold After Serial Clock Rising Edge 3 3 ns

can be either CLKIN or any of the DAI pins. Figure 34. S/PDIF Transmitter Input Timing Table 48. Oversampling Clock (TxC LK) Switching Characteristics

(digital PLL) generates the 512 × FS clock. Table 49. S/PDIF Receiver Inte rnal Digital PLL Mode Timing 1 The serial clock frequency is 64 × frame sync (FS) where FS = the frequency of LRCLK. Figure 35. S/PDIF Receiver Internal Digital PLL Mode Timing

Table 50. SPI Interface Protocol—Master Switching and Timing Specifications Figure 36. SPI Master Timing

Table 51. SPI Interface Protocol—Slave Switching and Timing Specifications Interface Port (SPI)” chapter. Figure 37. SPI Slave Timing

fication document rev 3.0 for more details. Table 52. MLB Interface, 3-Pin Specifications

512 FS/256 FS

1 MLBCLK Pulse Width Variation

512 FS/256

2 Bus Hold Time

1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, mea sured in ns peak-to-peak (p-p). minimized while meeting the maximum capacitive load listed.

Figure 38. MLB Timing (3-Pin Interface) Table 53. MLB Interface, 5-Pin Specifications

1 MLBCLK Pulse Width Variation 2 ns p-p

2 DAT/SIG Input Setup Time 3 ns

3 DO/SO Low From MLBCLK High

1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, mea sured in ns peak-to-peak (p-p). 2 Gate delays due to OR’ing logic on the pins must be accounted for. external pull-down resistors are required to keep the outputs fr om corrupting the MediaLB signal lines when not being driven.

Table 54. Shift Register

1 DAI_P08–01 (SR_SDI) Setup Before DAI_P08–01 (SR_SCLK) Rising Edge 7 ns

1 DAI_P08–01 (SR_SDI) Hold After DAI_P08–01 (SR_SCLK) Rising Edge 2 ns

2 SR_SCLK to SR_LAT Setup 2 ns

3 SR_SDO Hold After SR_SCLK Rising Edge 3 ns

3 SR_LDO Hold After SR_LAT Rising Edge 3 ns

3 SR_LDO Hold After DAI_P08–01 (SR_LAT) Rising Edge 3 ns

1 Any of the DAI_P08–01 pins can be routed to the shift register clock, latch clock and serial data input via the SRU. 3 For setup/hold timing requirements of off-chip shift register interfacing devices. 4 SPORTx serial clock out, frame sync out, and serial data outp uts are routed to shift register block internally and are also routed onto DAI_P20–01. 5 PCG serial clock output is routed to SPORT and shift register bl ock internally and are also routed onto DAI_P20–01. The SPORTs generate SR_LAT and SDI internally. 6 PCG Serial clock and frame sync outputs are routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SDI internally.

tions, see the ADSP-214xx SHARC Hardware Reference Manual. see the ADSP-214xx SHARC Hardware Reference Manual. Table 55. JTAG Test Access Port and Emulation

1 System Inputs Hold After TCK High 18 18 ns

MLBSO, SR_SDO, SR_LDO, and EMU. Figure 46. IEEE 1149.1 JTAG Test Access Port

die temperature of the chip. the common temperature sensor chips available. Table 60. Thermal Diode Parameters—Transistor Model 1

2 Forward Bias Current 10 300 μA

1 Analog Devices does not recommend operation of the thermal diode under reverse bias. 2 Analog Devices does not recommend operation of the thermal diode under reverse bias. 3 Specified by design characterization. q = electronic charge, VBE = voltage across the diode, k = Boltzmann constant, and T = absolute temperature (Kelvin). 5 The series resistance (RT) can be used for more accurate readings as needed.

Table 62 lists the 88-Lead LFCSP_VQ package lead names. Table 61. 88-Lead LFCSP_VQ Lead Assignments (Numerical by Lead Number) Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.

Table 62 lists the 100-Lead LQFP_EP lead names. Table 62. 100-Lead LQFP_EP Lead Assign ments (Numerical by Lead Number) Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.

• Lead no. 101 is the GND supply (see Figure 55 and Figure 56) for the processor; this pad must be robustly connected to GND.

Table 63. 196-Ball CSP_BGA Ball Assi gnment (Numerical by Ball No.)

LQFP_EP and 196-ball CSP_BGA RoHS compliant packages. Figure 57. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ 1] 1 For information relating to the exposed pad on the CP-88-5 package, see the table endnote on Page 67.

0.60 MAX

Figure 58. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP 1] 1 For information relating to the exposed pad on the SW-100-2 package, see the table endnote on Page 69. Figure 59. 196-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] SECTIONS OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.

0.35 NOM

0.30 MIN

Specifications section of this data sheet carefully. Table 64. Automotive Product Models specification, which is the only temperature specification. 3 Contains multichannel audio decoders from Dolby and DTS. 4 Contains Digital Transmission Content Protecti on (DTCP) from DTLA. User must have current license from DTLA to order this product.

ADSP-21477/ADSP-21478/ADSP-21479 Rev. B | Page 75 of 76 | March 2012 ORDERING GUIDE Model1 1 Z =RoHS compliant part. Temperature Range2 2 Referenced temperature is ambient temperature. The ambie nt temperature is not a specification. Please see Operating Conditions on Page 20 for junction temperature (TJ) specification, which is the only temperature specification. On-Chip SRAM Processor Instruction Rate (Max) Package Description Package Option ADSP-21477KCPZ-1A 0°C to +70°C 2M Bits 200 MHz 88-Lead LFCSP_VQ CP-88-5 ADSP-21477KSWZ-1A 0°C to +70°C 2M Bits 200 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21477BCPZ-1A –40 °C to +85°C 2M Bits 200 MHz 88-Lead LFCSP_VQ CP-88-5 ADSP-21478KCPZ-1A 0°C to +70°C 3M Bits 200 MHz 88-Lead LFCSP_VQ CP-88-5 ADSP-21478BCPZ-1A –40 °C to +85°C 3M Bits 200 MHz 88-Lead LFCSP_VQ CP-88-5 ADSP-21478BBCZ-2A –40°C to +85°C 3M Bits 266 MHz 196-Ball CSP_BGA BC-196-8 ADSP-21478BSWZ-2A –40°C to +85°C 3M Bits 266 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21478KBCZ-1A 0°C to +70°C 3M Bits 200 MHz 196-Ball CSP_BGA BC-196-8 ADSP-21478KBCZ-2A 0°C to +70°C 3M Bits 266 MHz 196-Ball CSP_BGA BC-196-8 ADSP-21478KBCZ-3A 0°C to +70°C 3M Bits 300 MHz 196-Ball CSP_BGA BC-196-8 ADSP-21478KSWZ-1A 0°C to +70°C 3M Bits 200 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21478KSWZ-2A 0°C to +70°C 3M Bits 266 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21479KCPZ-1A 0°C to +70°C 5M Bits 200 MHz 88-Lead LFCSP_VQ CP-88-5 ADSP-21479BCPZ-1A –40 °C to +85°C 5M Bits 200 MHz 88-Lead LFCSP_VQ CP-88-5 ADSP-21479BBCZ-2A –40°C to +85°C 5M Bits 266 MHz 196-Ball CSP_BGA BC-196-8 ADSP-21479BSWZ-2A –40°C to +85°C 5M Bits 266 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21479KBCZ-1A 0°C to +70°C 5M Bits 200 MHz 196-Ball CSP_BGA BC-196-8 ADSP-21479KBCZ-2A 0°C to +70°C 5M Bits 266 MHz 196-Ball CSP_BGA BC-196-8 ADSP-21479KBCZ-3A 0°C to +70°C 5M Bits 300 MHz 196-Ball CSP_BGA BC-196-8 ADSP-21479KSWZ-1A 0°C to +70°C 5M Bits 200 MHz 100-Lead LQFP_EP SW-100-2 ADSP-21479KSWZ-2A 0°C to +70°C 5M Bits 266 MHz 100-Lead LQFP_EP SW-100-2

Rev. B | Page 76 of 76 | March 2012 ADSP-21477/ADSP-21478/ADSP-21479 ©2012 An alog Devices, In c. A ll rights reserved. T rademarks and registered trademarks are the p roperty of their respective owners. D09017-0-3/12(B)