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SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Information furnished by Analog Devices is believed to be accurate and reliable. infringements of patents or other rights of third parties that may result from its use. registered trademarks are the property of their respective companies. Fax: 781.326.3113 ©2008 Analog Devices, Inc. All rights reserved. material that is subject to change without notice. converters, input data port, and more. ucts on Page 59 and Ordering Guide on Page 59. Figure 1. Function al Block Diagram

24 ADDRESS

4 BLOCKS OF

Rev. PrA | Page 2 of 60 | November 2008 ADSP-21462W/ADSP-21465W/ADSP-21467 Preliminary Technical Data KEY FEATURES—PROCESSOR CORE At up to 450 MHz core instruction rate, the processor per- forms at 2.7 GFLOPS/900 MMACs

5 Mbits on-chip RAM, 4 Mbits on-chip ROM for simultaneous

access by the core processor and DMA DDR2 DRAM interface (16-bit) operating at maximum fre- quency of half the core clock frequency Dual data address generators (DAGs) with modulo and bit- reverse addressing Zero-overhead looping with single-cycle loop setup, provid- ing efficient program sequencing VISA (variable instruction set) execution support Single instruction multiple data (SIMD) architecture provides: Two computational processing elements Concurrent execution Code compatibility with other SHARC family members at the assembly level Parallelism in buses and computational units allows: Single cycle executions (with or without SIMD) of a mul- tiply operation, an ALU operation, a dual memory read or write, and an instruction fetch Transfers between memory and core at a sustained

7.2 Gbytes/second bandwidth

FFT accelerator implements radix-2 complex/real input, com- plex output FFT with no core intervention IIR accelerators perform dedicated IIR filtering with high-per- formance, fixed- and floating-point processing capabilities with no core intervention FIR accelerators perform dedicated FIR filtering with high- performance, fixed- and floating-point processing capabil- ities with no core intervention Program sequencer can execute code directly from external memory bank 0 (SRAM, as well as DDR2 DRAM). This allows more options to a user in terms of code storage. New opcodes of 16 and 32 bits are supported in addition to the existing 48 bit opcodes. Variable Instruction Set Archi- tecture (VISA) execution from external DDR2 DRAM memory is also supported. INPUT/OUTPUT FEATURES Two 8-bit wide link ports can connect to the link ports of other SHARCs or peripherals. Link ports are bidirectional programmable ports having eight data lines, an acknowl- edge line and a clock line DMA controller supports

67 DMA channels for transfers between internal memory

and a variety of peripherals DMA transfers at peripheral clock speed, in parallel with full-speed processor execution External port provides glueless connection to 16-bit wide synchronous DDR2 DRAM using a dedicated DDR2 DRAM controller, and 8-bit wide asynchronous memory devices using asynchronous memory interface (AMI) Programmable wait state options (for AMI) 2 to 31 DDR2_CLK cycles Delay-line DMA engine maintains circular buffers in exter- nal memory with tap/offset based reads 16-bit data access for synchronous DDR2 DRAM memory 8-bit data access for asynchronous memory 4 memory select lines allows multiple external memory devices Digital audio interface (DAI) includes eight serial ports, four precision clock generators, an input data port, an S/PDIF transceiver, and a signal routing unit Digital peripheral interface (DPI) includes, two timers, one UART, and two SPI ports, a DTCP cipher (ADSP-21462W and ADSP-21465W), and a two-wire interface port Outputs of PCG A and B can be routed through DAI pins Outputs of PCG C and D can be driven on to DAI as well as DPI pins Eight dual data line serial ports — each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces

such as H.100/H.110 Up to 16 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port (IDP), configurable as eight channels of serial data or seven channels of serial data and up to a 20-bit wide parallel data channel Signal routing unit provides configurable and flexible con- nections between the various peripherals and the DAI/DPI components 4 independent asynchronous sample rate converters (ASRC). Each converter has separate serial input and output ports, a de-emphasis filter providing up to –128 dB SNR perfor- mance, stereo sample rate converter and supports left- justified, I2S, TDM, and right-justified modes and 24-, 20-, 18-, and 16-audio data word lengths. An MLB (media local bus) interface allows the processor to support for both 3-pin as well as 5-pin media local bus pro- tocols (ADSP-21462W and ADSP-21465W). 2 muxed flag/IRQ lines 1 muxed flag/IRQ /AMI_MS pin 1 muxed flag/Timer expired line /AMI_MS pin S/PDIF-compatible digital audio receiver/transmitter sup- ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards Left-justified, I2S or right-justified serial data input with 16-, 18-, 20- or 24-bit word widths (transmitter) Pulse-width modulation provides:

16 PWM outputs configured as four groups of four outputs

supports center-aligned or edge-aligned PWM waveforms PLL has a wide variety of software and hardware multi- plier/divider ratios Thermal diode to monitor die temperature Available in 19 mm by 19 mm PBGA package (see Ordering Guide on Page 59)

ADSP-21462W/ADSP-21465W/ADSP-21467Preliminary Technical Data Rev. PrA | Page 3 of 60 | November 2008 TABLE OF CONTENTS

REVISION HISTORY

11/08—Revision PrA Initial version

innovative digital applications interface (DAI). running at 400 MHz (ADSP-21462W, ADSP-21465W). Table 1. SHARC Family Features

2 Yes Yes No

1 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx,

management, delay, speaker equalization, graphic equalization, and more. www.analog.com for complete information.

2 The ADSP-21462W and ADSP-21465W proc essors provide the Digital Trans-

your Analog Devices sales office for more information. Table 2. Processor Benchmarks

1 Assumes two files in multichannel SIMD mode

Table 1. SHARC Family Features (Continued)

ADSP-21462W/ADSP-21465W/ADSP-21467Preliminary Technical Data Rev. PrA | Page 5 of 60 | November 2008 The ADSP-21462W/ADSP-21465W/ADSP-21467 continues SHARC’s industry-leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. The block diagram on Page 1 illustrates the following architec- tural features:

• Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core pro- cessor cycle
• Two programmable interval timers with external event counter capabilities
• O n - c h i p S R A M
• JTAG test access port
• FFT, FIR, IIR accelerators The block diagram of the processor on Page 1 also illustrates the following architectural features:
• DMA controller
• Digital applications interface that includes four precision clock generators (PCG), an S/PDIF-compatible digital audio receiver/transmitter with four independent asyn- chronous sample rate converters, an input data port (IDP) with eight serial ports, DTCP cipher, eight serial interfaces, a 20-bit parallel input port (PDAP), and a flexible signal routing unit (DAI SRU).
• Digital peripheral interface that includes two timers, one UART, two serial peripheral interfaces (SPI), a 2-wire interface (TWI), and a flexible signal routing unit (DPI SRU). FAMILY CORE ARCHITECTURE The ADSP-21462W/ADSP-21465W/ADSP-21467 is code com- patible at the assembly level with the ADSP-2137x, ADSP- 2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-21462W/ADSP-21465W/ADSP-21467 shares architec- tural features with the ADSP-2126x, ADSP-2136x, ADSP- 2137x, and ADSP-2116x SIMD SHARC processors, as detailed in the following sections. SIMD Computational Engine The ADSP-21462W/ADSP-21465W/ADSP-21467 contains two computational processing elements that operate as a single- instruction, multiple-data (SIMD) engine. The processing ele- ments are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruc- tion is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms. Entering SIMD mode also has an effect on the way data is trans- ferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the band- width between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all opera- tions in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing ele- ments. These computation units support IEEE 32-bit single- precision floating-point, 40-bit extended precision floating- point, and 32-bit fixed-point data formats. Data Register File A general-purpose data register file is contained in each pro- cessing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the processor’s enhanced Harvard architecture, allow unconstrained data flow between computa- tion units and internal memory. The registers in PEX are referred to as R0-R15 and in PEY as S0-S15. Single-Cycle Fetch of Instruction and Four Operands The ADSP-21462W/ADSP-21465W/ADSP-21467 features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1 on page 1). With the its separate program and data memory buses and on- chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache The ADSP-21462W/ADSP-21465W/ADSP-21467 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selec- tive—only the instructions whose fetches conflict with PM bus

Rev. PrA | Page 6 of 60 | November 2008 ADSP-21462W/ADSP-21465W/ADSP-21467 Preliminary Technical Data data accesses are cached. This cache allows full speed execution of core, looped operations such as digital filter multiply-accu- mulates, and FFT butterfly processing. Data Address Generators With Zero-Overhead Hardware Circular Buffer Support The ADSP-21462W/ADSP-21465W/ADSP-21467’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buff- ers allow efficient programming of delay lines and other data structures required in digital signal processing, and are com- monly used in digital filters and Fourier transforms. The two DAGs of the processors contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and sim- plify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21462W/ADSP-21465W/ADSP-21467 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. Variable Instruction Set Architecture In addition to supporting the standard 48-bit instructions from previously existing SHARC family of processors, the ADSP- 21462W/ADSP-21465W/ADSP-21467 support new instruc- tions of 16 and 32 bits in addition to the existing 48 bit instructions. This feature, called Variable Instruction Set Archi- tecture (VISA), is based on dropping redundant/unused bits within the 48-bit instruction to create more efficient and com- pact code. The program sequencer will now support fetching these 16-bit and 32-bit instructions as well in addition to the standard 48-bit instructions, both from internal as well as exter- nal memory. Source modules will need to be built using the VISA option, in order to allow code generation tools to create these more efficient opcodes. FFT Accelerator FFT accelerator implements radix-2 complex/real input, com- plex output FFT with no core intervention. FIR Accelerators The FIR (finite impulse response) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four MAC units. A controller manages the accelerator. The FIR accelerator runs at the peripheral clock frequency. IIR Accelerators The IIR (infinite impulse response) accelerator consists of a 1440 word coefficient memory for storage of biquad coeffi- cients, a data memory for storing the intermediate data and one MAC unit. A controller manages the accelerator. The IIR accel- erator runs at the peripheral clock frequency. MEMORY The ADSP-21462W/ADSP-21465W/ADSP-21467 adds the fol- lowing architectural features to the SIMD SHARC family core. On-Chip Memory The processors contain 5 Mbits of internal RAM. Each block can be configured for different combinations of code and data storage (see Table 3 on Page 7). Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The ADSP-21462W/ADSP-21465W/ADSP-21467 memory architecture, in combination with its separate on-chip buses, allow two data transfers from the core and one from the I/O processor, in a single cycle. The processor’s SRAM can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 5 megabit. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float- ing-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point for- mats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. The memory map in Table 3 displays the internal memory address space of the ADSP-21462W/ADSP-21465W/ADSP- 21467. The 48-bit space section describes what this address range looks like to an instruction that retrieves 48-bit memory. The 32-bit section describes what this address range looks like to an instruction that retrieves 32-bit memory. EXTERNAL MEMORY The external port on the ADSP-21462W/ADSP- 21465W/ADSP-21467 SHARC provides a high performance, glueless interface to a wide variety of industry-standard memory devices. The external port may be used to interface to synchro- nous and/or asynchronous memory devices through the use of its separate internal DDR2 memory controller. The 16-bit DDR2 DRAM controller connects to industry-standard syn- chronous DRAM devices, while the second 8-bit asynchronous memory controller is intended to interface to a variety of mem- ory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired combination of syn- chronous and asynchronous device types. Non DDR2 DRAM external memory address space is shown in Table 4.

from DDR2 space is different for VISA and non-VISA mode. supported. Delay line DMA functionality supported. ure the DDR2 DRAM banks to support memory devices. Table 3. ADSP-21462W/ADSP-21465W/ADS P-21467 Internal Memory Space

ous by the memory controller logic. throughput of TBD Mbps using a TBD MHz external bus speed. ing from bank select 1, and support for delay line DMA.

• Distributed, on-chip arbitration for the shared external bus
• Fixed and rotating pr iority bus arbitration
• Bus time-out logic
• Bus lock Multiple processors can share the external bus with no addi- tional arbitration logic. Arbitration logic is included on-chip to allow the connection of up to TBD processors. Bus arbitration is accomplished through the BR6-1 signals and the priority scheme for bus arbitration is determined by the set- ting of the RPBA pin. Table 6 on Page 13 provides descriptions of the pins used in multiprocessor systems. INPUT/OUTPUT FEATURES The ADSP-21462W and ADSP-21465W I/O processors provide 67 channels of DMA, while ADSP-21467 I/O processors pro- vide 36 channels of DMA as well as an extensive set of peripherals. These include a 20 lead digital applications inter- face, which controls:
• Eight serial ports
• S/PDIF receiver/transmitter
• Four precision clock generators
• Input data port/parallel data acquisition port
• Four asynchronous sample rate converters The ADSP-21462W/ADSP-21465W/ADSP-21467 processor also contains a 14 lead digital peripheral interface, which controls:
• Two general-purpose timers
• Two serial peripheral interfaces
• One universal asynchronous receiver/transmitter (UART)
• A n I 2C®-compatible 2-wire interface
• Two PCGs (C and D) can al so be routed through DPI DMA Controller The processor’s on-chip DMA controller allows data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously exe- cuting its program instructions. DMA transfers can occur between the ADSP-21462W/ADSP-21465W/ADSP-21467’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the paral- lel data acquisition port (PDAP) or the UART. Sixty-seven channels of DMA are available on the ADSP-21462W and ADSP-21465W devices, and thirty-six channels on the ADSP-21467. The breakdown is as follows: 16 via the serial ports, eight via the input data port, two for the

Table 5. External Memory for DDR2 DRAM Addresses Table 4. External Memory for Non DDR2 DRAM Addresses

ADSP-21462W/ADSP-21465W/ADSP-21467Preliminary Technical Data Rev. PrA | Page 9 of 60 | November 2008 UART, two for the SPI interface, two for the external port, two for DTCP (or memory-to-memory data transfer when DTCP is not used), two for the link port, two for the FFT/FIR/IIR accel- erators, and up to 31 DMA channels for the media local bus interface on the ADSP-21462W and ADSP-21465W. Programs can be downloaded to the ADSP-21462W/ADSP- 21465W/ADSP-21467 using DMA transfers. Other DMA fea- tures include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers. Delay Line DMA The ADSP-21462W/ADSP-21465W/ADSP-21467 processor provides delay line DMA functionality. This allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. Scatter/Gather DMA The ADSP-21462W/ADSP-21465W/ADSP-21467 processor provides scatter/gather DMA functionality. This allows processor DMA reads/writes to/from non-contin- geous memory blocks. Digital Applications Interface (DAI) The digital applications interface (DAI) provides the ability to connect various peripherals to any of the DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU), shown in Figure 1. The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be intercon- nected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with noncon- figurable signal paths. The DAI also includes eight serial ports, four precision clock generators (PCG), S/PDIF transceiver, four ASRCs, and an input data port (IDP). The IDP provides an additional input path to the SHARC core, configurable as either eight channels of serial data, or a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’s serial ports. Serial Ports The ADSP-21462W/ADSP-21465W/ADSP-21467 features eight synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be pro- grammed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports can support up to 16 transmit or 16 receive channels of audio data when all eight SPORTs are enabled, or four full duplex TDM streams of 128 channels per frame. The serial ports operate at a maximum data rate of 56.25 Mbps. Serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated DMA chan- nels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT pro- vides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in five modes:

• Standard DSP serial mode
• M u l t i c h a n n e l ( T D M ) m o d e 2S mode
• P a c k e d I2S mode
• Left-justified sample pair mode Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over var- ious attributes of this mode. Each of the serial ports supports the left-justified sample pair and I2S protocols (I2S is an industry-standard interface com- monly used by audio codecs, ADCs, and DACs such as the Analog Devices AD183x family), with two data pins, allowing four left-justified sample pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 32 I2S chan- nels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I 2S modes, data- word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional μ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be inter- nally or externally generated. The serial ports also contain frame sync error detection logic where the serial ports detect frame syncs that arrive early (for example frame syncs that arrive while the transmission/recep- tion of the previous word is occurring). All the serial ports also share one dedicated error interrupt. S/PDIF-Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter The S/PDIF receiver/transmitter has no separate DMA chan- nels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/transmitter can be formatted as left justified, I 2S or right justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), and are controlled by the SRU control registers. The sample rate converter (ASRC) contains four ASRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 128 dB SNR. The ASRC block is used to perform synchronous or asyn-

Rev. PrA | Page 10 of 60 | November 2008 ADSP-21462W/ADSP-21465W/ADSP-21467 Preliminary Technical Data chronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to con- vert multichannel audio data without phase mismatches. Finally, the ASRC can be used to clean up audio data from jit- tery clock sources such as the S/PDIF receiver. Digital Transmission Content Protection The DTCP specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance digital buses, such as the IEEE 1394 standard. Only legitimate entertainment content delivered to a source device via another approved copy protection system (such as the DVD content scrambling system) will be protected by this copy protection system. This feature is available on the ADSP-21462W and ADSP-21465W processors only. Licensing through DTLA is required for these products. Visit www.dtcp.com for more information. Digital Peripheral Interface (DPI) The digital peripheral interface provides connections to two serial peripheral interface ports (SPI), one universal asynchro- nous receiver-transmitter (UART), 12 flags, a 2-wire interface (TWI), and two general-purpose timers. Serial Peripheral (Compatible) Interface The ADSP-2146x SHARC processors contain two serial periph- eral interface ports (SPIs). The SPI is an industry-standard synchronous serial link, enabling the SPI-compatible port to communicate with other SPI compatible devices. The SPI con- sists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multi- master environment by interfacing with up to four other SPI- compatible devices, either acting as a master or slave device. The SPI-compatible peripheral implementation also features pro- grammable baud rate and clock phase and polarities. The SPI- compatible port uses open drain drivers to support a multimas- ter configuration and to avoid data contention. UART Port The processors provide a full-duplex Universal Asynchronous Receiver/Transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simpli- fied UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART also has multiprocessor communication capa- bility using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface stan- dard. The UART port also includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller trans- fers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The UART port's baud rate, serial data format, error code gen- eration and status, and interrupts are programmable:
• Supporting bit rates ranging from (f PCLK/ 1,048,576) to (fPCLK/16) bits per second.
• Supporting data formats from 7 to 12 bits per frame.
• Both transmit and receive operations can be configured to generate maskable interrupts to the processor. In conjunction with the general-purpose timer functions, auto- baud detection is supported. Timers The ADSP-21462W/ADSP-21465W/ADSP-21467 has a total of three timers: a core timer that can generate periodic software interrupts and two general purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes:
• P u l s e w a v e f o r m generation mode
• P u l s e w i d t h c ount/capture mode
• External event watchdog mode The core timer can be configured to use FLAG3 as a timer expired signal, and each general-purpose timer has one bidirec- tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A sin- gle control and status register enables or disables both general- purpose timers independently. 2-Wire Interface Port (TWI) The TWI is a bidirectional 2-wire, serial bus used to move 8-bit data while maintaining compliance with the I2C bus protocol. The TWI master incorporates the following features:
• 7-bit addressing
• Simultaneous master and slave operation on multiple device systems with support for multi master data arbitration
• Digital filtering and timed event processing
• 100 kbps and 400 kbps data rates
• Low interrupt rate Pulse-Width Modulation The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM wave- forms. In addition, it can generate complementary signals on

duty cycle values are programmable only once per PWM period. tortion in three-phase PWM inverters. can operate at a maximum frequency of 166 MHz. to 124 bytes of data per media local bus frame. boot modes are only available after the correct key is scanned. options and power supply issues. Processor Hardware Reference. be connected to the same power supply. recommended ferrite chip is the muRata BLM18AG102SN1D). the emulator will not affect target system loading or timing. priate “Emulator Hardware User's Guide”. Figure 2. Analog Power (V DD_A) Filter Circuit

Rev. PrA | Page 12 of 60 | November 2008 ADSP-21462W/ADSP-21465W/ADSP-21467 Preliminary Technical Data DEVELOPMENT TOOLS The ADSP-21462W/ADSP-21465W/ADSP-21467 processors are supported with a complete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other SHARC proces- sors also fully emulates the ADSP-2146x processors. EZ-KIT Lite Evaluation Board For evaluation of the processors, use the EZ-KIT Lite® board being developed by Analog Devices. The board comes with on- chip emulation capabilities and is equipped to enable software development. Multiple daughter cards are available. Designing an Emulator-Compatible DSP Board (Target) The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. Nonintrusive in- circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal fea- tures of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and com- mands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. Evaluation Kit Analog Devices offers a range of EZ-KIT Lite® evaluation plat- forms to use as a cost effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ ® development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product. The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board proces- sor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board Flash device to store user-specific boot code, enabling the board to run as a standal- one unit without being connected to the PC. With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any cus- tom defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, non- intrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-2146x architecture and functionality. For detailed information on the ADSP-21462W/ADSP-21465W/ADSP-21467 family core archi- tecture and instruction set, refer to the ADSP-2136x/ADSP- 2146x SHARC Processor Programming Reference.

(pd) = pull-down resistor, (pu) = pull-up resistor. Table 6. Pin List channel 0 scans the AMI_ADDR23–0 pins for parallel input data. ports (2), and the precision clock generators (4), to the DAI_P20–1 pins. 21462W/ADSP-21465W/ADSP-21467 reads a word from external memory. has fixed internal pull-up resistor1, 2. 21462W/ADSP-21465W/ADSP-21467 writes a word to external memory. AMI_WR has fixed internal pull-up resistor1, 2. DDR2 Address pins. DDR2 address pins. EMR(3) is loaded during the LOAD MODE command.

3 High-Z/

select the corresponding bank. DDR2_DATA15-0 I/O/T 3 High-Z DDR2 Data In/Out. Connect to corresponding DDR2_DATA pins. 7–0 and DM1 corresponds to DDR2_DATA 15–8. sponds to DDR2_DATA 7–0 and DQS1 corresponds to DDR2_DATA 15–8. other DDR2 command pins, defines the operation for the DDR2 to perform. DDR2 Clock. Free running, minimum frequency not guaranteed during reset. requirements) enables the DDR2 termination resistances. instruction is executed, whether or not the condition is true. see the ADSP-2146x SHARC Processor Hardware Reference. FLAG[0]/IRQ0 I/O 3 High-Z FLAG0/Interrupt Request0. FLAG[1]/IRQ1 I/O 3 High-Z FLAG1/Interrupt Request1. I/O 3 High-Z FLAG2/Interrupt Request2/Async Memory Select2. I/O 3 High-Z FLAG3/Timer Expired/Async Memory Select3. I/0 3 High-Z Link Port Data (Link Ports 0-1). I/O 3 High-Z Link Port Clock (Link Ports 0–1). 3 High-Z Link Port Acknowledge (Link Port 0-1). Table 6. Pin List (Continued)

has a fixed internal pull-up resistor1, 2. TDO O /T 3 High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path. fixed internal pull-up resistor1, 2. (pulsed low) after power-up or held low for proper operation of the processor. TRST has a fixed internal pull-up resistor1, 2. Table 9 for a description of the clock configuration modes. a description of the boot modes. input must be asserted (low) at power-up. halted, changed, or operated below the specified frequency. mation, see the ADSP-2146x SHARC Processor Hardware Reference. device and is received by all other MLB devices including the MLB controller.

RxStatus bytes from MLB devices. In 5-pin mode, this pin will be input only. MLB mode. This serves as the output data pin in 5-pin mode. pin MLB mode. This serves as the output signal pin in 5-pin mode. Bus request. Bus request pins for external DDR2 bus arbitration. RPBA I 3 Rotating priority bus arbitration. 1 Pull-up/pull-down resistor can not be enabled/disabled and th e value of the pull-up/pull-down resistor cannot be programmed. 2 Range of fixed pull-up resistor can be between 26k-63k Ω. Range of fixed pull-down resistor can be between 31k-85kΩ.

interface data (input/output), the PDAP (input only), and the FLAGS (input/output). Table 7 provides the pin settings. For details on processor timing, see Timing Specifications and Figure 3 on Page 21. Table 7. Function of Data Pins

000 AMI_ADDR [23:0] AMI_DATA [7:0]

001 Reserved

010 Reserved

011 FLAGS/PWM [15–0] FLAGS [15–0]

100 Reserved

101 PDAP (DATA + CTRL) FLAGS [7–0]

110 Reserved

111 Three-state all pins

Table 8. Boot Mode Selection

000 SPI Slave Boot

001 SPI Master Boot

010 AMI user boot (for 8-bit Flash boot)

011 Reserved

100 Link Port 0 Boot

101 Reserved

Table 9. Core Instruction Rate/ CLKIN Ratio Selection

11 Reserved

Rev. PrA | Page 18 of 60 | November 2008 ADSP-21462W/ADSP-21465W/ADSP-21467 Preliminary Technical Data SPECIFICATIONS OPERATING CONDITIONS Parameter1 1 Specifications subject to change without notice. Description Min Max Unit VDD_INT Internal (Core) Supply Voltage TBD2 2 The expected value is 1.1V and initial customer designs should design with a programmable regulator that can be adjusted from 0.95V to 1.15V +/-50mV TBD2 V VDD_EXT External (I/O) Supply Voltage 3.14 3.46 V VDD_DDR23 3 Applies to DDR2 signals. DDR2 Controller Supply Voltage 1.71 1.89 V VREF DDR2 Reference Voltage 0.84 0.96 V VIH4 4 Applies to input and bidirectional pins: AMI_ADDR23–0, AMI_DATA7–0, FLAG3–0, DAI_Px, DPI_Px, SPIDS, BOOTCFGx, CLKCFGx, CLKOUT (RUNRSTIN), RESET, TCK, TMS, TDI, TRST. High Level Input Voltage @ VDD_EXT = max 2.0 3.6 V VIL4 Low Level Input Voltage @ VDD_EXT = min -0.3 0.8 V VIH_CLKIN5 5 Applies to input pin CLKIN. High Level Input Voltage @ VDD_EXT = max TBD TBD V VIL_CLKIN5 Low Level Input Voltage @ VDD_EXT = min TBD TBD V VIL_DDR2 (DC) DC Low Level Input Voltage -0.3 VREF - 0.12 V VIH_DDR2 (DC) DC High Level Input Voltage VREF + 0.13 V DD_DDR2 + 0.3 V VIL_DDR2 (AC) AC Low Level Input Voltage VREF - 250 mV VIH_DDR2 (AC) AC High Level Input Voltage VREF + 250 mV TJ Junction Temperature 208-Lead PBGA @ TAMBIENT 0 °C to +70 °C 0 125 °C

ADSP-21462W/ADSP-21465W/ADSP-21467Preliminary Technical Data Rev. PrA | Page 19 of 60 | November 2008

ELECTRICAL CHARACTERISTICS

Parameter1 Description Test Conditions Min Typical Max Unit VOH2 High Level Output Voltage @ V DD_EXT = min, IOH = –1.0 mA3 2.4 V VOL2 Low Level Output Voltage @ VDD_EXT = min, IOL = 1.0 mA3 0.4 V IOH_DDR24 Output Source DC Current @ VOH_DDR2 (DC) = VDD_DDR2 -0.28 V TBD mA IOL_DDR24 Output Sink DC Current @ VOL_DDR2 (DC)=0.28 TBD mA VOH_DDR2 @ TBD mA VOL_DDR2 @ TBD mA IIH5, 6 High Level Input Current @ VDD_EXT = max, VIN = VDD_EXT max 10 μA IIL5 Low Level Input Current @ VDD_EXT = max, VIN = 0 V 10 μA IILPU6 Low Level Input Current Pull-up @ V DD_EXT = max, VIN = 0 V TBD μA IOZH7, 8 Three-State Leakage Current @ V DD_EXT = max, VIN = VDD_EXT max 10 μA IOZL7 Three-State Leakage Current @ V DD_EXT = max, VIN = 0 V 10 μA IOZLPU8 Three-State Leakage Current Pull-up @ V DD_EXT = max, VIN = 0 V TBD μA IDD-INTYP9, 10 Supply Current (Internal) TBD TBD mA CIN11, 12 Input Capacitance TBD TBD pF 1 Specifications subject to change without notice. 2 Applies to output and bidirectional pins: AMI_ADDR23-0, AMI_DATA7-0, AMI_RD , AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, CLKOUT. 3 See Output Drive Currents on Page 53 for typical drive current capabilities. 4 Applies to DDR2_ADDR18-0, DDR2_CAS , DDR2_CS3-0, DDR2_DQ1-0, DDR2_DM1-0, DDR2_DQS1-0, DDR2 _DATA15-0, DDR2_RAS, DDR2_WE, DDR2_CLK0, DDR2_CLK0, DDR2_CLK1 and, DDR2_CLK1. 5 Applies to input pins: BOOTCFGx, CLKCFGx, TCK, RESET , CLKIN. 6 Applies to input pins with internal pull-ups: TRST , TMS, TDI. 7 Applies to three-statable pins: FLAG3–0. 8 Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU . 9 Typical internal current data reflects nominal operating conditions. 10See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2146x SHARC Processors” for further information. 11Applies to all signal pins. 12Guaranteed, but not tested.

Table 10. Absolute Maximum Ratings ESD (electrostatic discharge) sensitive device. may occur on devices subjected to high energy ESD. avoid performance degradation or loss of functionality.

(DIVx for the serial ports). ADSP-2136x SHARC Processor Programming Reference. clock, the processor uses an internal phase-locked loop (PLL). tem clock (CLKIN) signal and the processor’s internal clock. INPUT is the input frequency to the PLL in MHz. Figure 3. Core Clock and System Clock Relationship to CLKIN

4096 CLKIN

Table 11. CLKOUT and CCLK Clock Generation Operation

derive parameters from the addition or subtraction of others. operates correctly with other devices. Table 12. Clock Periods

Table 13. Power Up Sequencing Timing Requirements (Processor Startup) of the power supply subsystem. a 25 ms maximum oscillator startup time if using the XTAL pin an d internal oscillator circuit in conjunction with an external c rystal. propagate default states at all I/O pins. Figure 4. Power-Up Sequencing

MHz crystal with the default multiplier of 16:1. Table 14. Clock Input

400 MHz 450 MHz

1 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL. 2 Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL. 3 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK. Figure 5. Clock Input Figure 6. 450 MHz Operation (Fundamental Mode Crystal)

29.125 MHz

Table 22. Precision Clock Generator (Direct Pin Routing) Figure 14. Precision Clock Generator (Direct Pin Routing)

Table 23. Flags Figure 15. Flags

Table 24. DDR2 SDRAM Read Cycle Timing, V DD-DDR2 nominal 1.8V Figure 16. DDR2 SDRAM Controller Input AC Timing

Table 25. DDR2 SDRAM Write Cycle Timing, V DD-DDR2 nominal 1.8V Figure 17. DDR2 SDRAM Controller Output AC Timing

Table 26. Memory Read —Bus Master W = (number of wait states specified in AMICTLx register) × t DDR2_CLK. IC = (number of idle cycles specified in AMICTLx register) x tDDR2_CLK). H = (number of hold cycles specified in AMICTLx register) x t DDR2_CLK. 1 Data delay/setup: System must meet tDAD, tDRLD, or tSDS. 2 The falling edge of AMI_MSx, is referenced. 3 Note that timing for AMI_ACK, AMI_DATA, AMI_RD , AMI_WR, and strobe timing parameters only apply to asynchronous access mode. 4 Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions on Page 53 for the calculation of hold times given capacitive and dc loads. 5 AMI_ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet tDAAK or tDSAK. Figure 18. Memory Read—Bus Master

Table 27. Memory Write —Bus Master 1 AMI_ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet tDAAK or tDSAK. 2 The falling edge of AMI_MSx is referenced. 3 Note that timing for AMI_ACK, AMI_DATA, AMI_RD , AMI_WR, and strobe timing parameters only applies to asynchronous access mode. 4 See Test Conditions on Page 53 for calculation of hold times given capacitive and dc loads. Figure 19. Memory Write —Bus Master

include only one tester guardband. port enable instruction and the DSP enabling the link port. Table 28. Link Ports – Receive 1 LACK goes low with tDLALC relative to rise of LCLK after first by te, but does not go low if the receiver's link buffer is not a bout to fill. Figure 20. Link Ports—Receive

Table 29. Link Ports – Transmit Figure 21. Link Ports—Transmit THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST BYTE TRANSMITTED.

2) data delay and data setup and hold, and 3) SCLK width. Table 30. Serial Ports—External Clock 1 Referenced to sample edge. Table 31. Serial Ports—Internal Clock 1 Referenced to the sample edge.

Table 32. Serial Ports—Enable and Three-State Table 33. Serial Ports—External Late Frame Sync 1 The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0. Figure 22. External Late Frame Sync1 1 This figure reflects changes made to support left-justified sample pair mode. USING THE SRU. THE TIMING SPECIFICATION S PROVIDED HERE ARE VALID AT THE DAI_P20 -1P I NS. ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH SAU.

Figure 23. Serial Ports NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

vided below are valid at the DAI_P20–1 pins. Table 34. Input Data Port (IDP) 1 AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins. Figure 24. IDP Master Timing

Table 35. ASRC, Serial Input Port

1 FS Setup Before SCLK Rising Edge TBD TBD ns

1 FS Hold After SCLK Rising Edge TBD TBD ns

1 SDATA Setup Before SCLK Rising Edge TBD TBD ns

1 SDATA Hold After SCLK Rising Edge TBD TBD ns

1 AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either C LKIN or any of the DAI pins. Figure 25. ASRC Serial Input Port Timing

Table 36. ASRC, Serial Output Port

1 Transmit Data Delay After SCLK Falling Edge TBD TBD ns

1 Transmit Data Hold After SCLK Falling Edge TBD TBD ns

1 AMI_DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. Figure 26. ASRC Serial Output Port Timing

Table 37. PDAP is the parallel mode operation of Channel 0 of remaining four bits can only be sourced through DAI_P4–1. The timing below is valid at the DATA7–0 pins. Table 37. Parallel Data Acquisition Port (PDAP) 1 Source pins of AMI_DATA are DATA7–0 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG. Figure 27. PDAP Timing

AMI_ADDR23-8 pins are configured as PWM. Table 38. Pulse-Width Modulation (PWM) Timing Figure 28. PWM Timing

tions provided below are valid at the DAI_P20–1 pins. input is divided down to generate the biphase clock. Table 39. S/PDIF Transmitter Input Data Timing 1 AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. Figure 32. S/PDIF Transmitter Input Timing Table 40. Over Sampling Clock (TxCLK) Switching Characteristics

(digital PLL) generates the TBD × FS clock. Table 41. S/PDIF Receiver Inte rnal Digital PLL Mode Timing 1 SCLK frequency is TBD x FS where FS = the frequency of LRCLK. Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing

Table 42. SPI Interface Protocol—Master Switching and Timing Specifications Figure 34. SPI Master Timing

Table 43. SPI Interface Protocol—Slave Switching and Timing Specifications Figure 35. SPI Slave Timing

tions provided below are valid at the DPI_P14–1 pins. Table 45. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices 1 1 All values referred to VIHmin and VILmax levels. For more information, see Electrical Characteristics on page 19. Figure 37. Fast and Standard Mode Timing on the TWI Bus

Table 46. JTAG Test Access Port and Emulation 1 System Inputs = AD15–0, CLKCFG1–0, RESET , BOOTCFG1–0, DAI_Px, and FLAG3–0. 2 System Outputs = DAI_Px, AD15–0, AMI_RD, AMI_WR, FLAG3–0, CLKOUT, and EMU. Figure 38. IEEE 1149.1 JTAG Test Access Port

Rev. PrA | Page 52 of 60 | November 2008 ADSP-21462W/ADSP-21465W/ADSP-21467 Preliminary Technical Data Thermal Diode TBD Media Local Bus TBD

Table 48 lists the pin assignments of the SHARC processors. Table 48. 19 mm by 19 mm PBGA Pin Assignment (Alphabetically by Signal)

are available in a 19 mm by 19 mm PBGA lead-free package. Figure 46. 324-Ball Plastic Ball Grid Array [PBGA]

0.50 NOM

0.40 MIN

1.00 REF

tive products are RoHS compliant. Table 49. Automotive Products 1 Referenced temperature is ambient temperature. 1 Referenced temperature is ambient temperature. 2 Z =Part number subject to change.

3 Z =RoHS Compliant Part

Rev. PrA | Page 60 of 60 | November 2008 ADSP-21462W/ADSP-21465W/ADSP-21467 Preliminary Technical Data ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07900-0-11/08(PrA)