AD1984AJCPZ

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Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without no tice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.

FEATURES

Microsoft Vista Premium Logo for desktop 96+ dB audio outputs, 90 dB audio inputs WLP 3.0 and 4.0 Security feature prevents unauthorized recording 2 stereo headphone amplifiers Internal 32-bit arithmetic for greater accuracy Impedance and presence detection on all jacks Full analog mixer with DAC inputs 3 independent microphone bias pins Digital and analog PCBeep 3 general-purpose digital I/O (GPIO) pins

3.3 V analog supply voltage

1.7 V to 1.9 V or 3.3 V digital supply voltages 1.5 V or 3.3 V HD Audio link signaling voltage Advanced power management modes 48-lead, RoHS compliant LFCSP_VQ package 192 kHz DACs/ADCs 2 independent stereo DAC/ADC pairs Simultaneous record of 2 stereo channels Simultaneous playback of 2 stereo channels Independent 8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz sample rates 16-, 20-, and 24-bit resolution Selectable stereo mixer on outputs STEREO DIGITAL MICROPHONE INTERFACE Two 192 kHz digital microphone channels Supports 1 or 2 microphones per pin Selectable bit clock rates of 1.5 MHz, 2.0 MHz, and 3.0 MHz Mono and stereo array support 8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz sample rates 16-, 20-, and 24-bit resolution S/PDIF OUTPUT Supports 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz sample rates 16-, 20-, and 24-bit data; PCM and AC3 formats Digital PCM gain control AUXILIARY PINS Stereo CD/auxiliary I/O port with ground sense Stereo auxiliary/dock I/O port Mono out pin for internal speakers or telephony Figure 1. Function al Block Diagram

Rev. 0 | Page 2 of 20 | April 2008 AD1984A TABLE OF CONTENTS

REVISION HISTORY

4/08—Rev 0. Initial version

notebook PCs where performance is key. Inc., sales representative for more information. used when selecting ports for particular functions. Table 1. Typical Desktop Configuration Table 2. Typical Notebook Configuration Table 3. Typical Notebook Configuration with Dock

Rev. 0 | Page 4 of 20 | April 2008 AD1984A AD1984A SPECIFICATIONS TEST CONDITIONS PERFORMANCE GENERAL SPECIFICATIONS Parameter Test Condition Temperature Digital Supply Analog Supply MIC_BIAS_IN (via Low-Pass Filter) Sample Rate F S Input Signal (Frequency Sine Wave) Amplitude for THD + N Analog Output Pass Band 25°C 3.3 V 3.3 V 5.0 V 48 kHz 1008 Hz –3.0 dB Full Scale

20 Hz to 20 kHz

1 DAC/ADC tests are performed with AES-17 filter enabled. 10 kΩ Output Load: Line-Out Tests 32 Ω Output Load: Headphone Tests ADC 0 dB Gain Parameter Min Typ Max Unit Line-Out Drive (10 kΩ loads—DAC to Pin) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in ref to fS A-Weighted) Signal-to-Noise Ratio –86 dB dB dB Headphone Drive (32 Ω loads—DAC to Pin) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in ref to f S A-Weighted) Signal-to-Noise Ratio –80 dB dB dB Microphone/Line-In (Pin to ADC, Mic Boost = 0 dB) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in ref to f S A-Weighted) Signal-to-Noise Ratio –81 dB dB dB Parameter Min Typ Max Unit DIGITAL DECIMATION AND INTERPOLATION FILTERS—fS = 8 kHz to 192 kHz1 Pass Band 0 0.4 fS Hz Pass-Band Ripple ±0.005 dB Stop Band 0.6 f S Hz Stop-Band Rejection –100 dB Group Delay 20 1/f S Group Delay Variation over Pass Band 0 μs ANALOG-TO-DIGITAL CONVERTERS Resolution 24 Bits Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ±10 % Interchannel Gain Mismatch (Difference of Gain Errors) ±0.2 ±0.5 dB ADC Offset Error1 ±5m V ADC Crosstalk1 Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) –85 dB Line Inputs to Other –100 –80 dB

Rev. 0 | Page 5 of 20 | April 2008 DIGITAL-TO-ANALOG CONVERTERS Resolution 24 Bits Gain Error (Full-Scale Span Relative to Nominal Input Voltage)1 ±10 % Interchannel Gain Mismatch (Difference of Gain Errors) ±0.5 dB Total Audible Out-of-Band Energy (Measured from 0.6 × fS to 20 kHz)1 –85 dB DAC Crosstalk (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT)1 –95 dB DAC VOLUMES Step Size 1.5 dB Output Gain/Attenuation Range –58.5 0 dB Mute Attenuation of 0 dB Fundamental1 –80 dB ADC VOLUMES Step Size 1.5 dB PGA Gain/Attenuation Range –58.5 +22.5 dB ANALOG MIXER Signal-to-Noise Ratio Input to Output—Ports B, C, E, or F to Port D Output 95 dB Step Size: All Mixer Inputs –1.5 dB Input Gain/Attenuation Range: All Mixer Inputs –34.5 +12.0 dB ANALOG LINE LEVEL OUTPUTS Full-Scale Output Voltage 1.0 2.83 V rms V p-p Ports A, D, E, F , and Mono Out Output Impedance1 190 Ω External Load Impedance1 10 kΩ Output Capacitance1 15 pF External Load Capacitance 1000 pF ANALOG HP DRIVE OUTPUTS Full-Scale Output Voltage 1.0 2.83 V rms V p-p Ports A and D Output Impedance1 0.5 Ω External Load Impedance1 32 Ω Output Capacitance1 15 pF External Load Capacitance1 1000 pF ANALOG INPUTS Input Voltages—Ports B, C, E, or F Mic Boost = 0 dB 1 2.83 V rms V p-p Input Voltages—Microphone Boost Amplifier, Ports B, C, or E Mic Boost = 10 dB 0.316 0.894 V rms V p-p Mic Boost = 20 dB 0.1 0.283 V rms V p-p Mic Boost = 30 dB 0.032 0.089 V rms V p-p Input Impedance PCBeep Ports B, C, E (Mic Boost = 0 dB) Port F 150 kΩ kΩ kΩ Input Capacitance 1 57 .5 p F Parameter Min Typ Max Unit

Rev. 0 | Page 6 of 20 | April 2008 AD1984A MICROPHONE BIAS MIC_BIAS-B, MIC_BIAS-C MIC_BIAS_IN (Pin 33) = 5 V or 3.3 V V REF Setting = High-Z High-Z VREF Setting = 0 V 0 V dc VREF Setting = 50% 1.65 V dc MIC_BIAS_IN (Pin 33) = 5 V VREF Setting = 80% 3.7 V dc VREF Setting = 100% 3.9 V dc MIC_BIAS_IN (Pin 33) = 3.3 V VREF Setting = 80% 2.86 V dc VREF Setting = 100% 3.0 V dc MIC_BIAS-E (When Enabled as BIAS) V REF Setting = High-Z High-Z VREF Setting = 0 V 0 V dc VREF Setting = 50% 1.65 V dc VREF Setting = 80% 2.86 V dc VREF Setting = 100% 3.0 V dc Output Drive Current VREF Setting = 50%, 80%, or 100% 1.6 mA GPIO 0 Input Signal High (VIH)D VIO × 0.60 DVIO V Input Signal Low (VIL)0 DVIO × 0.24 V Output Signal High (VOH) I OUT = –500 μAD V IO × 0.72 DVIO V Output Signal Low (VOL)I OUT = +1500 μA0 D V IO × 0.10 V Input Leakage Current (Signal High) (IIH) 150 nA Input Leakage Current (Signal Low) (IIL)– 50 μA GPIO 1 and GPIO 2 Input Signal High (VIH)A VDD × 0.60 AV DD V Input Signal Low (VIL)0 AVDD × 0.24 V Output Signal High (VOH)I OUT = –500 μAA V DD × 0.72 AV DD V Output Signal Low (VOL)I OUT = +1500 μA0 A V DD × 0.10 V Input Leakage Current (Signal High) (IIH) 150 nA Input Leakage Current (Signal Low) (IIL)– 50 μA DM Clock Output Signal High (VOH)I OUT = –500 μAA V DD × 0.72 AV DD V Output Signal Low (VOL)I OUT = +1500 μA0 A V DD × 0.10 V DM_1/2 and DM_2 Input Signal High (VIH)A VDD × 0.60 AV DD V Input Signal Low (VIL)0 AVDD × 0.24 V Input Leakage Current (Signal High) (IIH) –150 nA Input Leakage Current (Signal Low) (IIL)– 50 nA S/PDIF Input Signal High (VIH)D VIO × 0.60 DVIO V Input Signal Low (VIL)0 DVIO × 0.24 V Output Signal High (VOH) I OUT = –500 μAD V IO × 0.72 DVIO V Output Signal Low (VOL)I OUT = +1500 μA0 D V IO × 0.10 V Input Leakage Current (Signal High) (IIH) 150 nA Input Leakage Current (Signal Low) (IIL)– 50 μA Parameter Min Typ Max Unit

Rev. 0 | Page 7 of 20 | April 2008 HD AUDIO LINK SPECIFICATION High definition audio signals comply with the High Definition Audio Specification. Please refer to these specifications at www.intel.com/standards/hdaudio. POWER-DOWN STATES POWER SUPPLY Analog (AVDD) 3.3 V ± 5% Power Supply Range Power Dissipation Supply Current 3.13 3.30 75.9 3.46 V mW mA Digital (DV DD) 3.3 V ± 10% Power Supply Range Power Dissipation Supply Current 2.97 3.30 141.9 3.63 V mW mA Digital (DV CORE) 1.7 through 1.9 V ± 10% Power Supply Range Power Dissipation Supply Current 1.615 1.70 1.995 V mW mA Digital I/O (DV IO) 3.3 V ± 10% Power Supply Range Power Dissipation Supply Current 2.97 3.30 3.3 3.63 V mW mA Digital I/O (DV IO) 1.5 V ± 5.5% Power Supply Range Power Dissipation Supply Current 1.418 1.50 0.08 0.05 1.583 V mW mA Power Supply Rejection (Reference to f S 100 mV p-p Signal @ 1 kHz)1 80 dB 1 Guaranteed but not tested. Parameter Min Typ Max Unit Parameter IDVDD Typ (1.7 V) ID VDD Typ (3.3 V) IA VDD Typ Unit Function Node in D0, All Nodes Active 36 43 23 mA Function Node in D3 15.75 17 1 mA Function Node in D31 1 Maximum power saving mode; Register 0x31FD, Bit 4. 7.5 7.5 1 mA Codec in RESET 333m A Individual Block Power Savings DAC Pair Powered Down Saves (Each) ADC Pair Powered Down Saves (Each) Mixer Power Control (and Associated Amps) Saves DM_CLK Powered Down Saves MIC_BIAS Powered Down Saves3 2 Test conditions: 30 pF load, 2.0 MHz frequency, 3.3 V AVDD. 3 Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all micr ophone bias circuits set to 100% or 50%, setting them to the high-Z state. The 0 V and high-Z states remain unaffected by the MIC_BIAS power state. 4.5 4.5 0.1 mA mA mA mA mA

Rev. 0 | Page 8 of 20 | April 2008 AD1984A ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed below may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ENVIRONMENTAL CONDITIONS Ambient Temperature Rating: TAMB = TCASE – (PD × θCA) TCASE = case temperature in °C PD = power dissipation in W θCA = thermal resistance (case-to-ambient) θJA = thermal resistance (junction-to-ambient) θJC = thermal resistance (junction-to-case) All measurements per EIA-JESD51 with 2S2P test board per EIA-JESD51-7. Parameter Rating Digital (DVDD) –0.30 V to +3.65 V Digital (DVCORE) –0.30 V to +2.10 V Digital I/O (DVIO) –0.30 V to +3.65 V Analog (AVDD) –0.30 V to +3.65 V Input Current (Except Supply Pins) ±10.0 mA Analog Input Voltage (Signal Pins) –0.30 V to AV DD +0.3 V Digital Input Voltage (Signal Pins) –0.30 V to DV IO +0.3 V Ambient Temperature (Operating) 0 °C to +70°C Storage Temperature –65 °C to +150°C ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Package θJA θJC θCA Unit LFCSP_VQ 47 15 32 °C/W

Figure 2. AD1984A 48-Lead Package and Pinout

Table 4. Pin Function Descriptions Link Bit Clock. 24.000 MHz serial data clock. Link Serial Data Input. AD1984A output stream clocked only on one edge of BIT_CLK. Link Reset. AD1984A master hardware reset. 1 Input (for Single-phase Microphones). Digital Microphone 2 Input (for Single-phase Microphones). Clock to Drive External Digital Microphones. and 2.86 V. Pin 31 shares functionality between MIC_BIAS_E (default) and GPIO_1. resistors should be used to ensure the proper circuit state when this pin is in high-Z. Jack Sense A-D Input/Sense B drive. Jack Sense E-F Input/Sense A drive. Monaural Input from System for Analog PCBeep. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. capacitor if not in use as CD_GND. MUST always be ac-coupled. Front Panel Stereo MIC/Line-In. Front Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone. Rear Panel Headphone/Line-Out. Rear Panel Headphone/Line-Out. Front Panel Headphone/Line-Out. Front Panel Headphone/Line-Out. headphone load, MIC = input supports microphones with MIC bias and boost amplifier.

Switchable Microphone Bias. For use with Port B (Pins 21, 22). Switchable Microphone Bias. For use with Port C (Pins 23, 24). Source Power for Microphone Bias Boost Circuitry. is capable of providing 3.9 V as a mic bias to all of the mic bias pins (except on Pin 31). 1.7 V to 1.9 V DVDD may be applied to Pin 1 to lower the digital power requirements. Pin 9 MUST be connected to Pin 1 in this case. DVSS 7 I Digital Supply Return (Ground). connected to Pin 1 in this case. AVDD 3.3 V 25, 38 I CAUTION: DO NOT APPLY 5 V TO THESE PINS! Analog Supply Voltage 3.3 V ONLY . conductive trace under, or close to, the AD1984A. Table 4. Pin Function Descriptions (Continued) headphone load, MIC = input supports microphones with MIC bias and boost amplifier.

Figure 5. The interface can generate a microphone clock at Table 5. Microphone Timing Parameters

1 DM_CLK Rise Time 5 ns

Figure 3. Uniplex Microphone Timing Figure 4. DM_2 Uniplex Microphone Timing

Figure 5. Multiplex Microphone Timing

Table 6. HD Audio Widgets 1 1 All node IDs (NIDs) are sequential in the codec. Any NIDs missing for this table are vendor defined.

Table 7. Root and Function Node Parameters 1 Subject to change with silicon stepping. Table 8. Subsystem ID

Table 9. Widget Parameters

Table 10. Connection List previous NID to the current NID. For additional info rmation, see chapter 7.1.2, “Node Addressing” in the High Definition Audio Specification.

Table 11. Default Configuration Bytes Table 11. Default Configuration Bytes (Continued) Node ID Name Value Conn Type Color JD OVRD Def Assn. Seq.

Figure 6. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

0.50 BSC

0.20 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.60 MAX

0.60 MAX PIN 1

0.25 MIN

Rev. 0 | Page 20 of 20 | April 2008 AD1984A ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07399-0-4/08(0)