AD1984 AD | Alldatasheet
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a High Definition Audio SoundMAX® Codec AD1984 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without no tice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
Two independent stereo DAC/ADC pairs Simultaneous record of two stereo channels Simultaneous playback of two stereo channels Independent 8, 11.025, 16, 22.05, 32, 44.1, 48, 88.2, 96, 176.4, and 192 kHz sample rates 16, 20, and 24-bit resolution Selectable stereo mixer on outputs 4-CHANNEL DIGITAL MICROPHONE INTERFACE Four 192 kHz digital microphone channels Supports multiple microphone types Two microphones per pin (four total) One microphone per pin (two total) Low pin count, uses 3 pins Stereo or quad array support 176.4, and 192 kHz sample rates 16, 20, and 24-bit resolution S/PDIF OUTPUT Supports 44.1, 48, 88.2, 96, 176.4, and 192 kHz sample rates 16, 20, and 24-bit data; PCM, and AC3 formats Digital PCM gain control DEDICATED AUXILLARY PINS Stereo CD/auxillary I/O port w/GND sense Stereo auxillary/dock I/O port Mono out pin for internal speakers or telephony ENHANCED FEATURES Two stereo headphone amplifiers Microsoft Vista premimum logo for notebook and desktop 96+ dB audio outputs, 90+ dB audio inputs Internal 32-bit arithmetic for greater accuracy Impedance and presence detection on all jacks Three independent microphone bias pins Digital and analog PCBeep Three general-purpose digital I/O (GPIO) pins
3.3 V analog and digital supply voltages
Advanced power management modes 48-lead, Pb-free LFCSP_VQ package Figure 1. Function al Block Diagram
tal microphone interface, Digital Beep and analog PCBeep. and notebook PCs where performance is key. package in both reels and trays. See Ordering Guide on Page 20. http://www.analog.com/soundMAX. supports microphones with MIC bias and boost amplifier. Table 1. Port Assignments
Rev. 0 | Page 4 of 20 | January 2007 AD1984 AD1984 SPECIFICATIONS TEST CONDITIONS PERFORMANCE GENERAL SPECIFICATIONS Parameter Test Condition Temperature Digital Supply Analog Supply MIC_BIAS_IN (via Low-Pass Filter) Sample Rate FS Input Signal (Frequency Sine Wave) Amplitude for THD + N Analog Output Pass Band 25°C 3.3 V 3.3 V 5.0 V 48 kHz 1008 Hz –3.0 dB Full Scale
20 Hz to 20 kHz
DAC 10 k Ω Output Load: Line Out tests 32 Ω Output Load: Headphone Tests ADC 0 dB Gain Parameter Min Typ Max Unit Line Out Drive (10 kΩ loads—DAC to Pin) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in ref to fS A-Weighted) Signal-to-Noise Ratio –86 dB dB dB Headphone Drive (32 Ω loads—DAC to Pin) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in ref to f S A-Weighted) Signal-to-Noise Ratio –80 dB dB dB Microphone/Line In (Pin to ADC, Mic Boost = 0 dB) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in ref to fS A-Weighted) Signal-to-Noise Ratio –81 dB dB dB Parameter Min Typ Max Unit DIGITAL DECIMATION AND INTERPOLATION FILTERS1 Pass Band – fS (kHz) = 8 ~ 192 0 0.4 f S Hz Pass-Band Ripple– fS (kHz) = 8 ~ 192 ±0.005 dB Stop Band – fS (kHz) = 8 ~ 192 0.6 f S Hz Stop-Band Rejection – fS (kHz) = 8 ~ 192 –100 dB Group Delay – fS (kHz) = 8 ~ 192 20 1/f S Group Delay Variation Over Pass Band 0 μs ANALOG-TO-DIGITAL CONVERTERS Resolution 24 Bits Gain Error (Full-Scale Span Relative to Nominal Input Voltage)2 ±10 % Interchannel Gain Mismatch (Difference of Gain Errors) ±0.2 ±0.5 dB ADC Offset Error1 ±5m V ADC Crosstalk1 Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) –85 dB Line_In to Other –100 –80 dB
Rev. 0 | Page 5 of 20 | January 2007 DIGITAL-TO-ANALOG CONVERTERS Resolution 24 Bits Gain Error (Full Scale Span Relative to Nominal Input Voltage)1 ±10 % Interchannel Gain Mismatch (Difference of Gain Errors) ±0.5 dB Total Audible Out-of-Band Energy (Measured from 0.6 × fS to 20 kHz)1 –85 dB DAC Crosstalk (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT)1 –95 dB DAC VOLUMES Step size (DAC-0, DAC-1) 1.5 dB Output Gain/Attenuation Range –58.5 0 dB Mute Attenuation of 0 dB Fundamental1 –80 dB ADC VOLUMES Step size (ADCSEL-0, ADCSEL-1) 1.5 dB PGA Gain/Attenuation Range –58.5 +22.5 dB ANALOG MIXER Signal-to-Noise Ratio Input to Output – Ports B, C, or F, to Port D Output 95 dB Step Size: All Mixer Inputs –1.5 dB Input Gain/Attenuation Range: All Mixer Inputs –34.5 +12.0 dB ANALOG LINE LEVEL OUTPUTS Full-Scale Output Voltage: Line out drive enabled 1.0 V rms 3 Ports A, D, E, F , and Mono Out 2.83 V p-p Output Impedance1 190 Ω External Load Impedance1 10 k Ω Output Capacitance1 15 pF External Load Capacitance 1000 pF ANALOG HP DRIVE OUTPUTS Full-Scale Output Voltage: Line Out Drive Enabled 1.0 V rms 3 Ports A and D (when HP Drive is Enabled) 2.83 V p-p Output Impedance1 0.5 Ω External Load Impedance1 32 Ω Output Capacitance1 15 pF External Load Capacitance1 1000 pF ANALOG INPUTS Input Voltages – Ports B, C, or E Mic Boost = 0 dB 1 2.83 V rms3 V p-p Input Voltages – Microphone Boost Amplifier, Ports B, C, or E Mic Boost = +10 dB 0.316 0.894 V rms3 V p-p Mic Boost = +20 dB 0.1 0.283 V rms3 V p-p Mic Boost = +30 dB 0.032 0.089 V rms3 V p-p Input Impedance PCBEEP Ports B, C, E (Mic Boost = 0 dB) Port F 150 kΩ kΩ kΩ Input Capacitance 1 57 . 5 p F Parameter Min Typ Max Unit
Rev. 0 | Page 6 of 20 | January 2007 AD1984 MICROPHONE BIAS MIC_BIAS-B, MIC_BIAS-C MIC_BIAS_IN (Pin 33) = +5 V or +3.3 V V REF Setting = Hi-Z Hi-Z V REF Setting = 0 V 0 V dc V REF Setting = 50% 1.65 V dc MIC_BIAS_IN (Pin 33) = +5 V V REF Setting = 80% 3.7 V dc V REF Setting = 100% 3.9 V dc MIC_BIAS_IN (Pin 33) = +3.3 V V REF Setting = 80% 2.86 V dc VREF Setting = 100% 3.0 V dc MIC_BIAS-E (When enabled as BIAS) V REF Setting = Hi-Z Hi-Z V dc VREF Setting = 0 V 0 V dc VREF Setting = 50% 1.65 V dc VREF Setting = 80% 2.86 V dc VREF Setting = 100% 3.0 V dc Output Drive Current V REF Setting = 50%, 80%, or 100% 1.6 mA GPIO 0 Input Signal High (VIH)D V IO × 0.60 DV IO V Input Signal Low (VIL)0 D V IO × 0.24 V Output Signal High (VOH) I OUT = –500 μAD V IO × 0.72 DV IO V Output Signal Low (VOL)I OUT = +1500 μA0 D V IO × 0.10 V Input Leakage Current (Signal High) (IIH) –150 nA Input Leakage Current (Signal Low) (IIL)– 5 0 μA GPIO 1 and 2 Input Signal High (VIH)A V DD × 0.60 AV DD V Input Signal Low (VIL)0 A V DD × 0.24 V Output Signal High (VOH)I OUT = –500 μAA V DD × 0.72 AV DD V Output Signal Low (VOL)I OUT = +1500 μA0 A V DD × 0.10 V Input Leakage Current (Signal High) (IIH) –150 nA Input Leakage Current (Signal Low) (IIL)– 5 0 μA DM Clock Output Signal High (VOH)I OUT = –500 μAA V DD × 0.72 AV DD V Output Signal Low (VOL)I OUT = +1500 μA0 A V DD × 0.10 V DM 1/2 and 3/4 Input Signal High (VIH)A V DD × 0.60 AV DD V Input Signal Low (VIL)0 A V DD × 0.24 V Input Leakage Current (Signal High) (IIH) –150 nA Input Leakage Current (Signal Low) (IIL)– 5 0 n A POWER SUPPLY Analog (AVDD) 3.3 V ±5% Power Supply Range Power Dissipation Supply Current 3.13 3.30 3.46 V mW mA Digital (DV DD) 3.3 V ±10% Power Supply Range Power Dissipation Supply Current 2.97 3.30 162 3.63 V mW mA Digital I/O (DV IO) 3.3 V ±10% Power Supply Range Power Dissipation Supply Current 2.97 3.30 3.96 1.2 3.63 V mW mA Power Supply Rejection (reference to f S 100 mV p-p Signal @ 1 kHz)1 80 dB 1 Guaranteed but not tested. 2 Measurements reflect main ADC. 3 RMS values assume sine wave input. Parameter Min Typ Max Unit
Rev. 0 | Page 7 of 20 | January 2007 HD–AUDIO LINK SPECIFICATION High-definition audio signals comply with the High-definition Audio specification. Please refer to these specifications at: http://www.intel.com/standards/hdaudio/ POWER DOWN STATES Parameter ID VDD Typ IA VDD Typ Unit Function node in D0, all nodes active 58 31 mA Function node in D31 1 Function node D3 state powers down all nodes except for the VREF, Mixer and MIC_BIAS nodes which have independent power controls. VREF should be kept active when background functions such as jack presence detection or analog pass-through are required. Mixer should be kept active when analog pass-through is required. MIC_BIAS can be disabled if microphones are not in use in the power-down state. 21 2 mA Codec in RESET 33m A Individual block power savings DAC pair powered down saves (each) ADC pair powered down saves (each) Mixer power control (and associated amps) saves DM_FLT pair powered down saves (each) DM_CLK powered down saves MIC_BIAS powered down saves3 2 Test conditions: 30 pF load, 2.0 MHz frequency, 3.3 V AVDD. 3 Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all micr ophone bias circuits set to 100% or 50%, setting them to the Hi-Z state. The 0 Ω and Hi-Z states remain unaffected by the MIC_BIAS power state. 0.5 mA mA mA mA mA mA
for extended periods may affect device reliability. ESD (electrostatic discharge) sensitive device. performance degradation or loss of functionality. Table 2. Thermal Resistance
Figure 2. AD1984 48-L ead Package and Pinout
Table 3. AD1984 Pin Descriptions Link Bit Clock. 24.000 MHz serial data clock . Link Serial Data Input. AD1984 output stream clocked only on one edge of BIT_CLK. Link Reset. AD1984 master hardware reset. 1 input (for single-phase microphones). 2 input (for single-phase microphones). Clock to drive external digital microphones. General Purpose I/O/Microphone Bias for Port E. Capable of Hi-Z, 1.65 V, and 2.86 V. resistors should be used to insure the proper circuit state when this pin is in Hi-Z. S/PDIF_OUT – Supports S/PDIF output. Jack Sense A-D Input/Sense B drive. Jack Sense E-F Input/Sense A drive. Monaural Input from system for Analog PCBeep. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. capacitor if not in use as CD_GND. MUST always be ac coupled. Front Panel Stereo MIC/Line-In. Front Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone. Rear Panel Headphone/Line-Out. Rear Panel Headphone/Line-Out. Front Panel Headphone/Line-Out. Front Panel Headphone/Line-Out. driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier.
Switchable Microphone Bias. For use with Port B (Pins 21, 22). Switchable Microphone Bias. For use with Port C (Pins 23, 24). DVSS 7 I Digital supply return (ground). internal digital core internal to the AD1984. Analog supply voltage 3.3 V ONLY. 33 I Source power for microphone bias boost circuitry. (typically 3.0 V @ AVDD = 3.3 V). trace under, or close to, the AD1984. Table 3. AD1984 Pin Descriptions (Continued) driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier.
to suit quality and power requirements. Table 4. Digital Microphone Timing Parameters Figure 3. Uniplex Digital Mi crophone, Mono Interface
Figure 8. Multiplex Microphone Timing
Table 5. HD Audio Widgets
00 ROOT x Root Device identification
01 FUNCTION x Function Designates this device as an audio CODEC
02 S/PDIF DAC 0 Audio Output S/PDIF digital stream output interface
03 DAC_0 0 Audio Output Stereo headphone channel digital/audio converters
04 DAC_1 0 Audio Output Stereo front channel digital/audio converters
05 Dig Mic Conv 1/2 1 Audio Input Digital microphone Channel 1, 2 converters
06 Dig Mic Conv 3/4 1 Audio Input Digital microphone Channel 3, 4 converters
07 Port A Mixer 2 Audio Mixer Mixes the of DAC_(0, 1) and mixer output amps to drive Port A
08 ADC_0 1 Audio Input Stereo record Channel 0 audio/digital converters
09 ADC_1 1 Audio Input Stereo record Channel 1 audio/digital converters
10 Digital Beep 7 Beep Generator Internal digital PCBeep signal
11 Port A (Headphone) 4 Pin Complex Headphone jack pins
12 Port D (Line Out) 4 Pin Complex Line out jack pins
13 Mono Out 4 Pin Complex Monaural output pin (internal speakers or telephony system)
14 Port B (Mic In) 4 Pin Complex Microphone in jack pins
15 Port C (Line In) 4 Pin Complex Line in jack pins
16 Port F (Aux In/Out) 4 Pin Complex Auxiliary I/O pins
17 Dig Mic 1/2 Pin 4 Pin Complex Digital microphone 1, 2 input pin
18 Dig Mic 3/4 Pin 4 Pin Complex Digital microphone 3, 4 input pin
19 Mixer Power Down 5 Power Widget Powers down the analog mixer and associated amps
20 Analog Mixer 2 Audio Mixer Mixes individually gainable analog inputs
21 Mixer Output Atten 3 Audio Selector Attenuates the mixer output to drive the port mixers
22 Port A Out Selector 3 Audio Selector Selects the Port A DAC_(0, 1)
23 Port E Out Selector 3 Audio Selector Selects the Port E DAC_(0, 1)
24 Port E Mixer 2 Audio Mixer Mixes the DAC_(0, 1) and mixer output amps to drive Port E
25 Port E Mic Boost 3 Audio Selector 0 dB, 10 dB, 20 dB, or 30 dB gain boost for Port E
26 BIAS Power Down F Vendor Defined Powers down th e internal MIC_BIAS_FILT and all MIC_BIAS pins
Table 6. Root and Function Node Parameters
00 ROOT Root 11D41984 00100400 00010001
01 FUNCTION Function 00020025 00000001 00010C0C 40000003
Table 7. SubSystem ID 1 or soft reset in order to preserve modifications by BIOS control.
01 FUNCTION BFD4 00 00
Table 8. Widget Parameters
Table 9. Connection List Table 8. Widget Para meters (Continued)
Table 10. Default Configuration Bytes
11 Port A 0321401F Jack External Left HP Out 1/8" Jack Green 0 1 F
12 Port D 90130110 Fixed Internal N/A Speaker ATAPI Unknown 1 1 0
13 Mono Out 901301F0 Fixed Internal N/A Speaker ATAPI Unknown 1 F 0
14 Port B 03A190F0 Jack External Left Mic In 1/8" Jack Pink 0 F 0
15 Port C 96A30120 Fixed Internal Bottom Mic In ATAPI Unknown 1 2 0
16 Port F 99330121 Fixed Internal Special 3 CD ATAPI Unknown 1 2 1
17 Dig Mic 1/2 Pin 95A601F0 Fixed Internal Top Mic In Other Digital Unknown 1 F 0
18 Dig Mic 3/4 Pin 95A601F0 Fixed Internal Top Mic In Other Digital Unknown 1 F 0
registered trademarks are the property of their respective owners. Dimensions are shown in millimeters. Figure 9. 48-Lead, Pb-Free, Frame Chip Scale Package [LFCSP_VQ]