AD1981BJSTZ-REEL

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AC ’97 SoundMAX® Codec AD1981B Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved. AC ’97 2.3 COMPATIBLE FEATURES S/PDIF output, 20-bit data format, supporting 48 kHz and 44.1 kHz sample rates Integrated stereo headphone amplifier Variable sample rate audio External audio power-down control >90 dB dynamic range Stereo full-duplex codec 20-bit PCM DAC 3 analog line-level stereo inputs for line-in, AUX, and CD Mono line-level phone input Dual MIC input with built-in programmable preamplifier High quality CD input with ground sense Mono output for speakerphone or internal speaker power management support 48-lead LQFP package, Pb-free available ENHANCED FEATURES Stereo MIC preamplifier support Built-in digital equalizer function for optimized speaker sound Full-duplex variable sample rates from 7040 Hz to 48 kHz with 1 Hz resolution Jack sense pins for automatic output switching Software-programmed V REFOUT output for biasing microphone and external power amplifier Split power supplies: 3.3 V digital and 5 V analog Multiple codec configuration options FUNCTIONAL BLOCK DIAGRAM AM MIC1 MIC2 PHONE_IN CD_L CD_GND CD_R AUX_L AUX_R LINE_IN_L MIC PREAMP MONO_OUT HP_OUT_L HP MZLINE_OUT_L MZLINE_OUT_R HP_OUT_R HP OUTPUT SELECTOR G = GAIN A = ATTENUATION M = MUTE Z = HIGH Z GA PCM FRONT DAC RATE M M PCM L/R ADC RATE RECORD SELECTOR G LINE_IN_R CODEC CORE EAPD PLL XTL_OUT XTL_IN SPDIF SPDIF TX ID0 ID1 RESETADC AND DAC SLOT LOGIC SYNC BIT_CLK SDATA_OUT SDATA_IN EQ CORE STORAGE JS0 JS1 EAPD AD1981B G G 2CMIC MIX AM A A AM M GA M GA M GA M GA M GA M GA M GA M GA M M GAM M EQ BYPASS EQ G G AC '97 INTERFACE M G M G MS ANALOG MIXING CONTROL LOGIC AC '97 CONTROL REGISTERS VREFOUT VREF BYPASS 16-BIT Σ-∆ ADC 16-BIT Σ-∆ ADC 16-BIT Σ-∆ ADC 16-BIT Σ-∆ ADC 20-BIT Σ-∆ DAC 20-BIT Σ-∆ DAC CD DIFF AMP 03091-001 VOLTAGE REFERENCE Figure 1.

Rev. C | Page 2 of 32 TABLE OF CONTENTS

REVISION HISTORY

1/05—Rev. B to Rev. C 6/03—Rev. A to Rev. B C 2/03—Rev. 0 to Rev. A C 10/02—Revision 0: Initial Version

Rev. C | Page 3 of 32 SPECIFICATIONS TEST CONDITIONS Standard test conditions, unless otherwise noted. Table 1. Parameter Test Condition Temperature 25°C Digital Supply (DVDD) 3.3 V Analog Supply (AVDD) 5.0 V Sample Rate (fS) 48 kHz Input Signal 1008 Hz Analog Output Pass Band 20 Hz to 20 kHz DAC Calibrated −3 dB Attenuation Relative to Full Scale 0 dB Input 10 kΩ Output Load (LINE_OUT) 32 Ω Output Load (HP_OUT) ADC Calibrated 0 dB Gain Input −3.0 dB Relative to Full Scale GENERAL SPECIFICATIONS Table 2. Parameter Min Typ Max Unit ANALOG INPUT Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, AUX, CD, PHONE_IN 1 V rms

2.83 V p-p

MIC_IN with 20 dB Gain 0.1 V rms

0.283 V p-p

MIC_IN with 0 dB Gain 1 V rms Input Impedance1 20 kΩ Input Capacitance1 5 7.5 pF MASTER VOLUME Step Size (0 dB to −46.5 dB): LINE_OUT_L, LINE_OUT_R 1.5 dB Output Attenuation Range1 46.5 dB Step Size (0 dB to −46.5 dB): MONO_OUT 1.5 dB Output Attenuation Range1 46.5 dB Step Size (0 dB to −46.5 dB): HP_OUT_R, HP_OUT_L 1.5 dB Output Attenuation Range Span1 46.5 dB Mute Attenuation of 0 dB Fundamental1 80 dB PROGRAMMABLE GAIN AMPLIFIER—ADC Step Size (0 dB to 22.5 dB) 1.5 dB PGA Gain Range 22.5 dB ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS Signal-to-Noise Ratio (SNR) CD to LINE_OUT 90 dB Other to LINE_OUT1 90 dB

Rev. C | Page 4 of 32 Parameter Min Typ Max Unit Step Size (+12 dB to −34.5 dB) (All Steps Tested): MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC 1.5 dB Input Gain/Attenuation Range: MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC 46.5 dB DIGITAL DECIMATION AND INTERPOLATION FILTERS1 Pass Band 0 0.4 × fS Hz Pass-Band Ripple ±0.09 dB Transition Band 0.4 × fS 0.6 × fS Hz Stop Band 0.6 × fS ∞ Hz Stop-Band Rejection −74 dB Group Delay 16/fS s Group Delay Variation over Pass Band 0 µs ANALOG-TO-DIGITAL CONVERTERS Resolution 16 Bits Total Harmonic Distortion (THD) −84 dB Dynamic Range (−60 dB Input THD + N Referenced to Full Scale, A-Weighted) 80 85 dB Signal-to-Intermodulation Distortion1 (CCIF Method) 85 dB ADC Crosstalk1 Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) −80 dB Line_In to Other −100 −80 dB Gain Error2 (Full-Scale Span Relative to Nominal Input Voltage) ±10 % Interchannel Gain Mismatch (Difference of Gain Errors) ± 0.5 dB ADC Offset Error1 ±5 mV DIGITAL-TO-ANALOG CONVERTERS Resolution 20 Bits Total Harmonic Distortion (THD) LINE_OUT −85 dB Total Harmonic Distortion (THD) HP_OUT −75 dB Dynamic Range (−60 dB Input THD + N Referenced to Full Scale, A-Weighted) 85 90 dB Signal-to-Intermodulation Distortion1 (CCIF Method) −100 dB Gain Error2 (Output FS Voltage Relative to Nominal Output FS Voltage) ±10 % Interchannel Gain Mismatch (Difference of Gain Errors) ±0.7 dB DAC Crosstalk1 (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) −80 dB Total Audible Out-of-Band Energy1 (Measured from 0.6 × fS to 20 kHz) −40 dB ANALOG OUTPUT Full-Scale Output Voltage; LINE_OUT and MONO_OUT 1 V rms Output Impedance1 800 Ω External Load Impedance1 10 kΩ Output Capacitance1 15 pF External Load Capacitance1 100 pF Full-Scale Output Voltage; HP_OUT (0 dB Gain) 1 V rms External Load Impedance1 32 Ω VREF 2.05 2.25 2.45 V VREFOUT (Programmable to 3.70 V Nominal) 2.25 V VREFOUT Current Drive 5 mA Mute Click (Muted Output Minus Unmuted Midscale DAC Output) ±5 mV STATIC DIGITAL SPECIFICATIONS High Level Input Voltage (VIH): Digital Inputs 0.65 × DVDD V Low Level Input Voltage (VIL) 0.35 × DVDD V

Rev. C | Page 5 of 32 Parameter Min Typ Max Unit High Level Output Voltage (VOH), IOH = 2 mA 0.9 × DVDD V Low Level Output Voltage (VOL), IOL = 2 mA 0.1 × DVDD V Input Leakage Current −10 +10 µA Output Leakage Current −10 +10 µA POWER SUPPLY Power Supply Range—Analog (AVDD) 4.5 5.5 V Power Supply Range—Digital (DVDD) 3.0 3.47 V Power Dissipation—5 V/3.3 V 400 mW Analog Supply Current—5 V (AVDD) 50 mA Digital Supply Current—3.3 V (DVDD) 46 mA Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1 (At Both Analog and Digital Supply Pins, Both ADCs and DACs) 40 dB CLOCK SPECIFICATIONS1 Input Clock Frequency 24.576 MHz Recommended Clock Duty Cycle 40 50 60 % 1 Guaranteed but not tested. 2 Measurements reflect main ADC. POWER-DOWN STATES Values presented with VREFOUT not loaded. Table 3. Parameter Set Bits DVDD Typ AVDD Typ Unit Fully Active No Bits Value 42 51 mA ADC PR0 36 45 mA DAC PR1 29 35 mA ADC + DAC PR1, PR0 12 28 mA Mixer PR2 42 24 mA ADC + Mixer PR2, PR0 36 18 mA DAC + Mixer PR2, PR1 29 9 mA ADC + DAC + Mixer PR2, PR1, PR0 12 1.5 mA Standby PR5, PR4, PR3, PR2, PR1, PR0 0 0 mA Headphone Standby PR6 42 44 mA TIMING PARAMETERS Guaranteed over operating temperature range. Table 4. Parameter Symbol Min Typ Max Unit RESET Active Low Pulse Width tRST_LOW 1.0 ms RESET Inactive to BIT_CLK Start-Up Delay tRST2CLK 162.8 ns SYNC Active High Pulse Width tSYNC_HIGH 1.3 ms SYNC Low Pulse Width tSYNC_LOW 19.5 µs SYNC Inactive to BIT_CLK Start-Up Delay tSYNC2CLK 162.8 ns BIT_CLK Frequency 12.288 MHz BIT_CLK Frequency Accuracy ±1 ppm BIT_CLK Period tCLK_PERIOD 81.4 ns BIT_CLK Output Jitter1, , 2 3 750 2000 ps BIT_CLK High Pulse Width tCLK_HIGH 32.56 42 48.84 ns

TA = 25°C, unless otherwise noted. Table 6. Thermal Resistance tion or loss of functionality.

Figure 9. 48-Lead LQFP Pin Configuration Table 7. Pin Function Descriptions 2 XTL_IN I Crystal Input (24.576 MHz) or External Clock Input. 5 SDATA_OUT I AC-Link Serial Data Output, AD1981B Data Input Stream. 8 SDATA_IN O AC-Link Serial Data Input, AD1981B Data Output Stream. 10 SYNC I AC-Link Frame Sync. 11 RESET I AC-Link Reset, AD1981B Master Hardware Reset. 46 ID1 I Chip Select Input 1 (Active Low). 17 JS0 I Jack Sense 0 Input. 16 JS1 I Jack Sense 1 Input. 47 EAPD O External Amp Power-Down Control. 13 PHONE_IN I Phone Input. Mono input from telephony subsystem speaker phone or handset. 14 AUX_L I Auxiliary Input Left Channel. 15 AUX_R I Auxiliary Input Right Channel. 18 CD_L I CD Audio Left Channel. 19 CD_GND_REF I CD Audio Analog Ground Reference for Differential CD Input. 20 CD_ R I CD Audio Right Channel.

21 MIC1 I Microphone 1 Input (Mono) or Left Channel when 2-Channel Mode Selected

Rev. C | Page 11 of 32 Pin No. Mnemonic I/O Description

22 MIC2 I Microphone 2 Input (Mono) or Right Channel w hen 2-Channel Mode Selected

(Stereo MIC). 23 LINE_IN_L I Line-In Left Channel. 24 LINE_IN_R I Line-In Right Channel. 35 LINE_OUT_L O Line-Out (Front) Left Channel. 36 LINE_OUT_R O Line-Out (Front) Right Channel. 37 MONO_OUT O Monaural Output to Telephony Subsystem Speaker Phone. 39 HP_OUT_L O Headphone Left-Channel Output. 41 HP_OUT_R O Headphone Right-Channel Output. FILTER/REFERENCE2 27 VREF O Voltage Reference Filter. 28 VREFOUT O Voltage Reference Output 5 mA Drive (Intended for MIC Bias and Power Amp Bias). 29 AFILT1 O Antialiasing Filter Capacitor—ADC Right Channel. 30 AFILT2 O Antialiasing Filter Capacitor—ADC Left Channel. 31 AFILT3 O Antialiasing Filter Capacitor—Mixer ADC Right Channel. 32 AFILT4 O Antialiasing Filter Capacitor— Mixer ADC Left Channel. POWER AND GROUND SIGNALS 1 DVDD1 I Digital VDD, 3.3 V. 4 DVSS1 I Digital GND. 7 DVSS2 I Digital GND. 9 DVDD2 I Digital VDD, 3.3 V. 25 AVDD1 I Analog VDD, 5.0 V. 26 AVSS1 I Analog GND. 38 AVDD2 I Analog VDD, 5.0 V. 40 AVSS2 I Analog GND. 43 AVDD3 I Analog VDD, 5.0 V. 44 AVSS3 I Analog GND. 34 AVDD4 I Analog VDD, 5.0 V. 33 AVSS4 I Analog GND. NO CONNECTS 12 NC No Connect. 42 NC No Connect. 1 These pins can also be used to select an external clock. See Table 44. 2 These signals are connected to resistors, capacitors, or specific voltages.

Rev. C | Page 12 of 32 INDEXED CONTROL REGISTERS Table 8. Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x00 Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0x0090 0x02 Master Volum e MM X X LMV4 LMV3 LMV2 LMV1 LMV0 RM1 X X RMV4 RMV3 RMV2 RMV1 RMV0 0x8000 0x04 Headphone Volum e HPM X X LHV4 LHV3 LHV2 LHV1 LHV0 RM1 X X RHV4 RHV3 RHV2 RHV1 RHV0 0x8000 0x06 Mono Volum e MVM X X X X X X X X X X MV4 MV3 MV2 MV1 MV0 0x8000 0x0C Phone Volum e PHM X X X X X X X X X X PHV4 PHV3 PHV2 PHV1 PHV0 0x8008 0x0E MIC Volume MCM X X X X X X X X M20 X MCV4 MCV3 MCV2 MCV1 MCV0 0x8008 0x10 Line-In Volum e LVM X X LLV4 LLV3 LLV2 LLV1 LLV0 RM1 X X RLV4 RLV3 RLV2 RLV1 RLV0 0x8808 0x12 CD Volume CVM X X LCV4 LCV3 LCV2 LCV1 LCV0 RM1 X X RCV4 RCV3 RCV2 RCV1 RCV0 0x8808 0x16 AUX Volume AM X X LAV4 LAV3 LAV2 LAV1 LAV0 RM1 X X RAV4 RAV3 RAV2 RAV1 RAV0 0x8808 0x18 PCM-Out Volum e OM X X LOV4 LOV3 LOV2 LOV1 LOV0 RM1 X X ROV4 ROV3 ROV2 ROV1 ROV0 0x8808 0x1A Record Sel ect X X X X X LS2 LS1 LS0 X X X X X RS2 RS1 RS0 0x0000 0x1C Record Gain IM X X X LIM3 LIM2 LIM1 LIM0 RM1 X X X RIM3 RIM2 RIM1 RIM0 0x8000 0x20 General- Purpose X X X X X X MIX MS LPBK X X X X X X X 0x0000 0x26 Power-Down Ctr l/Stat EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 0x000X 0x28 Ext’d Audio ID IDC1 IDC0 X X REVC1 REVC0 AMAP X X X DSA1 DSA0 X SPDIF X VRAS 0xX605 0x2A Ext’d Audio Stat/Ctr l VFORCE X X X X SPCV X X X X SPSA1 SPSA0 X SPDIF X VRA 0x0000 0x2C PCM Front DAC Rate SRF15 SRF14 SRF13 SRF12 SRF 11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 0xBB80 0x32 PCM L/R ADC Rate SRA15 SRA14 SRA13 SRA12 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 0xBB80 0x3A SPDIF Control V X SPSR1 SPSR0 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /AUD PRO 0x2000 0x60 EQ Ctrl EQM MAD LBEN X X X X X X SYM CHS BCA5 BCA4 BCA3 BCA2 BCA1 BCA0 0x8080 0x62 EQ Data CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0x0000 0x64 Mixer ADC, Volum e MXM X X X LMG3 LMG2 LMG1 LMG0 RM1 X X X RMG3 RMG2 RMG1 RMG0 0x8000 0x72 Jack Sense X X X JS MT2 JS MT JS MT JS1 EQB JS0 EQB JS1 TM R JS0 TM R JS1 MD JS0 MD JS1 ST JS0 ST JS1 INT JS0 INT 0x0000 0x74 Serial Config SLOT 16 REGM 2 REGM 1 REGM 0 X X X CHEN X X X INTS X SPAL SPDZ SPLNK 0x7001 0x76 Misc Control Bit DACZ X MSPLT LODIS DAM X FMXE X MAD PD 2CMIC X MAD ST VREFH VREFD MBG1 MBG0 0x0000 0x7C Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 0x4144 0x7E Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 0x5374 All registers not shown. Bits containing an X are assumed to be reserved. Odd register addresses are aliased to the next lower even address. Reserved registers should not be written. Zeros should be written to reserved bits. 1 For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect.

X is a wild card and has no effect on the value. Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 0x74, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement. SE[4:0] Stereo Enhancement. The AD1981B does not provide ha rdware 3D stereo enhancement (all bits are 0s). ID[9:0] Identify Capability. The ID decodes the capabilities o f AD1981B based on the functions listed in Table 9. Table 9. ID Bits all lower five bits read 1s whenever these bits are set to 1. Refer to Table 12 for examples. 1 For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. MM bit. Otherwise, this bit always reads 0 and has no effect when set to 1. h case this mute bit affects only the left channel.

all lower five bits read 1s whenever these bits are set to 1. Refer to Table 12 for examples. 1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. HPM bit. Otherwise, this bit always reads 0 and has no effect when set to 1. h case this mute bit affects only the left channel. Table 12. Volume Settings for Master and Headphone 1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. X is a wild card and has no effect on the value.

set to 1. Refer to Table 14 for examples. All registers are not shown, and bits containing an X are assumed to be reserved. MVM Mono Volume Mute When this bit is set to 1, the channel is muted. Table 14. Volume Settings for Mono

1 X XXXX X XXXX −∞ dB Gain, Muted

An X is a wild card and has no effect on the value. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 17 for examples. PHM Phone Mute When this bit is set to 1, the phone channel is muted. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 17 for examples.

All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 17 for examples. (0x76) allow changing the gain boost to 10 dB or 30 dB, if necessary. MCM MIC Mute When this bit is set to 1, the MIC channel is muted. Table 17. Volume Settings for Phone and MIC X is a wild card, and has no effect on the value. 1For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. dB to −34.5 dB. The default value is 0 dB, mute enabled. LM bit. Otherwise, this bit always reads 0 and has no effect when set to 1. dB to −34.5 dB. The default value is 0 dB, mute enabled. h case this mute bit affects only the left channel.

Rev. C | Page 17 of 32 CD VOLUME REGISTER Index 0x12 Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x12 CD Volume CVM X X LCV4 LCV3 LCV2 LCV1 LCV0 RM1 X X RCV4 RCV3 RCV2 RCV1 RCV0 0x8808 1 For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 22 for examples. Table 19. Bit Mnemonic Function RCV [4:0] Right CD Volume Allows setting the CD right-channel attenuator in 32 volume lev els. The LSB represents 1.5 dB, and the gain range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled. RM Right-Channel Mute Once enabled by the MSPLT bit in Register 0x76, this bit mutes t he right channel separately from the CVM bit. Otherwise, this bit always reads 0 and has no affect when set to 1. LCV [4:0] Left CD Volume Allows setting the CD left-channel attenuator in 32 volume lev els. The LSB represents 1.5 dB, and the gain range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled. CVM CD Volume Mute When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in whic h case this mute bit affects only the left channel. AUX VOLUME REGISTER Index 0x16 Reg No. Name D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x16 AUX Volume AM X X LAV4 LAV3 LAV2 LAV1 LAV0 RM1 X X RAV4 RAV3 RAV2 RAV1 RAV0 0x8808 1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to for examples. Table 22 Table 20. Bit Mnemonic Function RAV [4:0] Right AUX Volume Allows setting the AUX right-channel attenuator in 32 volume levels. The LSB r epresents 1.5 dB, and the gain range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled. RM Right-Channel Mute Once enabled by the MSPLT bit in Register 0x76, this bit mutes t he right channel separately from the AM bit. Otherwise, this bit always reads 0 and has no affect when set to 1. LAV [4:0] Left AUX Volume Allows setting the AUX left-channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range i s +12 dB to −34.5 dB. The default value is 0 dB, mute enabled. AM AUX Volume Mute When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in whic h case this mute bit affects only the left channel.

1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. the range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled. bit always reads 0 and has no effect when set to 1. dB to −34.5 dB. The default value is 0 dB, mute enabled. h case this mute bit affects only the left channel. Table 22. Volume Settings for Line-In, CD Volume, AUX, and PCM-Out

1 X XXXX X XXXX −∞ dB Gain,

0x0000, which corresponds to MIC In. Refer to Table 24 for examples. Table 24. Settings for Record Select Control

000 MIC 000 MIC

001 CD_L 001 CD_R

010 Muted 010 Muted

011 AUX_L 011 AUX_R

100 LINE_IN_L 100 LINE_IN_R

101 Stereo Mix (L) 101 Stereo Mix (R)

110 Mono Mix 110 Mono Mix

111 PHONE_IN 111 PHONE_IN

1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 24 for examples. Each LSB represents 1.5 dB, 0000 = 0 dB, and th e gain range is 0 dB to 22.5 dB. IM bit. Otherwise, this bit always reads 0 and has no affect when set to 1. Each LSB represents 1.5 dB, 0000 = 0 dB, and th e gain range is 0 dB to 22.5 dB. h case this mute bit affects only the left channel.

Table 26. Settings for Record Gain Register

1 XXXX XXXX −∞ dB Gain,

1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. X is a wild card and has no effect on the value. This register should be read before writing to generate a mask for only the bit(s) that need to be changed. l registers are not shown, and bits containing an X are assumed to be reserved. LPBK Loopback Control ADC/DAC Digital Loopback Mode. ck PCM Digital Data from ADC Output to DAC. MS MIC Select Selects mono MIC input. See the 2CMIC bit in Register 0x76 to enable ste reo microphone recording. MIX Mono Output Select Selects mono output au dio source. 0 = Mixer Mono Output (reset default).

Rev. C | Page 21 of 32 POWER-DOWN CONTROL/STATUS REGISTER Index 0x26 Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x26 Power-Down Ctrl/Stat EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 0x000X The ready bits are read-only; writing to REF, ANL, DAC, ADC has no effect. These bits indicate the status for the AD1981B subsections. If the bit is a 1, that subsection is ready. Ready is defined as the subsection able to perform in its nominal state. All registers are not shown, and bits containing an X are assumed to be reserved. Table 28. Bit Mnemonic Function ADC ADC Sections Ready to Transmit Data. DAC DAC Sections Ready to Accept Data. ANL Analog Amplifiers, Attenuators, and Mixers Rea dy. REF Voltage References, VREF and VREFOUT, Up to Nominal Level. PR [6:0] Codec Power- Dow n Modes The first three bits are to be used individually rather than in combination with each other. PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until the reference is p owered up. PR5 has no effect unless all ADCs, DACs, and the ac-link are powered down. The reference and the mixer can be either powered up or powered down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in the slave codec, if the master’s PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5. EAPD External Audio Power-Down Control Controls the state of the EAPD pin. EAPD = 0 sets the EAPD pin low, enabling an ext ernal power amplifier (reset default). EAPD = 1 sets the EAPD pin high, shutting the external power amplifier off. Table 29. Power-Down State Set Bits PR [6:0] ADCs and Input MUX Power-Down PR0 [000 0001] DACs Power-Down PR1 [000 0010] Analog Mixer Power-Down (VREF and VREFOUT On) PR1, PR2 [000 0101] Analog Mixer Power-Down (VREF and VREFOUT Off) PR0, PR1, PR3 [000 1011] AC-Link Interface Power-Down PR4 [001 0000] Internal Clocks Disabled PR0, PR1, PR4, PR5 [011 0011] ADC and DAC Power-Down PR0, PR1 [000 0011] VREF Standby Mode PR0, PR1, PR2, PR4, PR5 [011 0111] Total Power-Down PR0, PR1, PR2, P R3, PR4, PR5, PR6 [111 1111] Headphone Amp Power-In Standby PR6 [100 0000]

Rev. C | Page 22 of 32 EXTENDED AUDIO ID REGISTER Index 0x28 Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x28 Ext’d Audio ID IDC1 IDC0 X X REVC1 REVC0 AMAP X X X DSA1 DSA0 X SPDIF X VRAS 0xX605 The extended audio ID register identifies which extended a udio features are supported. A nonzero extended audio ID value indicates that one or more of the extended audio features are supported. All registers are not shown, and bits containing an X are assumed to be reserved. Table 30. Bit Mnemonic Function VRAS Variable Rate PCM Audio Support (Read-Only) This bit returns a 1 when Read To indicates that the variable rate PCM audio is supported. SPDIF SPDIF Support (Read-Only) This bit returns a 1 when Read To indicates that the SPDIF transmitter is suppor ted (IEC958). This bit is also used to validate that the SPDIF tr ansmitter output is enabled. The SPDIF bit can be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled; therefore, this bit returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter is actually enabled. DSA [1:0] DAC Slot Assignments (Read/ Write) Reset default = 00. 00 DACs 1, 2 = 3 and 4. 01 DACs 1, 2 = 7 and 8. 10 DACs 1, 2 = 6 and 9. 11 Reserved. AMAP Slot DAC Mappings Based on Codec ID (Re ad-Only) This bit returns a 1 when read to indicate that slot/DAC mappi ngs based on the codec ID are supported. REVC [1:0] AC ’97 Revision Compliance REVC [1:0] = 01 indicates that the codec is AC ’97 revision 2.2 compl iant (read-only). IDC [1:0] Indicates Codec Configuration (Read-Onl 00 = Primary. 01, 10, 11 = Secondary. EXTENDED AUDIO STATUS AND CONTROL REGISTER Index 0x2A Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x2A Ext’d Audio St at/Ctrl VFORCE X X X X SPCV X X X X SPSA1 SPSA0 X SPDIF X VRA 0x0000 All registers are not shown, and bits containing an X are assumed to be reserved. Th e extended audio status and control register is a read/write register that provides status and control of the extended audio features. Table 31. Bit Mnemonic Function VRA Variable Rate Audio (Read/ Write) VRA = 0 sets the fixed sample rate audio to 48 k Hz (reset default). VRA = 1 enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling). SPDIF SPDIF Transmitter Subsystem Enable/ Disable Bit (Read/Write) SPDIF = 1 enables the SPDIF transmitter. SPDIF = 0 disables the SPDIF tra nsmitter (default). This bit is also used to validate that the SPDIF tr ansmitter output is enabled. The SPDIF bit can be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and this bit returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter is enabled. SPSA [1:0] SPDIF Slot Assignment Bits (Read/ Write) These bits control the SPDIF slot assignment and respective defaults, depending on the codec ID configuration.

independent of the SPDIF enable bit status. subframe) to be controlled by the V bit (D15) in Register 0x3A (SPDIF control register). VFORCE = 0 and V = 0; the validity bit is managed by the codec error detection logic. VFORCE = 0 and V = 1; the validity bit is forced h igh, indicating the subframe data is invalid. VFORCE = 1 and V = 0; the validity bit is forced low, ind icating the subframe data is valid. VFORCE = 1 and V = 1; the validity bit is forced high, indicating the subframe data is inva lid. Table 32. AC ’97 2.2 AMAP-Compliant Default SPDIF Slot Assignments This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz. VRA, the sample rate is reset to 48 kHz. This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz. VRA, the sample rate is reset to 48 kHz.

Rev. C | Page 24 of 32 SPDIF CONTROL REGISTER Index 0x3A Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x3A SPDIF Control V X SPSR1 SPSR0 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY AUD PRO 0x2000 Register 0x3A is a read/write register that controls SPDIF f unctionality and manages bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should be written to only when the SPDIF transmitter is disabled (SPDIF bit in Register 0x2A is 0). This ensures that control and status information start up correctly at the beginning of SPDIF transmission. Table 35. Bit Mnemonic Function PRO Professional 1 = Professional use of channel status. 0 = Consumer. AUD Nonaudio 1 = Data is non-PCM format. 0 = Data is PCM format. COPY Copyright 1 = Copyright is asserted. 0 = Copyright is not asserted. PRE Pre-emphasis 1 = Filter pre-emphasis is 50 µs/15 µs. 0 = Pre-emphasis is none. CC [6:0] Category Code Programmed according to IEC standards, or as a ppropriate. L Generation Level Programmed according to IEC standards, or as a ppropriate. SPSR [1:0] SPDIF Transmit Sample Rate SPSR [1:0] = 00: Transmit sample rate is 44.1 kHz. SPSR [1:0] = 01: Reserved. SPSR [1:0] = 10: Transmit sample rate is 48 kHz (reset default). SPSR [1:0] = 11: Not supported. V Validity This bit affects the validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain connection during error or mute conditions. V = 1: Each SPDIF subframe (L + R) has Bit 28 set to 1. This tags both samples as invalid. V = 0: Each SPDIF subframe (L + R) has Bit 28 set to 0 for val id data and 1 for invalid data (error condition). When V = 0, asserting the VFORCE bit (D15) in Register 0x2A (Ext’d Au dio Stat/Ctrl) forces the validity flag low, marking both samples as valid. EQ CONTROL REGISTER Index 0x60 Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x60 EQ Ctrl EQM MAD LBEN X X X X X X SYM CHS BCA5 BCA4 BCA3 BCA2 BCA1 BCA0 0x8080 Register 0x60 is a read/write register that controls the equalizer functionality and data setup. This register contains the biquad and coefficient address pointer, which is used in conjunction with the EQ data register (0x78) to set up the equalizer coefficients. The reset default disables the equalizer function until the coefficients can be properly set up by the software and sets the symmetry bit to allow equal coefficients for left and right channels. All registers are not shown, and bits containing an X are assumed to be reserved. Table 36. Bit Mnemonic Function BCA [5:0] Biquad and Coefficient Addres s Pointer biquad 0 coef a0 BCA[5:0] = 011011 biquad 0 coef a1 BCA[5:0] = 011010 biquad 0 coef a2 BCA[5:0] = 011001 biquad 0 coef b1 BCA[5:0] = 011101 biquad 0 coef b2 BCA[5:0] = 011100 biquad 1 coef a0 BCA[5:0] = 100000 biquad 1 coef a1 BCA[5:0] = 011111

Rev. C | Page 25 of 32 Bit Mnemonic Function biquad 1 coef a2 BCA[5:0] = 011110 biquad 1 coef b1 BCA[5:0] = 100010 biquad 1 coef b2 BCA[5:0] = 100001 biquad 2 coef a0 BCA[5:0] = 100101 biquad 2 coef a1 BCA[5:0] = 100100 biquad 2 coef a2 BCA[5:0] = 100011 biquad 2 coef b1 BCA[5:0] = 100111 biquad 2 coef b2 BCA[5:0] = 100110 biquad 3 coef a0 BCA[5:0] = 101010 biquad 3 coef a1 BCA[5:0] = 101001 biquad 3 coef a2 BCA[5:0] = 101000 biquad 3 coef b1 BCA[5:0] = 101100 biquad 3 coef b2 BCA[5:0] = 101011 biquad 4 coef a0 BCA[5:0] = 101111 biquad 4 coef a1 BCA[5:0] = 101110 biquad 4 coef a2 BCA[5:0] = 101101 biquad 4 coef b1 BCA[5:0] = 110001 biquad 4 coef b2 BCA[5:0] = 110000 biquad 5 coef a0 BCA[5:0] = 110100 biquad 5 coef a1 BCA[5:0] = 110011 biquad 5 coef a2 BCA[5:0] = 110010 biquad 5 coef b1 BCA[5:0] = 110110 biquad 5 coef b2 BCA[5:0] = 110101 biquad 6 coef a0 BCA[5:0] = 111001 biquad 6 coef a1 BCA[5:0] = 111000 biquad 6 coef a2 BCA[5:0] = 110111 biquad 6 coef b1 BCA[5:0] = 111011 biquad 6 coef b2 BCA[5:0] = 111010 CHS Channel Select CHS = 0 selects the left-channel coefficient’s data block. CHS = 1 selects the right-channe l coefficient’s data block. SYM Symmetry When set to 1, this bit indicates that the left and right-channel coefficients are equal. This shortens the coefficients’ setup sequence, because only the left-channel coefficients need to be addressed and set up. The right-channel coefficients are fetched from the left-channel memory. MAD LBEN Mixer ADC Loopback Enable Enables mixer ADC data to be summed into the PCM stream. 0 = No loopback allowed (default). 1 = Enable l oopback. EQM Equalizer Mute When set to 1, this bit disables t he equalizer function (allows all data to pass through). The reset default sets this bit to 1, disabling the equalizer function until the biquad coefficients can be properly set.

bits in the EQ Cntrl Register (0x60). Data is written to memory only if the EQM bit (Register 0x60, Bit 15) is asserted. 1For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 39 for examples. least significant bit represents 1.5 dB. bit. Otherwise, this bit always reads 0 and has no affect when set to 1. least significant bit represents 1.5 dB. Table 39. Settings for Mixer ADC, Input Gain 1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the RM bit has no effect. X is a wild card and has no effect on the value.

Rev. C | Page 27 of 32 JACK SENSE/AUDIO INTERRUPT/STATUS REGISTER Index 0x72 Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x72 Jack Sen se X X X JS MT2 JS MT1 JS MT0 JS1 EQB JS0 EQB JS1 TMR JS0 TMR JS1 MD JS0 MD JS1 ST JS0 ST JS1 INT JS0 INT 0x0000 All register bits are read/write except f or JS0ST and JS1ST, which are read-only. All registers are not shown, and bits containing an X are assumed to be reserved. Table 40. Bit Mnemonic Function JS0INT JS0 Interrupt This bit indicates that Pin JS0 has generated an interrupt. This bit remains set until the software service s the JS0 interrupt, that is, JS0 ISR should clear this bit by writing a 0 to it. The interrupt to the system is an OR combination of this bit and JS1INT. The actual interrupt implementation is selected by the INT S bit (Register 0x76). It is also possible to generate a software system interrupt by writing a 1 to this bit. JS1INT Js1 Interrupt This bit indicates that Pin JS1 has generated an interrupt. This bit remains set until the software service s the JS1 interrupt, that is, JS1 ISR should clear this bit by writing a 0 to it. See the JS0INT description for details. JS0ST JS0 State This bit always reports the logic state of the JS0 pin. JS1ST JS1 State This bit always reports the logic state of the JS1 pin. JS0MD JS0 Mode This bit selects the operatio n mode for the JS0 pin. 0 = Jack sense mode (default). 1 = Interrupt mode. JS1MD JS1 Mode This bit selects the operatio n mode for the JS1 pin. 0 = Jack sense mode (default). 1 = Interrupt mode. JS0TMR JS0 Timer Enable If this bit is set to 1, JS0 must be high for >278 ms to be recognized. JS1TMR JS1 Timer Enable If this bit is set to 1, JS1 must be high for >278 ms to be recognized. JS0EQB JS0 EQ Bypass Enable This bit enables JS0 to control the EQ bypass. When this bit is set to 1, JS0 = 1 causes the EQ to be bypassed. JS1EQB JS1 EQ Bypass Enable This bit enables JS1 to control the EQ bypass. When this bit is set to 1, JS1 = 1 causes the EQ to be bypassed. JSMT [2:0] JS Mute Enable Selector These three bits select and enable the jack sense muting action (see Table 41).

Table 41. Jack Sense Mute Select—JSMT [2:0] 0 OUT (0) OUT (0) 0 0 0 ACTIVE ACTIVE ACTIVE JS0 and JS1 ignored.

1 OUT (0) IN (1) 0 0 0 ACTIVE ACTIVE ACTIVE

2 IN (1) OUT (0) 0 0 0 ACTIVE ACTIVE ACTIVE

3 IN (1) IN (1) 0 0 0 ACTIVE ACTIVE ACTIVE

4 OUT (0) OUT (0) 0 0 1 FMUTE FMUTE ACTIVE JS0 no mute action;

5 OUT (0) IN (1) 0 0 1 FMUTE ACTIVE ACTIVE

6 IN (1) OUT (0) 0 0 1 ACTIVE FMUTE ACTIVE

7 IN (1) IN (1) 0 0 1 ACTIVE FMUTE ACTIVE

8 OUT (0) OUT (0) 0 1 0 FMUTE FMUTE ACTIVE JS0 no mute action;

9 OUT (0) IN (1) 0 1 0 FMUTE ACTIVE ACTIVE

10 IN (1) OUT (0) 0 1 0 ACTIVE FMUTE FMUTE

11 IN (1) IN (1) 0 1 0 ACTIVE FMUTE FMUTE

16 OUT (0) OUT (0) 1 0 0 FMUTE FMUTE ACTIVE JS0 mutes Mono;

17 OUT (0) IN (1) 1 0 0 FMUTE ACTIVE FMUTE

18 IN (1) OUT (0) 1 0 0 ACTIVE FMUTE ACTIVE

19 IN (1) IN (1) 1 0 0 ACTIVE ACTIVE FMUTE

20 OUT (0) OUT (0) 1 0 1 FMUTE FMUTE ACTIVE JS0 mutes Mono;

21 OUT (0) IN (1) 1 0 1 FMUTE ACTIVE FMUTE

22 IN (1) OUT (0) 1 0 1 ACTIVE FMUTE ACTIVE

23 IN (1) IN (1) 1 0 1 ACTIVE FMUTE FMUTE

24 OUT (0) OUT (0) 1 1 0 FMUTE FMUTE ACTIVE JS0 mutes Mono;

25 OUT (0) IN (1) 1 1 0 FMUTE ACTIVE FMUTE

26 IN (1) OUT (0) 1 1 0 ACTIVE FMUTE FMUTE

27 IN (1) IN (1) 1 1 0 ACTIVE FMUTE FMUTE

FMUTE = Output is forced to mute independent of the respective volume register setting. ACTIVE = Output is not muted, and its status is dependent on the respective volume register setting. OUT = Nothing plugged into the jack and, therefore, the JS status is low (via the load resistor pull-down). IN = Jack has plug inserted and, therefore, the JS status is high (via the codec JS internal pull-up).

Rev. C | Page 29 of 32 SERIAL CONFIGURATION REGISTER Index 0x74 Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x74 Serial Con fig SLOT16 REGM2 REGM1 REGM0 X X X CHEN X X X INTS X SPAL SPDZ SPLNK 0x7001 This register is not reset when the reset register (Register 0x00) is written. Al l registers are not shown, and bits containing an X are assumed to be reserved. Table 42. Bit Mnemonic Function SPLNK SPDIF Link This bit enables the SPDIF to link with the DAC for data requests. 0 = SPDIF and DAC are not linked. 1 = SPDIF and DAC are linked and receive the sa me data requests (reset default). SPDZ SPDIF DACZ 0 = Repeat last sample out of the SPDIF stream if FIFO underrun s (reset default). 1 = Forces midscale sample out the SPDIF stream if FIFO underr uns. SPAL SPDIF ADC Loop- Around 0 = SPDIF transmitter is connected to the ac-link stream (reset default). 1 = SPDIF transmitter is connected to the digital ADC stream, not the ac-link. INTS Interrupt Mode Select This bit selects t he JS interrupt implementation path. 0 = Bit 0 Slot 12 (modem interrupt). 1 = Slot 6 valid bit (MIC ADC interrupt). CHEN Chain Enable This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45). 0 = Disable chaining (reset default). 1 = Enable chaining into ID0 pin. REGM0 Master Codec Register Mas k REGM1 Slave 1 Codec Register Mas k REGM2 Slave 2 Codec Register Mas k SLOT16 Enable 16-Bit Slot Mode Slot 16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a preferred mode for DSP serial port interfacing. MISCELLANEOUS CONTROL BIT REGISTER Index 0x76 Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x76 Misc Control Bit DACZ X MSPLT LODIS DAM X FMXE X MADPD 2CMIC X MADST VREFH VREFD MBG1 MBG0 0x0000 All registers are not shown, and bits containing an X are assumed to be reserved. Table 43. Bit Mnemonic Function MBG [1:0] MIC Boost Gain Change Register These two bits allow changing the MIC preamp gain from the nominal 20 dB ga in. This gain setting takes effect only while Bit D6 (M20) on the MIC volume register (0x0E) is set to 1; otherwise, the MIC boost block has a gain of 0 dB. 00 = 20 dB gain (reset default). 01 = 10 dB gain. 10 = 30 dB gain. 11 = Reserved.

Rev. C | Page 30 of 32 Bit Mnemonic Function VREFD VREFOUT Disable This bit disables VREFOUT, placing it into high Z out mode. This bit overrides the VREFH bit selection. 0 = VREFOUT pin is driven by the internal reference (reset default). 1 = VREFOUT pin is placed into high Z out mode. VREFH VREFOUT High This bit changes VREFOUT from 2.25 V to 3.70 V for MIC bias applications. 0 = VREFOUT pin is set to 2.25 V output (reset default). 1 = VREFOUT pin is set to 3.70 V output. MADST Mixer ADC Status Bit This bit indicates status of the mixer digitizing ADC (left and righ t channels). 0 = Mixer ADC not ready. 1 = Mixer ADC ready. 2CMIC 2-Channel MIC Select This bit enables simultaneous recording from MIC1 and MIC2 in puts for applications that use a stereo microphone array. This register works in conjunction with the MS bit in Register 0x20. 0 = MIC1 or MIC2 (determined by the MS bit) is r outed to the record selector’s left and right MIC channels, as well as to the mixer (reset default). 1 = MIC1 is routed to the record selector’s left MIC channel and MIC2 is routed to the record selector’s right MIC channel. In this mode, the MS bit should be set low, and MIC1 can still be enabled into the mixer. MADPD Mixer ADC Power-Down This bit controls power-down for mixer digitizing ADC. 0 = Mixer ADC is powered on (default). 1 = Mixer ADC is powered down. FMXE Front DAC into Mixer Enable This bit controls the front (main) DAC to mix er mute switches. 0 = Front DAC outputs are allowed to sum into the mixer (reset default). 1 = Front DAC outputs are muted into the mixer (blocked). DAM Digital Audio Mode PCM DAC outputs bypass the analog mix er and are sent directly to the codec output. LODIS LINE_OUT Disable This bit disables the LINE_OUT pins (L/R), placing them into high Z mode so that the assigned output audio jack can be shared for the input function (or other function). 0 = LINE_OUT pins have normal audio drive capability (reset default). 1 = LINE_OUT pins are placed into high Z mode. MSPLT Mute Split This bit allows separate mute control bits for the master, headphone, LINE_IN, CD, AUX, and PCM volume control registers as well as for the record gain register. 0 = Both left- and right-channel mutes are controlled by Bit 15 in the respective registers (reset default). 1 = Bit 15 affects only the left-channel mute, and Bit 7 affects o nly the right-channel mute. DACZ DAC Zero-Fill This bit determines DAC d ata fill under starved conditions. 0 = DAC data is repeated when DACs are starve d for data (reset default). 1 = DAC is zero-filled when DACs are starved for data.

S[7:0] This register is ASCII encoded to A. F[7:0] This register is ASCII encoded to D. T[7:0] This register is ASCII encoded to S. REV[7:0] Vendor-specific revision number: The AD1981B assigns 0x74 to this field. Table 44. Codec ID and External Clock Selection 1 1 (00) Primary 24.576 MHz Local crystal or external into XTL_IN. 1 0 (01) Secondary 12.288 MHz External into BIT_CLK. 0 1 (00) Primary 48.000 MHz External into XTL_IN. 0 0 (00) Primary 14.31818 MHz External into XTL_IN. Internally, the ID pins have weak pull-ups and are inverted.

9.00 BSC

0.08 MAX

Figure 10. 48-Lead Low Profile Quad Flat Package [LQFP] lead solder pastes at reflow temperatures of 220°C to 235°C. 2 DVDD tolerance: ±5% maximum. registered trademarks are the prop erty of their respective owners.

Summary

AC 97 SoundMAX Codec REV. C

Description