AD1974YSTZ-RL

AD1974 AD | Alldatasheet

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4 ADC with PLL,

192 kHz, 24-Bit Codec AD1974 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.

FEATURES

Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates Differential ADC input Log volume control with autoramp function SPI®-controllable for flexibility Software-controllable clickless mute Software power-down Right justified, left justified, I2S, and TDM modes Master and slave modes up to 16-channel input/output Available in a 48-lead LQFP

APPLICATIONS

Digital audio effects processors GENERAL DESCRIPTION The AD1974 is a high performance, single-chip codec that pro- vides four analog-to-digital converters (ADCs) with differential inputs using the Analog Devices, Inc. patented multibit sigma- delta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1974 operates from 3.3 V digital and analog supplies. The AD1974 is available in a single-ended output 48-lead LQFP . The AD1974 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board phase-locked loop (PLL) to derive the master clock from the LR clock or from an external crystal, the AD1974 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The ADCs are designed using the latest continuous time archi- tectures from Analog Devices to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions. FUNCTIONAL BLOCK DIAGRAM QUAD DEC FILTER 48kHz/ 96kHz/192kHz SERIAL DATA PORT DIGITAL AUDIO INPUT/OUTPUT PRECISION VOLTAGE REFERENCE 12.48MHz TIMING MANAGEMENT AND CONTROL (CLOCK AND PLL) CONTROL PORT SPI CONTROL DATA INPUT/OUTPUT AD1974 ADC ADC ADC ADC ANALOG AUDIO INPUTS SDATA OUT CLOCKS 06614-001 Figure 1.

Rev. 0 | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

4/07—Revision 0: Initial Version

Rev. 0 | Page 3 of 24 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply Voltages (AVDD, DVDD) 3.3 V Temperature R ange1 As specified in Table 1 and Table 2 Master Clock 12.288 MHz (48 kHz fS, 256 × fS mode) Input Sample Rate 48 kHz Measurement Bandwidth 20 Hz to 20 kHz Word Width 24 bits Load Capacitance (Digital Output) 20 pF Load Current (Digital Output) ±1 mA or 1.5 kΩ to ½ DVDD supply Input Voltage High 2.0 V Input Voltage Low 0.8 V 1 Functionally guaranteed at −40°C to +125°C case temperature. ANALOG PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). Table 1. Parameter Conditions Min Typ Max Unit ANALOG-TO-DIGITAL CONVERTERS ADC Resolution All ADCs 24 Bits Full-Scale Input Voltage (Differential) 1.9 V rms Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 98 102 dB With A-Weighted Filter (RMS) 100 105 dB Total Harmonic Distortion + Noise (THD + N) −1 dBFS −96 −87 dB Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV Gain Drift 100 ppm/°C Interchannel Isolation −110 dB CMRR 100 mV rms, 1 kHz 55 dB 100 mV rms, 20 kHz 55 dB Input Resistance 14 kΩ Input Capacitance 10 pF Input Common-Mode Bias Voltage 1.5 V REFERENCE Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V

Rev. 0 | Page 4 of 24 Specifications measured at 130°C (case). Table 2. Parameter Conditions Min Typ Max Unit ANALOG-TO-DIGITAL CONVERTERS ADC Resolution All ADCs 24 Bits Full-Scale Input Voltage (Differential) 1.9 V rms Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 95 102 dB With A-Weighted Filter (RMS) 97 105 dB Total Harmonic Distortion + Noise (THD + N) −1 dBFS −96 −87 dB Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV REFERENCE Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V CRYSTAL OSCILLATOR SPECIFICATIONS Table 3. Parameter Min Typ Max Unit Transconductance 3.5 Mmhos DIGITAL INPUT/OUTPUT SPECIFICATIONS Table 4. Parameter Conditions/Comments Min Typ Max Unit Input Voltage High (VIH) 2.0 V Input Voltage High (VIH) MCLKI pin 2.2 V Input Voltage Low (VIL) 0.8 V Input Leakage IIH @ VIH = 2.4 V 10 μA I IL @ VIL = 0.8 V 10 μA High Level Output Voltage (VOH) IOH = 1 mA DVDD − 0.60 V Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V Input Capacitance 5 pF

Rev. 0 | Page 5 of 24 POWER SUPPLY SPECIFICATIONS Table 5. Parameter Conditions/Comments Min Typ Max Unit SUPPLIES Voltage DVDD 3.0 3.3 3.6 V AVDD 3.0 3.3 3.6 V Digital Current MCLK = 256 fS Normal Operation fS = 48 kHz 56 mA fS = 96 kHz 65 mA fS = 192 kHz 95 mA Power-Down fS = 48 kHz to 192 kHz 2.0 mA Analog Current Normal Operation 74 mA Power-Down 23 mA DISSIPATION Operation MCLK = 256 fS, 48 kHz All Supplies 429 mW Digital Supply 185 mW Analog Supply 244 mW Power-Down, All Supplies 83 mW POWER SUPPLY REJECTION RATIO Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB 20 kHz, 200 mV p-p 50 dB DIGITAL FILTERS Table 6. Parameter Mode Factor Min Typ Max Unit ADC DECIMATION FILTER All modes @ 48 kHz Pass Band 0.4375 fS 21 kHz Pass-Band Ripple ±0.015 dB Transition Band 0.5 fS 24 kHz Stop Band 0.5625 fS 27 kHz Stop-Band Attenuation 79 dB Group Delay 22.9844 fS 479 μs TIMING SPECIFICATIONS Table 7. Parameter Condition Comments Min Max Unit INPUT MASTER CLOCK (MCLK) AND RESET tMH MCLK duty cycle ADC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, 768 fS 40 60 % tMH ADC clock source = direct MCLK @ 512 fS (bypass on-chip PLL) 40 60 % fMCLK MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz fMCLK Direct 512 fS mode 27.6 MHz tPDR Low 15 ns tPDRR Recovery Reset to active output 4096 tMCLK

Rev. 0 | Page 6 of 24 Parameter Condition Comments Min Max Unit PLL Lock Time MCLK and LRCLK input 10 ms 256 fS VCO Clock 40 60 % Output Duty Cycle MCLK_O Pin SPI PORT See Figure 5 tCCH CCLK high 35 ns tCCL CCLK low 35 ns fCCLK CCLK frequency fCCLK = 1/tCCP; only tCCP shown in Figure 5 10 MHz tCDS CDATA setup To CCLK rising 10 ns tCDH CDATA hold From CCLK rising 10 ns tCLS Setup To CCLK rising 10 ns tCLH Hold From CCLK falling 10 ns tCLHIGH High Not shown in Figure 5 10 ns tCOE COUT enable From CCLK falling 30 ns tCOD COUT delay From CCLK falling 30 ns tCOH COUT hold From CCLK falling, not shown in Figure 5 30 ns tCOTS COUT tristate From CCLK falling 30 ns ADC SERIAL PORT See Figure 13 tABH ABCLK high Slave mode 10 ns tABL ABCLK low Slave mode 10 ns tALS ALRCLK setup To ABCLK rising, slave mode 10 ns tALH ALRCLK hold From ABCLK rising, slave mode 5 ns tALS ALRCLK skew From ABCLK falling, master mode −8 +8 ns tABDD ASDATA delay From ABCLK falling 18 ns AUXILIARY INTERFACE See Figure 12 tXDS AAUXDATA setup To AUXBCLK rising 10 ns tXDH AAUXDATA hold From AUXBCLK rising 5 ns tXBH AUXBCLK high 10 ns tXBL AUXBCLK low 10 ns tXLS AUXLRCLK setup To AUXBCLK rising 10 ns tXLH AUXLRCLK hold From AUXBCLK rising 5 ns

Rev. 0 | Page 7 of 24 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Rating Analog (AVDD) −0.3 V to +3.6 V Digital (DVDD) −0.3 V to +3.6 V Input Current (Except Supply Pins) ±20 mA Analog Input Voltage (Signal Pins) –0.3 V to AVDD + 0.3 V Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V Operating Temperature Range (Case) −40°C to +125°C Storage Temperature Range −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA represents thermal resistance, junction-to-ambient; θJC represents the thermal resistance, junction-to-case. All characteristics are for a 4-layer board. Table 9. Package Type θJA θJC Unit 48-Lead LQFP 50.1 17 °C/W ESD CAUTION

Figure 2. AD1974 Single-Ended Output, 48-Lead LQFP Pin Configuration Table 10. Pin Function Description 2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input. 3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output. 5, 33, 37, 48 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 10 I PD/RST Power-Down/Reset (Active Low). 12, 25 I DGND Digital Ground. 13 I DVDD Digital Power Supply. Connect to digital 3.3 V supply. 14 I/O AUXDATA2 Auxiliary Data Input 2 (From External ADC 2). 15 I/O AUXDATA1 Auxiliary Data Input 1 (From External ADC 1). 17 I/O AUXBCLK Auxiliary Bit Clock. 18 I/O AUXLRCLK Auxiliary Left-Right Framing Clock. 19 I/O ASDATA2 ADC Serial Data Output 2 (ADC 2 Left and ADC 2 Right)/ADC TDM Data Input. 20 O ASDATA1 ADC Serial Data Output 1 (ADC 1 Left and ADC 1 Right)/ADC TDM Data Output. 21 I/O ABCLK Serial Bit Clock for ADCs. 22 I/O ALRCLK Left-Right Framing Clock for ADCs. 23 I CIN Control Data Input (SPI). 24 I/O COUT Control Data Output (SPI). 26 I CCLK Control Clock Input (SPI). 27 I CLATCH Latch Input for Control Data (SPI). 35 O FILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND. 38 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND. 39 I ADC1LP ADC1 Left Positive Input. 40 I ADC1LN ADC1 Left Negative Input. 41 I ADC1RP ADC1 Right Positive Input. 42 I ADC1RN ADC1 Right Negative Input. 43 I ADC2LP ADC2 Left Positive Input.

Rev. 0 | Page 9 of 24 Pin No. Type 1 Mnemonic Description 44 I ADC2LN ADC2 Left Negative Input. 45 I ADC2RP ADC2 Right Positive Input. 46 I ADC2RN ADC2 Right Negative Input. 47 O LF PLL Loop Filter, Return to AVDD. 1 I = input, O = output.

Rev. 0 | Page 11 of 24 THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTERS (ADCS) There are four ADC channels in the AD1974 configured as two stereo pairs with differential inputs. The ADCs can operate at a nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs include on-board digital antialiasing filters with a 79 dB stop- band attenuation and a linear phase response, operating at an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz modes). Digital outputs are supplied through two serial data output pins (one for each stereo pair) as well as a common frame (ALRCLK) and bit clock (ABCLK). Alternatively, one of the time division multiplexed (TDM) modes can be used to access up to 16 channels on a single TDM data line. The ADCs must be driven from a differential signal source for best performance. The input pins of the ADCs connect to inter- nal switched capacitors. To isolate the external driving op amp from the glitches caused by the internal switched capacitors, each input pin should be isolated by using a series connected, external, 100 Ω resistor together with a 1 nF capacitor connected from each input to ground. This capacitor must be of high quality, for instance, a ceramic NPO capacitor or a polypropylene film capacitor. The differential inputs have a nominal common-mode voltage of 1.5 V . The voltage at the common-mode reference pin (CM) can be used to bias external op amps to buffer the input signals (see the Power Supply and Voltage Reference section). The inputs can also be ac-coupled and do not need an external dc bias to CM. A digital high-pass filter can be switched in line with the ADCs under serial control to remove residual dc offsets. It has a 1.4 Hz, 6 dB per octave cutoff at a 48 kHz sample rate. The cutoff fre- quency scales directly with sample frequency. The voltage at CM can be used to bias the external op amps that buffer the output signals (see the Power Supply and Voltage Reference section). CLOCK SIGNALS The on-chip PLL can be selected to reference the input sample rate from either the LRCLK or AUXLRCK pins or 256, 384, 512, or 768 times the sample rate, referenced to the 48 kHz mode from the MCLKI/XI pin. The default at power-up is 256 × fS from MCLKI. In 96 kHz mode, the master clock frequency stays at the same absolute frequency; therefore, the actual mul- tiplication rate is divided by 2. In 192 kHz mode, the actual multiplication rate is divided by 4. For example, if the AD1974 is programmed in 256 × f S mode, the frequency of the master clock input is 256 × 48 kHz = 12.288 MHz. If the AD1974 is then switched to 96 kHz operation (by writing to the SPI or I2C port), the frequency of the master clock should remain at 12.288 MHz (128 × fS). In 192 kHz mode, this becomes 64 × fS. The internal clock for the ADCs is 256 × fS for all clock modes. By default, the on-board PLL generates this internal master clock from an external clock. A direct 512 × f S (referenced to 48 kHz mode) master clock can be used for the ADCs if selected in the PLL and Clock Control 1 register. Note that it is not possible to use a direct clock for the ADCs set to the 192 kHz mode. It is required that the on-chip PLL be used in this mode. The PLL can be powered down in the PLL and Clock Control 0 register. To ensure reliable locking when changing PLL modes, or if the reference clock is unstable at power-on, power down the PLL and then power it back up when the reference clock has stabilized. The internal MCLK can be disabled in the PLL and Clock Control 0 register to reduce power dissipation when the AD1974 is idle. The clock should be stable before it is enabled. Unless a stand- alone mode is selected (see the Serial Control Port section), the clock is disabled by reset and must be enabled by writing to the SPI or I2C port for normal operation. To maintain the highest performance possible, it is recom- mended that the clock jitter of the internal master clock signal be limited to less than 300 ps rms time interval error (TIE). Even at these levels, extra noise or tones can appear in the outputs if the jitter spectrum contains large spectral peaks. If the internal PLL is not being used, it is highly recommended that an inde- pendent crystal oscillator generate the master clock. In addition, it is especially important that the clock signal should not be passed through an FPGA, CPLD, DSP , or other large digital chip before being applied to the AD1974. In most cases, this induces clock jitter due to the sharing of common power and ground connections with other unrelated digital output signals. When the PLL is used, jitter in the reference clock is attenuated above a certain frequency depending on the loop filter. RESET AND POWER-DOWN The reset pin sets all the control registers to their default settings. To avoid pops, reset does not power down the analog outputs. After reset is deasserted, and the PLL acquires a lock condition, an initialization routine runs inside the AD1974. This initializa- tion lasts for approximately 256 master clock cycles. The PLL and Clock Control 0 register and the ADC Control 1 register power down their respective sections using power down bits. All other register settings are retained. The PD/RST pin should be pulled low by an external resistor to guarantee proper startup.

of each pin in TDM and AUX Modes, see Table 12. available only in the 48 kHz/44.1 kHz/32 kHz sample rate.

256 BCLKs

32 BCLKs

Figure 6. ADC TDM (8-Channel I2S Mode. Table 12. Pin Function Changes in TDM and AUX Modes

32 BITS

Figure 7. 8-Channel AUX ADC Mode

Figure 8. 16-Channel AUX ADC Mode

second AD1974 is the device attached to the DSP TDM port. configuration with two external stereo ADCs. Figure 11 through Figure 13 show the serial mode formats. normal polarity. The default mode is I2S. Figure 9. ADC TDM Daisy-Chain Mode (256 fS ABCLK, Two AD1974 Daisy Chains) Figure 10. ADC TDM Daisy-Chain Mode (512 fS ABCLK, Two AD1974 Daisy Chains)

Note that the first setting in each control register parameter is the default setting. Table 14. Register Format Table 15. Register Addresses Description

0 PLL and Clock Control 0

1 PLL and Clock Control 1

2 AUXPORT Control 0

3 AUXPORT Control 1

4 AUXPORT Control 2

5 Reserved

6 Reserved

7 Reserved

8 Reserved

9 Reserved

10 Reserved

11 Reserved

12 Reserved

13 Reserved

14 ADC Control 0

15 ADC Control 1

16 ADC Control 2

Table 16. PLL and Clock Control 0

1 Power-down

11 Off

01 AUXLRCLK

10 ALRCLK

1 Enable: ADC active

Table 17. PLL and Clock Control 1

1 MCLK

1 Disabled

1 Locked

Table 18. AUXPORT Control 0

1 Reserved

101 Reserved

110 Reserved

111 Reserved

01 Reserved

10 ADC AUX mode (ADC-, TDM-coupled)

Table 19. AUXPORT Control 1

1 Left high

1 Master

1 Internally generated

1 Inverted

Table 20. AUXPORT Control 2 Table 21. ADC Control 0

1 Power down

1 Mute

Table 22. ADC Control 1

01 TDM (daisy chain)

10 ADC AUX mode (TDM-coupled)

1 Latch in at end of cycle (pipeline)

Table 23. ADC Control 2

1 Pulse (32-BCLK/channel)

1 Drive out on rising edge

by the PLL with the ALRCLK as the PLL reference frequency. Figure 15. Serial ADC Data Transmission in TDM Format Without ABCLK Figure 16. I2S Pipeline Mode in ADC Serial Data Transmission

filters for LR clock and master clock as the PLL reference are shown in Figure 18.

3 OP275

5 OP275

Figure 17. Typical ADC Input Filter Circuit Figure 18. Recommended Loop Filters for LRCLK or MCLK PLL Reference

Figure 19. 48-Lead Low Profile Quad Flat Package [LQFP] 2 Single-ended output; SPI control port. registered trademarks are the property of their respective owners.